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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Interrupt controller support for Galileo's GT64260. |
3 | * | |
4 | * Author: Chris Zankel <source@mvista.com> | |
5 | * Modified by: Mark A. Greer <mgreer@mvista.com> | |
6 | * | |
7 | * Based on sources from Rabeeh Khoury / Galileo Technology | |
8 | * | |
9 | * 2001 (c) MontaVista, Software, Inc. This file is licensed under | |
10 | * the terms of the GNU General Public License version 2. This program | |
11 | * is licensed "as is" without any warranty of any kind, whether express | |
12 | * or implied. | |
13 | */ | |
14 | ||
15 | /* | |
16 | * This file contains the specific functions to support the GT64260 | |
17 | * interrupt controller. | |
18 | * | |
19 | * The GT64260 has two main interrupt registers (high and low) that | |
20 | * summarizes the interrupts generated by the units of the GT64260. | |
21 | * Each bit is assigned to an interrupt number, where the low register | |
22 | * are assigned from IRQ0 to IRQ31 and the high cause register | |
23 | * from IRQ32 to IRQ63 | |
24 | * The GPP (General Purpose Port) interrupts are assigned from IRQ64 (GPP0) | |
25 | * to IRQ95 (GPP31). | |
26 | * get_irq() returns the lowest interrupt number that is currently asserted. | |
27 | * | |
28 | * Note: | |
29 | * - This driver does not initialize the GPP when used as an interrupt | |
30 | * input. | |
31 | */ | |
32 | ||
33 | #include <linux/stddef.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/sched.h> | |
37 | #include <linux/signal.h> | |
38 | #include <linux/stddef.h> | |
39 | #include <linux/delay.h> | |
40 | #include <linux/irq.h> | |
41 | ||
42 | #include <asm/io.h> | |
43 | #include <asm/system.h> | |
44 | #include <asm/irq.h> | |
45 | #include <asm/mv64x60.h> | |
fd582ec8 | 46 | #include <asm/machdep.h> |
1da177e4 LT |
47 | |
48 | #define CPU_INTR_STR "gt64260 cpu interface error" | |
49 | #define PCI0_INTR_STR "gt64260 pci 0 error" | |
50 | #define PCI1_INTR_STR "gt64260 pci 1 error" | |
51 | ||
52 | /* ========================== forward declaration ========================== */ | |
53 | ||
54 | static void gt64260_unmask_irq(unsigned int); | |
55 | static void gt64260_mask_irq(unsigned int); | |
56 | ||
57 | /* ========================== local declarations =========================== */ | |
58 | ||
59 | struct hw_interrupt_type gt64260_pic = { | |
60 | .typename = " gt64260_pic ", | |
61 | .enable = gt64260_unmask_irq, | |
62 | .disable = gt64260_mask_irq, | |
63 | .ack = gt64260_mask_irq, | |
64 | .end = gt64260_unmask_irq, | |
65 | }; | |
66 | ||
67 | u32 gt64260_irq_base = 0; /* GT64260 handles the next 96 IRQs from here */ | |
68 | ||
69 | static struct mv64x60_handle bh; | |
70 | ||
71 | /* gt64260_init_irq() | |
72 | * | |
73 | * This function initializes the interrupt controller. It assigns | |
74 | * all interrupts from IRQ0 to IRQ95 to the gt64260 interrupt controller. | |
75 | * | |
76 | * Note: | |
77 | * We register all GPP inputs as interrupt source, but disable them. | |
78 | */ | |
79 | void __init | |
80 | gt64260_init_irq(void) | |
81 | { | |
82 | int i; | |
83 | ||
84 | if (ppc_md.progress) | |
85 | ppc_md.progress("gt64260_init_irq: enter", 0x0); | |
86 | ||
87 | bh.v_base = mv64x60_get_bridge_vbase(); | |
88 | ||
89 | ppc_cached_irq_mask[0] = 0; | |
90 | ppc_cached_irq_mask[1] = 0x0f000000; /* Enable GPP intrs */ | |
91 | ppc_cached_irq_mask[2] = 0; | |
92 | ||
93 | /* disable all interrupts and clear current interrupts */ | |
94 | mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, ppc_cached_irq_mask[2]); | |
95 | mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, 0); | |
96 | mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_LO, ppc_cached_irq_mask[0]); | |
97 | mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_HI, ppc_cached_irq_mask[1]); | |
98 | ||
99 | /* use the gt64260 for all (possible) interrupt sources */ | |
100 | for (i = gt64260_irq_base; i < (gt64260_irq_base + 96); i++) | |
101 | irq_desc[i].handler = >64260_pic; | |
102 | ||
103 | if (ppc_md.progress) | |
104 | ppc_md.progress("gt64260_init_irq: exit", 0x0); | |
105 | } | |
106 | ||
107 | /* | |
108 | * gt64260_get_irq() | |
109 | * | |
110 | * This function returns the lowest interrupt number of all interrupts that | |
111 | * are currently asserted. | |
112 | * | |
113 | * Input Variable(s): | |
114 | * struct pt_regs* not used | |
115 | * | |
116 | * Output Variable(s): | |
117 | * None. | |
118 | * | |
119 | * Returns: | |
120 | * int <interrupt number> or -2 (bogus interrupt) | |
121 | */ | |
122 | int | |
123 | gt64260_get_irq(struct pt_regs *regs) | |
124 | { | |
125 | int irq; | |
126 | int irq_gpp; | |
127 | ||
128 | irq = mv64x60_read(&bh, GT64260_IC_MAIN_CAUSE_LO); | |
129 | irq = __ilog2((irq & 0x3dfffffe) & ppc_cached_irq_mask[0]); | |
130 | ||
131 | if (irq == -1) { | |
132 | irq = mv64x60_read(&bh, GT64260_IC_MAIN_CAUSE_HI); | |
133 | irq = __ilog2((irq & 0x0f000db7) & ppc_cached_irq_mask[1]); | |
134 | ||
135 | if (irq == -1) | |
136 | irq = -2; /* bogus interrupt, should never happen */ | |
137 | else { | |
138 | if (irq >= 24) { | |
139 | irq_gpp = mv64x60_read(&bh, | |
140 | MV64x60_GPP_INTR_CAUSE); | |
141 | irq_gpp = __ilog2(irq_gpp & | |
142 | ppc_cached_irq_mask[2]); | |
143 | ||
144 | if (irq_gpp == -1) | |
145 | irq = -2; | |
146 | else { | |
147 | irq = irq_gpp + 64; | |
148 | mv64x60_write(&bh, | |
149 | MV64x60_GPP_INTR_CAUSE, | |
150 | ~(1 << (irq - 64))); | |
151 | } | |
152 | } else | |
153 | irq += 32; | |
154 | } | |
155 | } | |
156 | ||
157 | (void)mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE); | |
158 | ||
159 | if (irq < 0) | |
160 | return (irq); | |
161 | else | |
162 | return (gt64260_irq_base + irq); | |
163 | } | |
164 | ||
165 | /* gt64260_unmask_irq() | |
166 | * | |
167 | * This function enables an interrupt. | |
168 | * | |
169 | * Input Variable(s): | |
170 | * unsigned int interrupt number (IRQ0...IRQ95). | |
171 | * | |
172 | * Output Variable(s): | |
173 | * None. | |
174 | * | |
175 | * Returns: | |
176 | * void | |
177 | */ | |
178 | static void | |
179 | gt64260_unmask_irq(unsigned int irq) | |
180 | { | |
181 | irq -= gt64260_irq_base; | |
182 | ||
183 | if (irq > 31) | |
184 | if (irq > 63) /* unmask GPP irq */ | |
185 | mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, | |
186 | ppc_cached_irq_mask[2] |= (1 << (irq - 64))); | |
187 | else /* mask high interrupt register */ | |
188 | mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_HI, | |
189 | ppc_cached_irq_mask[1] |= (1 << (irq - 32))); | |
190 | else /* mask low interrupt register */ | |
191 | mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_LO, | |
192 | ppc_cached_irq_mask[0] |= (1 << irq)); | |
193 | ||
194 | (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK); | |
195 | return; | |
196 | } | |
197 | ||
198 | /* gt64260_mask_irq() | |
199 | * | |
200 | * This function disables the requested interrupt. | |
201 | * | |
202 | * Input Variable(s): | |
203 | * unsigned int interrupt number (IRQ0...IRQ95). | |
204 | * | |
205 | * Output Variable(s): | |
206 | * None. | |
207 | * | |
208 | * Returns: | |
209 | * void | |
210 | */ | |
211 | static void | |
212 | gt64260_mask_irq(unsigned int irq) | |
213 | { | |
214 | irq -= gt64260_irq_base; | |
215 | ||
216 | if (irq > 31) | |
217 | if (irq > 63) /* mask GPP irq */ | |
218 | mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, | |
219 | ppc_cached_irq_mask[2] &= ~(1 << (irq - 64))); | |
220 | else /* mask high interrupt register */ | |
221 | mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_HI, | |
222 | ppc_cached_irq_mask[1] &= ~(1 << (irq - 32))); | |
223 | else /* mask low interrupt register */ | |
224 | mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_LO, | |
225 | ppc_cached_irq_mask[0] &= ~(1 << irq)); | |
226 | ||
227 | (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK); | |
228 | return; | |
229 | } | |
230 | ||
231 | static irqreturn_t | |
232 | gt64260_cpu_error_int_handler(int irq, void *dev_id, struct pt_regs *regs) | |
233 | { | |
234 | printk(KERN_ERR "gt64260_cpu_error_int_handler: %s 0x%08x\n", | |
235 | "Error on CPU interface - Cause regiser", | |
236 | mv64x60_read(&bh, MV64x60_CPU_ERR_CAUSE)); | |
237 | printk(KERN_ERR "\tCPU error register dump:\n"); | |
238 | printk(KERN_ERR "\tAddress low 0x%08x\n", | |
239 | mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_LO)); | |
240 | printk(KERN_ERR "\tAddress high 0x%08x\n", | |
241 | mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_HI)); | |
242 | printk(KERN_ERR "\tData low 0x%08x\n", | |
243 | mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_LO)); | |
244 | printk(KERN_ERR "\tData high 0x%08x\n", | |
245 | mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_HI)); | |
246 | printk(KERN_ERR "\tParity 0x%08x\n", | |
247 | mv64x60_read(&bh, MV64x60_CPU_ERR_PARITY)); | |
248 | mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0); | |
249 | return IRQ_HANDLED; | |
250 | } | |
251 | ||
252 | static irqreturn_t | |
253 | gt64260_pci_error_int_handler(int irq, void *dev_id, struct pt_regs *regs) | |
254 | { | |
255 | u32 val; | |
256 | unsigned int pci_bus = (unsigned int)dev_id; | |
257 | ||
258 | if (pci_bus == 0) { /* Error on PCI 0 */ | |
259 | val = mv64x60_read(&bh, MV64x60_PCI0_ERR_CAUSE); | |
260 | printk(KERN_ERR "%s: Error in PCI %d Interface\n", | |
261 | "gt64260_pci_error_int_handler", pci_bus); | |
262 | printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus); | |
263 | printk(KERN_ERR "\tCause register 0x%08x\n", val); | |
264 | printk(KERN_ERR "\tAddress Low 0x%08x\n", | |
265 | mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_LO)); | |
266 | printk(KERN_ERR "\tAddress High 0x%08x\n", | |
267 | mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_HI)); | |
268 | printk(KERN_ERR "\tAttribute 0x%08x\n", | |
269 | mv64x60_read(&bh, MV64x60_PCI0_ERR_DATA_LO)); | |
270 | printk(KERN_ERR "\tCommand 0x%08x\n", | |
271 | mv64x60_read(&bh, MV64x60_PCI0_ERR_CMD)); | |
272 | mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, ~val); | |
273 | } | |
274 | if (pci_bus == 1) { /* Error on PCI 1 */ | |
275 | val = mv64x60_read(&bh, MV64x60_PCI1_ERR_CAUSE); | |
276 | printk(KERN_ERR "%s: Error in PCI %d Interface\n", | |
277 | "gt64260_pci_error_int_handler", pci_bus); | |
278 | printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus); | |
279 | printk(KERN_ERR "\tCause register 0x%08x\n", val); | |
280 | printk(KERN_ERR "\tAddress Low 0x%08x\n", | |
281 | mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_LO)); | |
282 | printk(KERN_ERR "\tAddress High 0x%08x\n", | |
283 | mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_HI)); | |
284 | printk(KERN_ERR "\tAttribute 0x%08x\n", | |
285 | mv64x60_read(&bh, MV64x60_PCI1_ERR_DATA_LO)); | |
286 | printk(KERN_ERR "\tCommand 0x%08x\n", | |
287 | mv64x60_read(&bh, MV64x60_PCI1_ERR_CMD)); | |
288 | mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, ~val); | |
289 | } | |
290 | return IRQ_HANDLED; | |
291 | } | |
292 | ||
293 | static int __init | |
294 | gt64260_register_hdlrs(void) | |
295 | { | |
296 | int rc; | |
297 | ||
298 | /* Register CPU interface error interrupt handler */ | |
299 | if ((rc = request_irq(MV64x60_IRQ_CPU_ERR, | |
300 | gt64260_cpu_error_int_handler, SA_INTERRUPT, CPU_INTR_STR, 0))) | |
301 | printk(KERN_WARNING "Can't register cpu error handler: %d", rc); | |
302 | ||
303 | mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0); | |
304 | mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0x000000fe); | |
305 | ||
306 | /* Register PCI 0 error interrupt handler */ | |
307 | if ((rc = request_irq(MV64360_IRQ_PCI0, gt64260_pci_error_int_handler, | |
308 | SA_INTERRUPT, PCI0_INTR_STR, (void *)0))) | |
309 | printk(KERN_WARNING "Can't register pci 0 error handler: %d", | |
310 | rc); | |
311 | ||
312 | mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0); | |
313 | mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0x003c0c24); | |
314 | ||
315 | /* Register PCI 1 error interrupt handler */ | |
316 | if ((rc = request_irq(MV64360_IRQ_PCI1, gt64260_pci_error_int_handler, | |
317 | SA_INTERRUPT, PCI1_INTR_STR, (void *)1))) | |
318 | printk(KERN_WARNING "Can't register pci 1 error handler: %d", | |
319 | rc); | |
320 | ||
321 | mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0); | |
322 | mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0x003c0c24); | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
327 | arch_initcall(gt64260_register_hdlrs); |