[net-next-2.6.git] / arch / ppc / platforms / 85xx / mpc85xx_cds_common.c

/*
 * arch/ppc/platform/85xx/mpc85xx_cds_common.c
 *
 * MPC85xx CDS board specific routines
 *
 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
 *
 * Copyright 2004 Freescale Semiconductor, Inc
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/config.h>
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/major.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/serial.h>
#include <linux/module.h>
#include <linux/root_dev.h>
#include <linux/initrd.h>
#include <linux/tty.h>
#include <linux/serial_core.h>
#include <linux/fsl_devices.h>

#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/atomic.h>
#include <asm/time.h>
#include <asm/todc.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/open_pic.h>
#include <asm/i8259.h>
#include <asm/bootinfo.h>
#include <asm/pci-bridge.h>
#include <asm/mpc85xx.h>
#include <asm/irq.h>
#include <asm/immap_85xx.h>
#include <asm/cpm2.h>
#include <asm/ppc_sys.h>
#include <asm/kgdb.h>

#include <mm/mmu_decl.h>
#include <syslib/cpm2_pic.h>
#include <syslib/ppc85xx_common.h>
#include <syslib/ppc85xx_setup.h>


#ifndef CONFIG_PCI
unsigned long isa_io_base = 0;
unsigned long isa_mem_base = 0;
#endif

extern unsigned long total_memory;      /* in mm/init */

unsigned char __res[sizeof (bd_t)];

static int cds_pci_slot = 2;
static volatile u8 * cadmus;

/* Internal interrupts are all Level Sensitive, and Positive Polarity */
static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
	MPC85XX_INTERNAL_IRQ_SENSES,
#if defined(CONFIG_PCI)
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* External 0: PCI1 slot */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* External 1: PCI1 slot */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* External 2: PCI1 slot */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* External 3: PCI1 slot */
#else
	0x0,						/* External  0: */
	0x0,						/* External  1: */
	0x0,						/* External  2: */
	0x0,						/* External  3: */
#endif
	0x0,						/* External  4: */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* External  5: PHY */
	0x0,						/* External  6: */
	0x0,						/* External  7: */
	0x0,						/* External  8: */
	0x0,						/* External  9: */
	0x0,						/* External 10: */
#if defined(CONFIG_85xx_PCI2) && defined(CONFIG_PCI)
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* External 11: PCI2 slot 0 */
#else
	0x0,						/* External 11: */
#endif
};

/* ************************************************************************ */
int
mpc85xx_cds_show_cpuinfo(struct seq_file *m)
{
	uint pvid, svid, phid1;
	uint memsize = total_memory;
	bd_t *binfo = (bd_t *) __res;
	unsigned int freq;

	/* get the core frequency */
	freq = binfo->bi_intfreq;

	pvid = mfspr(SPRN_PVR);
	svid = mfspr(SPRN_SVR);

	seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
	seq_printf(m, "Machine\t\t: CDS - MPC%s (%x)\n", cur_ppc_sys_spec->ppc_sys_name, cadmus[CM_VER]);
	seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
	seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
	seq_printf(m, "SVR\t\t: 0x%x\n", svid);

	/* Display cpu Pll setting */
	phid1 = mfspr(SPRN_HID1);
	seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));

	/* Display the amount of memory */
	seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));

	return 0;
}

#ifdef CONFIG_CPM2
static void cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
{
	while((irq = cpm2_get_irq(regs)) >= 0)
		__do_IRQ(irq, regs);
}

static struct irqaction cpm2_irqaction = {
	.handler = cpm2_cascade,
	.flags = SA_INTERRUPT,
	.mask = CPU_MASK_NONE,
	.name = "cpm2_cascade",
};
#endif /* CONFIG_CPM2 */

void __init
mpc85xx_cds_init_IRQ(void)
{
	bd_t *binfo = (bd_t *) __res;
	int i;

	/* Determine the Physical Address of the OpenPIC regs */
	phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
	OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
	OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses;
	OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);

	/* Skip reserved space and internal sources */
#ifdef CONFIG_MPC8548
	openpic_set_sources(0, 48, OpenPIC_Addr + 0x10200);
#else
	openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
#endif
	/* Map PIC IRQs 0-11 */
	openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);

	/* we let openpic interrupts starting from an offset, to
	 * leave space for cascading interrupts underneath.
	 */
	openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);

#ifdef CONFIG_PCI
	openpic_hookup_cascade(PIRQ0A, "82c59 cascade", i8259_irq);

	i8259_init(0, 0);
#endif

#ifdef CONFIG_CPM2
	/* Setup CPM2 PIC */
        cpm2_init_IRQ();

	setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
#endif

	return;
}

#ifdef CONFIG_PCI
/*
 * interrupt routing
 */
int
mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
	struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);

	if (!hose->index)
	{
		/* Handle PCI1 interrupts */
		char pci_irq_table[][4] =
			/*
			 *      PCI IDSEL/INTPIN->INTLINE
			 *        A      B      C      D
			 */

			/* Note IRQ assignment for slots is based on which slot the elysium is
			 * in -- in this setup elysium is in slot #2 (this PIRQA as first
			 * interrupt on slot */
		{
			{ 0, 1, 2, 3 }, /* 16 - PMC */
			{ 0, 1, 2, 3 }, /* 17 P2P (Tsi320) */
			{ 0, 1, 2, 3 }, /* 18 - Slot 1 */
			{ 1, 2, 3, 0 }, /* 19 - Slot 2 */
			{ 2, 3, 0, 1 }, /* 20 - Slot 3 */
			{ 3, 0, 1, 2 }, /* 21 - Slot 4 */
		};

		const long min_idsel = 16, max_idsel = 21, irqs_per_slot = 4;
		int i, j;

		for (i = 0; i < 6; i++)
			for (j = 0; j < 4; j++)
				pci_irq_table[i][j] =
					((pci_irq_table[i][j] + 5 -
					  cds_pci_slot) & 0x3) + PIRQ0A;

		return PCI_IRQ_TABLE_LOOKUP;
	} else {
		/* Handle PCI2 interrupts (if we have one) */
		char pci_irq_table[][4] =
		{
			/*
			 * We only have one slot and one interrupt
			 * going to PIRQA - PIRQD */
			{ PIRQ1A, PIRQ1A, PIRQ1A, PIRQ1A }, /* 21 - slot 0 */
		};

		const long min_idsel = 21, max_idsel = 21, irqs_per_slot = 4;

		return PCI_IRQ_TABLE_LOOKUP;
	}
}

#define ARCADIA_HOST_BRIDGE_IDSEL	17
#define ARCADIA_2ND_BRIDGE_IDSEL	3

extern int mpc85xx_pci1_last_busno;

int
mpc85xx_exclude_device(u_char bus, u_char devfn)
{
	if (bus == 0 && PCI_SLOT(devfn) == 0)
		return PCIBIOS_DEVICE_NOT_FOUND;
#ifdef CONFIG_85xx_PCI2
	if (mpc85xx_pci1_last_busno)
		if (bus == (mpc85xx_pci1_last_busno + 1) && PCI_SLOT(devfn) == 0)
			return PCIBIOS_DEVICE_NOT_FOUND;
#endif
	/* We explicitly do not go past the Tundra 320 Bridge */
	if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
		return PCIBIOS_DEVICE_NOT_FOUND;
	if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
		return PCIBIOS_DEVICE_NOT_FOUND;
	else
		return PCIBIOS_SUCCESSFUL;
}

void __init
mpc85xx_cds_enable_via(struct pci_controller *hose)
{
	u32 pci_class;
	u16 vid, did;

	early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
	if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
		return;

	/* Configure P2P so that we can reach bus 1 */
	early_write_config_byte(hose, 0, 0x88, PCI_PRIMARY_BUS, 0);
	early_write_config_byte(hose, 0, 0x88, PCI_SECONDARY_BUS, 1);
	early_write_config_byte(hose, 0, 0x88, PCI_SUBORDINATE_BUS, 0xff);

	early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
	early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);

	if ((vid != PCI_VENDOR_ID_VIA) ||
			(did != PCI_DEVICE_ID_VIA_82C686))
		return;

	/* Enable USB and IDE functions */
	early_write_config_byte(hose, 1, 0x10, 0x48, 0x08);
}

void __init
mpc85xx_cds_fixup_via(struct pci_controller *hose)
{
	u32 pci_class;
	u16 vid, did;

	early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
	if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
		return;

	/*
	 * Force the backplane P2P bridge to have a window
	 * open from 0x00000000-0x00001fff in PCI I/O space.
	 * This allows legacy I/O (i8259, etc) on the VIA
	 * southbridge to be accessed.
	 */
	early_write_config_byte(hose, 0, 0x88, PCI_IO_BASE, 0x00);
	early_write_config_word(hose, 0, 0x88, PCI_IO_BASE_UPPER16, 0x0000);
	early_write_config_byte(hose, 0, 0x88, PCI_IO_LIMIT, 0x10);
	early_write_config_word(hose, 0, 0x88, PCI_IO_LIMIT_UPPER16, 0x0000);

	early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
	early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
	if ((vid != PCI_VENDOR_ID_VIA) ||
			(did != PCI_DEVICE_ID_VIA_82C686))
		return;

	/*
	 * Since the P2P window was forced to cover the fixed
	 * legacy I/O addresses, it is necessary to manually
	 * place the base addresses for the IDE and USB functions
	 * within this window.
	 */
	/* Function 1, IDE */
	early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_0, 0x1ff8);
	early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_1, 0x1ff4);
	early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_2, 0x1fe8);
	early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_3, 0x1fe4);
	early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_4, 0x1fd0);

	/* Function 2, USB ports 0-1 */
	early_write_config_dword(hose, 1, 0x12, PCI_BASE_ADDRESS_4, 0x1fa0);

	/* Function 3, USB ports 2-3 */
	early_write_config_dword(hose, 1, 0x13, PCI_BASE_ADDRESS_4, 0x1f80);

	/* Function 5, Power Management */
	early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_0, 0x1e00);
	early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_1, 0x1dfc);
	early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_2, 0x1df8);

	/* Function 6, AC97 Interface */
	early_write_config_dword(hose, 1, 0x16, PCI_BASE_ADDRESS_0, 0x1c00);
}

void __init
mpc85xx_cds_pcibios_fixup(void)
{
        struct pci_dev *dev = NULL;
	u_char		c;

        if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
                                        PCI_DEVICE_ID_VIA_82C586_1, NULL))) {
                /*
                 * U-Boot does not set the enable bits
                 * for the IDE device. Force them on here.
                 */
                pci_read_config_byte(dev, 0x40, &c);
                c |= 0x03; /* IDE: Chip Enable Bits */
                pci_write_config_byte(dev, 0x40, c);

		/*
		 * Since only primary interface works, force the
		 * IDE function to standard primary IDE interrupt
		 * w/ 8259 offset
		 */
                dev->irq = 14;
                pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
        }

	/*
	 * Force legacy USB interrupt routing
	 */
        if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
                                        PCI_DEVICE_ID_VIA_82C586_2, NULL))) {
                dev->irq = 10;
                pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10);
        }

        if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
                                        PCI_DEVICE_ID_VIA_82C586_2, dev))) {
                dev->irq = 11;
                pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
        }
}
#endif /* CONFIG_PCI */

TODC_ALLOC();

static const char *GFAR_PHY_0 = "phy0:0";
static const char *GFAR_PHY_1 = "phy0:1";

/* ************************************************************************
 *
 * Setup the architecture
 *
 */
static void __init
mpc85xx_cds_setup_arch(void)
{
	bd_t *binfo = (bd_t *) __res;
	unsigned int freq;
	struct gianfar_platform_data *pdata;
	struct gianfar_mdio_data *mdata;

	/* get the core frequency */
	freq = binfo->bi_intfreq;

	printk("mpc85xx_cds_setup_arch\n");

#ifdef CONFIG_CPM2
	cpm2_reset();
#endif

	cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
	cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
	printk("CDS Version = %x in PCI slot %d\n", cadmus[CM_VER], cds_pci_slot);

	/* Setup TODC access */
	TODC_INIT(TODC_TYPE_DS1743,
			0,
			0,
			ioremap(CDS_RTC_ADDR, CDS_RTC_SIZE),
			8);

	/* Set loops_per_jiffy to a half-way reasonable value,
	   for use until calibrate_delay gets called. */
	loops_per_jiffy = freq / HZ;

#ifdef CONFIG_PCI
	/* VIA IDE configuration */
        ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup;

	/* setup PCI host bridges */
	mpc85xx_setup_hose();
#endif

#ifdef CONFIG_SERIAL_8250
	mpc85xx_early_serial_map();
#endif

#ifdef CONFIG_SERIAL_TEXT_DEBUG
	/* Invalidate the entry we stole earlier the serial ports
	 * should be properly mapped */
	invalidate_tlbcam_entry(num_tlbcam_entries - 1);
#endif

	/* setup the board related info for the MDIO bus */
	mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);

	mdata->irq[0] = MPC85xx_IRQ_EXT5;
	mdata->irq[1] = MPC85xx_IRQ_EXT5;
	mdata->irq[2] = -1;
	mdata->irq[3] = -1;
	mdata->irq[31] = -1;
	mdata->paddr += binfo->bi_immr_base;

	/* setup the board related information for the enet controllers */
	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
	if (pdata) {
		pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
		pdata->bus_id = GFAR_PHY_0;
		memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
	}

	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
	if (pdata) {
		pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
		pdata->bus_id = GFAR_PHY_1;
		memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
	}

	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC1);
	if (pdata) {
		pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
		pdata->bus_id = GFAR_PHY_0;
		memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
	}

	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC2);
	if (pdata) {
		pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
		pdata->bus_id = GFAR_PHY_1;
		memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
	}

	ppc_sys_device_remove(MPC85xx_eTSEC3);
	ppc_sys_device_remove(MPC85xx_eTSEC4);

#ifdef CONFIG_BLK_DEV_INITRD
	if (initrd_start)
		ROOT_DEV = Root_RAM0;
	else
#endif
#ifdef  CONFIG_ROOT_NFS
		ROOT_DEV = Root_NFS;
#else
	ROOT_DEV = Root_HDA1;
#endif
}

/* ************************************************************************ */
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
              unsigned long r6, unsigned long r7)
{
	/* parse_bootinfo must always be called first */
	parse_bootinfo(find_bootinfo());

	/*
	 * If we were passed in a board information, copy it into the
	 * residual data area.
	 */
	if (r3) {
		memcpy((void *) __res, (void *) (r3 + KERNELBASE),
				sizeof (bd_t));

	}
#ifdef CONFIG_SERIAL_TEXT_DEBUG
	{
		bd_t *binfo = (bd_t *) __res;
		struct uart_port p;

		/* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
		settlbcam(num_tlbcam_entries - 1, binfo->bi_immr_base,
				binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);

		memset(&p, 0, sizeof (p));
		p.iotype = SERIAL_IO_MEM;
		p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
		p.uartclk = binfo->bi_busfreq;

		gen550_init(0, &p);

		memset(&p, 0, sizeof (p));
		p.iotype = SERIAL_IO_MEM;
		p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
		p.uartclk = binfo->bi_busfreq;

		gen550_init(1, &p);
	}
#endif

#if defined(CONFIG_BLK_DEV_INITRD)
	/*
	 * If the init RAM disk has been configured in, and there's a valid
	 * starting address for it, set it up.
	 */
	if (r4) {
		initrd_start = r4 + KERNELBASE;
		initrd_end = r5 + KERNELBASE;
	}
#endif /* CONFIG_BLK_DEV_INITRD */

	/* Copy the kernel command line arguments to a safe place. */

	if (r6) {
		*(char *) (r7 + KERNELBASE) = 0;
		strcpy(cmd_line, (char *) (r6 + KERNELBASE));
	}

	identify_ppc_sys_by_id(mfspr(SPRN_SVR));

	/* setup the PowerPC module struct */
	ppc_md.setup_arch = mpc85xx_cds_setup_arch;
	ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo;

	ppc_md.init_IRQ = mpc85xx_cds_init_IRQ;
	ppc_md.get_irq = openpic_get_irq;

	ppc_md.restart = mpc85xx_restart;
	ppc_md.power_off = mpc85xx_power_off;
	ppc_md.halt = mpc85xx_halt;

	ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;

	ppc_md.calibrate_decr = mpc85xx_calibrate_decr;

	ppc_md.time_init = todc_time_init;
	ppc_md.set_rtc_time = todc_set_rtc_time;
	ppc_md.get_rtc_time = todc_get_rtc_time;

	ppc_md.nvram_read_val = todc_direct_read_val;
	ppc_md.nvram_write_val = todc_direct_write_val;

#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
	ppc_md.progress = gen550_progress;
#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
	ppc_md.early_serial_map = mpc85xx_early_serial_map;
#endif	/* CONFIG_SERIAL_8250 && CONFIG_KGDB */

	if (ppc_md.progress)
		ppc_md.progress("mpc85xx_cds_init(): exit", 0);

	return;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* arch/ppc/platform/85xx/mpc85xx_cds_common.c
	3	*
	4	* MPC85xx CDS board specific routines
	5	*
4c8d3d99	6	* Maintainer: Kumar Gala <galak@kernel.crashing.org>
1da177e4 LT	7	*
	8	* Copyright 2004 Freescale Semiconductor, Inc
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*/
	15
	16	#include <linux/config.h>
	17	#include <linux/stddef.h>
	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
	20	#include <linux/errno.h>
	21	#include <linux/reboot.h>
	22	#include <linux/pci.h>
	23	#include <linux/kdev_t.h>
	24	#include <linux/major.h>
	25	#include <linux/console.h>
	26	#include <linux/delay.h>
1da177e4 LT	27	#include <linux/seq_file.h>
	28	#include <linux/serial.h>
	29	#include <linux/module.h>
	30	#include <linux/root_dev.h>
	31	#include <linux/initrd.h>
	32	#include <linux/tty.h>
	33	#include <linux/serial_core.h>
	34	#include <linux/fsl_devices.h>
	35
	36	#include <asm/system.h>
	37	#include <asm/pgtable.h>
	38	#include <asm/page.h>
	39	#include <asm/atomic.h>
	40	#include <asm/time.h>
	41	#include <asm/todc.h>
	42	#include <asm/io.h>
	43	#include <asm/machdep.h>
1da177e4	44	#include <asm/open_pic.h>
ed369596	45	#include <asm/i8259.h>
1da177e4 LT	46	#include <asm/bootinfo.h>
	47	#include <asm/pci-bridge.h>
	48	#include <asm/mpc85xx.h>
	49	#include <asm/irq.h>
	50	#include <asm/immap_85xx.h>
d054b5ac	51	#include <asm/cpm2.h>
1da177e4 LT	52	#include <asm/ppc_sys.h>
	53	#include <asm/kgdb.h>
	54
	55	#include <mm/mmu_decl.h>
	56	#include <syslib/cpm2_pic.h>
	57	#include <syslib/ppc85xx_common.h>
	58	#include <syslib/ppc85xx_setup.h>
	59
	60
	61	#ifndef CONFIG_PCI
	62	unsigned long isa_io_base = 0;
	63	unsigned long isa_mem_base = 0;
	64	#endif
	65
	66	extern unsigned long total_memory; /* in mm/init */
	67
	68	unsigned char __res[sizeof (bd_t)];
	69
	70	static int cds_pci_slot = 2;
	71	static volatile u8 * cadmus;
	72
	73	/* Internal interrupts are all Level Sensitive, and Positive Polarity */
1da177e4	74	static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
65145e06	75	MPC85XX_INTERNAL_IRQ_SENSES,
1da177e4 LT	76	#if defined(CONFIG_PCI)
	77	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */
	78	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */
	79	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* External 2: PCI1 slot */
	80	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* External 3: PCI1 slot */
	81	#else
	82	0x0, /* External 0: */
	83	0x0, /* External 1: */
	84	0x0, /* External 2: */
	85	0x0, /* External 3: */
	86	#endif
	87	0x0, /* External 4: */
	88	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
	89	0x0, /* External 6: */
	90	0x0, /* External 7: */
	91	0x0, /* External 8: */
	92	0x0, /* External 9: */
	93	0x0, /* External 10: */
	94	#if defined(CONFIG_85xx_PCI2) && defined(CONFIG_PCI)
	95	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* External 11: PCI2 slot 0 */
	96	#else
	97	0x0, /* External 11: */
	98	#endif
	99	};
	100
	101	/* ************************************************************************ */
	102	int
	103	mpc85xx_cds_show_cpuinfo(struct seq_file *m)
	104	{
	105	uint pvid, svid, phid1;
	106	uint memsize = total_memory;
	107	bd_t binfo = (bd_t ) __res;
	108	unsigned int freq;
	109
	110	/* get the core frequency */
	111	freq = binfo->bi_intfreq;
	112
	113	pvid = mfspr(SPRN_PVR);
	114	svid = mfspr(SPRN_SVR);
	115
	116	seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
	117	seq_printf(m, "Machine\t\t: CDS - MPC%s (%x)\n", cur_ppc_sys_spec->ppc_sys_name, cadmus[CM_VER]);
	118	seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
	119	seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
	120	seq_printf(m, "SVR\t\t: 0x%x\n", svid);
	121
	122	/* Display cpu Pll setting */
	123	phid1 = mfspr(SPRN_HID1);
	124	seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
	125
	126	/* Display the amount of memory */
	127	seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
	128
	129	return 0;
	130	}
	131
	132	#ifdef CONFIG_CPM2
	133	static void cpm2_cascade(int irq, void dev_id, struct pt_regs regs)
	134	{
	135	while((irq = cpm2_get_irq(regs)) >= 0)
	136	__do_IRQ(irq, regs);
	137	}
	138
	139	static struct irqaction cpm2_irqaction = {
140	.handler = cpm2_cascade,
141	.flags = SA_INTERRUPT,
142	.mask = CPU_MASK_NONE,
143	.name = "cpm2_cascade",
144	};
145	#endif /* CONFIG_CPM2 */
146
147	void __init
148	mpc85xx_cds_init_IRQ(void)
149	{
150	bd_t binfo = (bd_t ) __res;
f1b04770	151	int i;
1da177e4 LT	152
	153	/* Determine the Physical Address of the OpenPIC regs */
	154	phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
	155	OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
	156	OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses;
	157	OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);
	158
	159	/* Skip reserved space and internal sources */
65145e06 KG	160	#ifdef CONFIG_MPC8548
	161	openpic_set_sources(0, 48, OpenPIC_Addr + 0x10200);
	162	#else
1da177e4	163	openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
65145e06	164	#endif
1da177e4	165	/* Map PIC IRQs 0-11 */
65145e06	166	openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
1da177e4 LT	167
	168	/* we let openpic interrupts starting from an offset, to
	169	* leave space for cascading interrupts underneath.
	170	*/
	171	openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
	172
6cf2b3fc	173	#ifdef CONFIG_PCI
ed369596 KG	174	openpic_hookup_cascade(PIRQ0A, "82c59 cascade", i8259_irq);
ed369596 KG	175
f9bd170a	176	i8259_init(0, 0);
6cf2b3fc	177	#endif
ed369596	178
1da177e4 LT	179	#ifdef CONFIG_CPM2
	180	/* Setup CPM2 PIC */
	181	cpm2_init_IRQ();
	182
	183	setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
	184	#endif
	185
	186	return;
	187	}
	188
	189	#ifdef CONFIG_PCI
	190	/*
	191	* interrupt routing
	192	*/
	193	int
	194	mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
	195	{
	196	struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
	197
	198	if (!hose->index)
	199	{
	200	/* Handle PCI1 interrupts */
	201	char pci_irq_table[][4] =
	202	/*
	203	* PCI IDSEL/INTPIN->INTLINE
	204	* A B C D
	205	*/
	206
	207	/* Note IRQ assignment for slots is based on which slot the elysium is
	208	* in -- in this setup elysium is in slot #2 (this PIRQA as first
	209	* interrupt on slot */
	210	{
	211	{ 0, 1, 2, 3 }, /* 16 - PMC */
ed369596	212	{ 0, 1, 2, 3 }, /* 17 P2P (Tsi320) */
1da177e4 LT	213	{ 0, 1, 2, 3 }, /* 18 - Slot 1 */
	214	{ 1, 2, 3, 0 }, /* 19 - Slot 2 */
	215	{ 2, 3, 0, 1 }, /* 20 - Slot 3 */
	216	{ 3, 0, 1, 2 }, /* 21 - Slot 4 */
	217	};
	218
	219	const long min_idsel = 16, max_idsel = 21, irqs_per_slot = 4;
	220	int i, j;
	221
	222	for (i = 0; i < 6; i++)
	223	for (j = 0; j < 4; j++)
	224	pci_irq_table[i][j] =
	225	((pci_irq_table[i][j] + 5 -
	226	cds_pci_slot) & 0x3) + PIRQ0A;
	227
	228	return PCI_IRQ_TABLE_LOOKUP;
	229	} else {
	230	/* Handle PCI2 interrupts (if we have one) */
	231	char pci_irq_table[][4] =
	232	{
	233	/*
	234	* We only have one slot and one interrupt
	235	* going to PIRQA - PIRQD */
	236	{ PIRQ1A, PIRQ1A, PIRQ1A, PIRQ1A }, /* 21 - slot 0 */
	237	};
	238
	239	const long min_idsel = 21, max_idsel = 21, irqs_per_slot = 4;
	240
	241	return PCI_IRQ_TABLE_LOOKUP;
	242	}
	243	}
	244
	245	#define ARCADIA_HOST_BRIDGE_IDSEL 17
	246	#define ARCADIA_2ND_BRIDGE_IDSEL 3
	247
	248	extern int mpc85xx_pci1_last_busno;
	249
	250	int
	251	mpc85xx_exclude_device(u_char bus, u_char devfn)
	252	{
	253	if (bus == 0 && PCI_SLOT(devfn) == 0)
	254	return PCIBIOS_DEVICE_NOT_FOUND;
	255	#ifdef CONFIG_85xx_PCI2
	256	if (mpc85xx_pci1_last_busno)
	257	if (bus == (mpc85xx_pci1_last_busno + 1) && PCI_SLOT(devfn) == 0)
	258	return PCIBIOS_DEVICE_NOT_FOUND;
	259	#endif
	260	/* We explicitly do not go past the Tundra 320 Bridge */
ed369596	261	if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
1da177e4 LT	262	return PCIBIOS_DEVICE_NOT_FOUND;
	263	if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
	264	return PCIBIOS_DEVICE_NOT_FOUND;
	265	else
	266	return PCIBIOS_SUCCESSFUL;
	267	}
ed369596 KG	268
	269	void __init
	270	mpc85xx_cds_enable_via(struct pci_controller *hose)
	271	{
	272	u32 pci_class;
	273	u16 vid, did;
	274
	275	early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
	276	if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
	277	return;
	278
	279	/* Configure P2P so that we can reach bus 1 */
	280	early_write_config_byte(hose, 0, 0x88, PCI_PRIMARY_BUS, 0);
	281	early_write_config_byte(hose, 0, 0x88, PCI_SECONDARY_BUS, 1);
	282	early_write_config_byte(hose, 0, 0x88, PCI_SUBORDINATE_BUS, 0xff);
	283
	284	early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
	285	early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
	286
	287	if ((vid != PCI_VENDOR_ID_VIA) \|\|
	288	(did != PCI_DEVICE_ID_VIA_82C686))
	289	return;
	290
	291	/* Enable USB and IDE functions */
	292	early_write_config_byte(hose, 1, 0x10, 0x48, 0x08);
	293	}
	294
	295	void __init
	296	mpc85xx_cds_fixup_via(struct pci_controller *hose)
	297	{
	298	u32 pci_class;
	299	u16 vid, did;
	300
	301	early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
	302	if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
	303	return;
	304
	305	/*
	306	* Force the backplane P2P bridge to have a window
	307	* open from 0x00000000-0x00001fff in PCI I/O space.
	308	* This allows legacy I/O (i8259, etc) on the VIA
	309	* southbridge to be accessed.
	310	*/
	311	early_write_config_byte(hose, 0, 0x88, PCI_IO_BASE, 0x00);
	312	early_write_config_word(hose, 0, 0x88, PCI_IO_BASE_UPPER16, 0x0000);
	313	early_write_config_byte(hose, 0, 0x88, PCI_IO_LIMIT, 0x10);
	314	early_write_config_word(hose, 0, 0x88, PCI_IO_LIMIT_UPPER16, 0x0000);
	315
	316	early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
	317	early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
	318	if ((vid != PCI_VENDOR_ID_VIA) \|\|
	319	(did != PCI_DEVICE_ID_VIA_82C686))
	320	return;
	321
	322	/*
	323	* Since the P2P window was forced to cover the fixed
	324	* legacy I/O addresses, it is necessary to manually
	325	* place the base addresses for the IDE and USB functions
	326	* within this window.
	327	*/
	328	/* Function 1, IDE */
	329	early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_0, 0x1ff8);
	330	early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_1, 0x1ff4);
	331	early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_2, 0x1fe8);
332	early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_3, 0x1fe4);
333	early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_4, 0x1fd0);
334
335	/* Function 2, USB ports 0-1 */
336	early_write_config_dword(hose, 1, 0x12, PCI_BASE_ADDRESS_4, 0x1fa0);
337
338	/* Function 3, USB ports 2-3 */
339	early_write_config_dword(hose, 1, 0x13, PCI_BASE_ADDRESS_4, 0x1f80);
340
341	/* Function 5, Power Management */
342	early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_0, 0x1e00);
343	early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_1, 0x1dfc);
344	early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_2, 0x1df8);
345
346	/* Function 6, AC97 Interface */
347	early_write_config_dword(hose, 1, 0x16, PCI_BASE_ADDRESS_0, 0x1c00);
348	}
349
350	void __init
351	mpc85xx_cds_pcibios_fixup(void)
352	{
353	struct pci_dev *dev = NULL;
354	u_char c;
355
356	if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
357	PCI_DEVICE_ID_VIA_82C586_1, NULL))) {
358	/*
359	* U-Boot does not set the enable bits
360	* for the IDE device. Force them on here.
361	*/
362	pci_read_config_byte(dev, 0x40, &c);
363	c \|= 0x03; /* IDE: Chip Enable Bits */
364	pci_write_config_byte(dev, 0x40, c);
365
366	/*
367	* Since only primary interface works, force the
368	* IDE function to standard primary IDE interrupt
369	* w/ 8259 offset
370	*/
371	dev->irq = 14;
372	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
373	}
374
375	/*
376	* Force legacy USB interrupt routing
377	*/
378	if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
379	PCI_DEVICE_ID_VIA_82C586_2, NULL))) {
380	dev->irq = 10;
381	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10);
382	}
383
384	if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
385	PCI_DEVICE_ID_VIA_82C586_2, dev))) {
386	dev->irq = 11;
387	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
388	}
389	}
1da177e4 LT	390	#endif /* CONFIG_PCI */
	391
	392	TODC_ALLOC();
	393
b37665e0 AF	394	static const char *GFAR_PHY_0 = "phy0:0";
	395	static const char *GFAR_PHY_1 = "phy0:1";
	396
1da177e4 LT	397	/* ************************************************************************
	398	*
	399	* Setup the architecture
	400	*
	401	*/
	402	static void __init
	403	mpc85xx_cds_setup_arch(void)
	404	{
	405	bd_t binfo = (bd_t ) __res;
	406	unsigned int freq;
	407	struct gianfar_platform_data *pdata;
b37665e0	408	struct gianfar_mdio_data *mdata;
1da177e4 LT	409
	410	/* get the core frequency */
	411	freq = binfo->bi_intfreq;
	412
	413	printk("mpc85xx_cds_setup_arch\n");
	414
	415	#ifdef CONFIG_CPM2
	416	cpm2_reset();
	417	#endif
	418
	419	cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
	420	cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
	421	printk("CDS Version = %x in PCI slot %d\n", cadmus[CM_VER], cds_pci_slot);
	422
	423	/* Setup TODC access */
	424	TODC_INIT(TODC_TYPE_DS1743,
	425	0,
	426	0,
	427	ioremap(CDS_RTC_ADDR, CDS_RTC_SIZE),
	428	8);
	429
	430	/* Set loops_per_jiffy to a half-way reasonable value,
	431	for use until calibrate_delay gets called. */
	432	loops_per_jiffy = freq / HZ;
	433
	434	#ifdef CONFIG_PCI
91f9855a KG	435	/* VIA IDE configuration */
	436	ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup;
	437
1da177e4 LT	438	/* setup PCI host bridges */
	439	mpc85xx_setup_hose();
	440	#endif
	441
	442	#ifdef CONFIG_SERIAL_8250
	443	mpc85xx_early_serial_map();
	444	#endif
	445
	446	#ifdef CONFIG_SERIAL_TEXT_DEBUG
	447	/* Invalidate the entry we stole earlier the serial ports
	448	* should be properly mapped */
5be061ee	449	invalidate_tlbcam_entry(num_tlbcam_entries - 1);
1da177e4 LT	450	#endif
1da177e4 LT	451
b37665e0 AF	452	/* setup the board related info for the MDIO bus */
	453	mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
	454
	455	mdata->irq[0] = MPC85xx_IRQ_EXT5;
	456	mdata->irq[1] = MPC85xx_IRQ_EXT5;
	457	mdata->irq[2] = -1;
	458	mdata->irq[3] = -1;
	459	mdata->irq[31] = -1;
	460	mdata->paddr += binfo->bi_immr_base;
	461
1da177e4 LT	462	/* setup the board related information for the enet controllers */
1da177e4 LT	463	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
c91999bb KG	464	if (pdata) {
c91999bb KG	465	pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
b37665e0	466	pdata->bus_id = GFAR_PHY_0;
c91999bb KG	467	memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
c91999bb KG	468	}
1da177e4 LT	469
1da177e4 LT	470	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
c91999bb KG	471	if (pdata) {
c91999bb KG	472	pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
b37665e0	473	pdata->bus_id = GFAR_PHY_1;
c91999bb KG	474	memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
	475	}
	476
	477	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC1);
	478	if (pdata) {
	479	pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
b37665e0	480	pdata->bus_id = GFAR_PHY_0;
c91999bb KG	481	memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
	482	}
	483
	484	pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC2);
	485	if (pdata) {
	486	pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
b37665e0	487	pdata->bus_id = GFAR_PHY_1;
c91999bb KG	488	memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
c91999bb KG	489	}
1da177e4	490
c91999bb KG	491	ppc_sys_device_remove(MPC85xx_eTSEC3);
c91999bb KG	492	ppc_sys_device_remove(MPC85xx_eTSEC4);
1da177e4 LT	493
	494	#ifdef CONFIG_BLK_DEV_INITRD
	495	if (initrd_start)
	496	ROOT_DEV = Root_RAM0;
	497	else
	498	#endif
	499	#ifdef CONFIG_ROOT_NFS
	500	ROOT_DEV = Root_NFS;
	501	#else
	502	ROOT_DEV = Root_HDA1;
	503	#endif
	504	}
	505
	506	/* ************************************************************************ */
	507	void __init
	508	platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
	509	unsigned long r6, unsigned long r7)
	510	{
	511	/* parse_bootinfo must always be called first */
	512	parse_bootinfo(find_bootinfo());
	513
	514	/*
	515	* If we were passed in a board information, copy it into the
	516	* residual data area.
	517	*/
	518	if (r3) {
	519	memcpy((void ) __res, (void ) (r3 + KERNELBASE),
	520	sizeof (bd_t));
	521
	522	}
	523	#ifdef CONFIG_SERIAL_TEXT_DEBUG
	524	{
	525	bd_t binfo = (bd_t ) __res;
	526	struct uart_port p;
	527
	528	/* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
5be061ee	529	settlbcam(num_tlbcam_entries - 1, binfo->bi_immr_base,
1da177e4 LT	530	binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
	531
	532	memset(&p, 0, sizeof (p));
	533	p.iotype = SERIAL_IO_MEM;
	534	p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
	535	p.uartclk = binfo->bi_busfreq;
	536
	537	gen550_init(0, &p);
	538
	539	memset(&p, 0, sizeof (p));
	540	p.iotype = SERIAL_IO_MEM;
	541	p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
	542	p.uartclk = binfo->bi_busfreq;
	543
	544	gen550_init(1, &p);
	545	}
	546	#endif
	547
	548	#if defined(CONFIG_BLK_DEV_INITRD)
	549	/*
	550	* If the init RAM disk has been configured in, and there's a valid
	551	* starting address for it, set it up.
	552	*/
	553	if (r4) {
	554	initrd_start = r4 + KERNELBASE;
	555	initrd_end = r5 + KERNELBASE;
	556	}
	557	#endif /* CONFIG_BLK_DEV_INITRD */
	558
	559	/* Copy the kernel command line arguments to a safe place. */
	560
	561	if (r6) {
	562	(char ) (r7 + KERNELBASE) = 0;
	563	strcpy(cmd_line, (char *) (r6 + KERNELBASE));
	564	}
	565
	566	identify_ppc_sys_by_id(mfspr(SPRN_SVR));
	567
	568	/* setup the PowerPC module struct */
	569	ppc_md.setup_arch = mpc85xx_cds_setup_arch;
	570	ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo;
	571
	572	ppc_md.init_IRQ = mpc85xx_cds_init_IRQ;
	573	ppc_md.get_irq = openpic_get_irq;
	574
	575	ppc_md.restart = mpc85xx_restart;
	576	ppc_md.power_off = mpc85xx_power_off;
	577	ppc_md.halt = mpc85xx_halt;
	578
	579	ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
	580
	581	ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
	582
	583	ppc_md.time_init = todc_time_init;
	584	ppc_md.set_rtc_time = todc_set_rtc_time;
	585	ppc_md.get_rtc_time = todc_get_rtc_time;
	586
	587	ppc_md.nvram_read_val = todc_direct_read_val;
	588	ppc_md.nvram_write_val = todc_direct_write_val;
	589
	590	#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
	591	ppc_md.progress = gen550_progress;
	592	#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
252fcaed KG	593	#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
	594	ppc_md.early_serial_map = mpc85xx_early_serial_map;
	595	#endif /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
1da177e4 LT	596
	597	if (ppc_md.progress)
	598	ppc_md.progress("mpc85xx_cds_init(): exit", 0);
	599
	600	return;
	601	}