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98658538 LY |
1 | /* |
2 | * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved. | |
3 | * | |
4 | * Authors: Shlomi Gridish <gridish@freescale.com> | |
5 | * Li Yang <leoli@freescale.com> | |
6 | * Based on cpm2_common.c from Dan Malek (dmalek@jlc.net) | |
7 | * | |
8 | * Description: | |
9 | * General Purpose functions for the global management of the | |
10 | * QUICC Engine (QE). | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify it | |
13 | * under the terms of the GNU General Public License as published by the | |
14 | * Free Software Foundation; either version 2 of the License, or (at your | |
15 | * option) any later version. | |
16 | */ | |
17 | #include <linux/errno.h> | |
18 | #include <linux/sched.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/param.h> | |
21 | #include <linux/string.h> | |
09a3fba8 | 22 | #include <linux/spinlock.h> |
98658538 LY |
23 | #include <linux/mm.h> |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/bootmem.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/ioport.h> | |
bc556ba9 | 29 | #include <linux/crc32.h> |
98658538 LY |
30 | #include <asm/irq.h> |
31 | #include <asm/page.h> | |
32 | #include <asm/pgtable.h> | |
33 | #include <asm/immap_qe.h> | |
34 | #include <asm/qe.h> | |
35 | #include <asm/prom.h> | |
36 | #include <asm/rheap.h> | |
37 | ||
38 | static void qe_snums_init(void); | |
98658538 LY |
39 | static int qe_sdma_init(void); |
40 | ||
41 | static DEFINE_SPINLOCK(qe_lock); | |
09a3fba8 AV |
42 | DEFINE_SPINLOCK(cmxgcr_lock); |
43 | EXPORT_SYMBOL(cmxgcr_lock); | |
98658538 LY |
44 | |
45 | /* QE snum state */ | |
46 | enum qe_snum_state { | |
47 | QE_SNUM_STATE_USED, | |
48 | QE_SNUM_STATE_FREE | |
49 | }; | |
50 | ||
51 | /* QE snum */ | |
52 | struct qe_snum { | |
53 | u8 num; | |
54 | enum qe_snum_state state; | |
55 | }; | |
56 | ||
57 | /* We allocate this here because it is used almost exclusively for | |
58 | * the communication processor devices. | |
59 | */ | |
0b51b02e | 60 | struct qe_immap __iomem *qe_immr; |
98658538 LY |
61 | EXPORT_SYMBOL(qe_immr); |
62 | ||
63 | static struct qe_snum snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */ | |
98ca77af | 64 | static unsigned int qe_num_of_snum; |
98658538 LY |
65 | |
66 | static phys_addr_t qebase = -1; | |
67 | ||
68 | phys_addr_t get_qe_base(void) | |
69 | { | |
70 | struct device_node *qe; | |
7e1cc9c5 | 71 | int size; |
d8985fd2 | 72 | const u32 *prop; |
98658538 LY |
73 | |
74 | if (qebase != -1) | |
75 | return qebase; | |
76 | ||
a2dd70a1 AV |
77 | qe = of_find_compatible_node(NULL, NULL, "fsl,qe"); |
78 | if (!qe) { | |
79 | qe = of_find_node_by_type(NULL, "qe"); | |
80 | if (!qe) | |
81 | return qebase; | |
82 | } | |
83 | ||
84 | prop = of_get_property(qe, "reg", &size); | |
d8985fd2 AV |
85 | if (prop && size >= sizeof(*prop)) |
86 | qebase = of_translate_address(qe, prop); | |
a2dd70a1 | 87 | of_node_put(qe); |
98658538 LY |
88 | |
89 | return qebase; | |
90 | } | |
91 | ||
92 | EXPORT_SYMBOL(get_qe_base); | |
93 | ||
0c7b87b0 | 94 | void qe_reset(void) |
98658538 LY |
95 | { |
96 | if (qe_immr == NULL) | |
97 | qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE); | |
98 | ||
99 | qe_snums_init(); | |
100 | ||
101 | qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID, | |
102 | QE_CR_PROTOCOL_UNSPECIFIED, 0); | |
103 | ||
104 | /* Reclaim the MURAM memory for our use. */ | |
105 | qe_muram_init(); | |
106 | ||
107 | if (qe_sdma_init()) | |
108 | panic("sdma init failed!"); | |
109 | } | |
110 | ||
111 | int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input) | |
112 | { | |
113 | unsigned long flags; | |
114 | u8 mcn_shift = 0, dev_shift = 0; | |
f49156ea | 115 | u32 ret; |
98658538 LY |
116 | |
117 | spin_lock_irqsave(&qe_lock, flags); | |
118 | if (cmd == QE_RESET) { | |
119 | out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG)); | |
120 | } else { | |
121 | if (cmd == QE_ASSIGN_PAGE) { | |
122 | /* Here device is the SNUM, not sub-block */ | |
123 | dev_shift = QE_CR_SNUM_SHIFT; | |
124 | } else if (cmd == QE_ASSIGN_RISC) { | |
125 | /* Here device is the SNUM, and mcnProtocol is | |
126 | * e_QeCmdRiscAssignment value */ | |
127 | dev_shift = QE_CR_SNUM_SHIFT; | |
128 | mcn_shift = QE_CR_MCN_RISC_ASSIGN_SHIFT; | |
129 | } else { | |
130 | if (device == QE_CR_SUBBLOCK_USB) | |
131 | mcn_shift = QE_CR_MCN_USB_SHIFT; | |
132 | else | |
133 | mcn_shift = QE_CR_MCN_NORMAL_SHIFT; | |
134 | } | |
135 | ||
302439d2 | 136 | out_be32(&qe_immr->cp.cecdr, cmd_input); |
98658538 LY |
137 | out_be32(&qe_immr->cp.cecr, |
138 | (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32) | |
139 | mcn_protocol << mcn_shift)); | |
140 | } | |
141 | ||
142 | /* wait for the QE_CR_FLG to clear */ | |
f49156ea TT |
143 | ret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0, |
144 | 100, 0); | |
145 | /* On timeout (e.g. failure), the expression will be false (ret == 0), | |
146 | otherwise it will be true (ret == 1). */ | |
98658538 LY |
147 | spin_unlock_irqrestore(&qe_lock, flags); |
148 | ||
f49156ea | 149 | return ret == 1; |
98658538 LY |
150 | } |
151 | EXPORT_SYMBOL(qe_issue_cmd); | |
152 | ||
153 | /* Set a baud rate generator. This needs lots of work. There are | |
154 | * 16 BRGs, which can be connected to the QE channels or output | |
155 | * as clocks. The BRGs are in two different block of internal | |
156 | * memory mapped space. | |
6b0b594b | 157 | * The BRG clock is the QE clock divided by 2. |
98658538 LY |
158 | * It was set up long ago during the initial boot phase and is |
159 | * is given to us. | |
160 | * Baud rate clocks are zero-based in the driver code (as that maps | |
161 | * to port numbers). Documentation uses 1-based numbering. | |
162 | */ | |
163 | static unsigned int brg_clk = 0; | |
164 | ||
7f0a6fc8 | 165 | unsigned int qe_get_brg_clk(void) |
98658538 LY |
166 | { |
167 | struct device_node *qe; | |
7e1cc9c5 | 168 | int size; |
a2dd70a1 AV |
169 | const u32 *prop; |
170 | ||
98658538 LY |
171 | if (brg_clk) |
172 | return brg_clk; | |
173 | ||
a2dd70a1 AV |
174 | qe = of_find_compatible_node(NULL, NULL, "fsl,qe"); |
175 | if (!qe) { | |
176 | qe = of_find_node_by_type(NULL, "qe"); | |
177 | if (!qe) | |
178 | return brg_clk; | |
179 | } | |
180 | ||
181 | prop = of_get_property(qe, "brg-frequency", &size); | |
d8985fd2 AV |
182 | if (prop && size == sizeof(*prop)) |
183 | brg_clk = *prop; | |
a2dd70a1 | 184 | |
a2dd70a1 AV |
185 | of_node_put(qe); |
186 | ||
98658538 LY |
187 | return brg_clk; |
188 | } | |
7f0a6fc8 | 189 | EXPORT_SYMBOL(qe_get_brg_clk); |
98658538 | 190 | |
6b0b594b TT |
191 | /* Program the BRG to the given sampling rate and multiplier |
192 | * | |
7264ec44 | 193 | * @brg: the BRG, QE_BRG1 - QE_BRG16 |
6b0b594b TT |
194 | * @rate: the desired sampling rate |
195 | * @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or | |
196 | * GUMR_L[TDCR]. E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01, | |
197 | * then 'multiplier' should be 8. | |
98658538 | 198 | */ |
7264ec44 | 199 | int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier) |
98658538 | 200 | { |
98658538 | 201 | u32 divisor, tempval; |
6b0b594b | 202 | u32 div16 = 0; |
98658538 | 203 | |
7264ec44 TT |
204 | if ((brg < QE_BRG1) || (brg > QE_BRG16)) |
205 | return -EINVAL; | |
206 | ||
7f0a6fc8 | 207 | divisor = qe_get_brg_clk() / (rate * multiplier); |
98658538 | 208 | |
98658538 | 209 | if (divisor > QE_BRGC_DIVISOR_MAX + 1) { |
6b0b594b | 210 | div16 = QE_BRGC_DIV16; |
98658538 LY |
211 | divisor /= 16; |
212 | } | |
213 | ||
6b0b594b TT |
214 | /* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says |
215 | that the BRG divisor must be even if you're not using divide-by-16 | |
216 | mode. */ | |
217 | if (!div16 && (divisor & 1)) | |
218 | divisor++; | |
219 | ||
220 | tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | | |
221 | QE_BRGC_ENABLE | div16; | |
98658538 | 222 | |
7264ec44 TT |
223 | out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval); |
224 | ||
225 | return 0; | |
98658538 | 226 | } |
7264ec44 | 227 | EXPORT_SYMBOL(qe_setbrg); |
98658538 | 228 | |
174b0da2 TT |
229 | /* Convert a string to a QE clock source enum |
230 | * | |
231 | * This function takes a string, typically from a property in the device | |
232 | * tree, and returns the corresponding "enum qe_clock" value. | |
233 | */ | |
234 | enum qe_clock qe_clock_source(const char *source) | |
235 | { | |
236 | unsigned int i; | |
237 | ||
238 | if (strcasecmp(source, "none") == 0) | |
239 | return QE_CLK_NONE; | |
240 | ||
241 | if (strncasecmp(source, "brg", 3) == 0) { | |
242 | i = simple_strtoul(source + 3, NULL, 10); | |
243 | if ((i >= 1) && (i <= 16)) | |
244 | return (QE_BRG1 - 1) + i; | |
245 | else | |
246 | return QE_CLK_DUMMY; | |
247 | } | |
248 | ||
249 | if (strncasecmp(source, "clk", 3) == 0) { | |
250 | i = simple_strtoul(source + 3, NULL, 10); | |
251 | if ((i >= 1) && (i <= 24)) | |
252 | return (QE_CLK1 - 1) + i; | |
253 | else | |
254 | return QE_CLK_DUMMY; | |
255 | } | |
256 | ||
257 | return QE_CLK_DUMMY; | |
258 | } | |
259 | EXPORT_SYMBOL(qe_clock_source); | |
260 | ||
98658538 LY |
261 | /* Initialize SNUMs (thread serial numbers) according to |
262 | * QE Module Control chapter, SNUM table | |
263 | */ | |
264 | static void qe_snums_init(void) | |
265 | { | |
266 | int i; | |
267 | static const u8 snum_init[] = { | |
268 | 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D, | |
269 | 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89, | |
270 | 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9, | |
98ca77af HW |
271 | 0xD8, 0xD9, 0xE8, 0xE9, 0x08, 0x09, 0x18, 0x19, |
272 | 0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59, | |
273 | 0x68, 0x69, 0x78, 0x79, 0x80, 0x81, | |
98658538 LY |
274 | }; |
275 | ||
98ca77af HW |
276 | qe_num_of_snum = qe_get_num_of_snums(); |
277 | ||
278 | for (i = 0; i < qe_num_of_snum; i++) { | |
98658538 LY |
279 | snums[i].num = snum_init[i]; |
280 | snums[i].state = QE_SNUM_STATE_FREE; | |
281 | } | |
282 | } | |
283 | ||
284 | int qe_get_snum(void) | |
285 | { | |
286 | unsigned long flags; | |
287 | int snum = -EBUSY; | |
288 | int i; | |
289 | ||
290 | spin_lock_irqsave(&qe_lock, flags); | |
98ca77af | 291 | for (i = 0; i < qe_num_of_snum; i++) { |
98658538 LY |
292 | if (snums[i].state == QE_SNUM_STATE_FREE) { |
293 | snums[i].state = QE_SNUM_STATE_USED; | |
294 | snum = snums[i].num; | |
295 | break; | |
296 | } | |
297 | } | |
298 | spin_unlock_irqrestore(&qe_lock, flags); | |
299 | ||
300 | return snum; | |
301 | } | |
302 | EXPORT_SYMBOL(qe_get_snum); | |
303 | ||
304 | void qe_put_snum(u8 snum) | |
305 | { | |
306 | int i; | |
307 | ||
98ca77af | 308 | for (i = 0; i < qe_num_of_snum; i++) { |
98658538 LY |
309 | if (snums[i].num == snum) { |
310 | snums[i].state = QE_SNUM_STATE_FREE; | |
311 | break; | |
312 | } | |
313 | } | |
314 | } | |
315 | EXPORT_SYMBOL(qe_put_snum); | |
316 | ||
317 | static int qe_sdma_init(void) | |
318 | { | |
7e1cc9c5 | 319 | struct sdma __iomem *sdma = &qe_immr->sdma; |
0c7b87b0 | 320 | static unsigned long sdma_buf_offset = (unsigned long)-ENOMEM; |
98658538 LY |
321 | |
322 | if (!sdma) | |
323 | return -ENODEV; | |
324 | ||
325 | /* allocate 2 internal temporary buffers (512 bytes size each) for | |
326 | * the SDMA */ | |
0c7b87b0 AV |
327 | if (IS_ERR_VALUE(sdma_buf_offset)) { |
328 | sdma_buf_offset = qe_muram_alloc(512 * 2, 4096); | |
329 | if (IS_ERR_VALUE(sdma_buf_offset)) | |
330 | return -ENOMEM; | |
331 | } | |
98658538 | 332 | |
4c35630c | 333 | out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK); |
7f013bc9 CM |
334 | out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK | |
335 | (0x1 << QE_SDMR_CEN_SHIFT))); | |
98658538 LY |
336 | |
337 | return 0; | |
338 | } | |
339 | ||
bc556ba9 | 340 | /* The maximum number of RISCs we support */ |
98eaa098 | 341 | #define MAX_QE_RISC 4 |
bc556ba9 TT |
342 | |
343 | /* Firmware information stored here for qe_get_firmware_info() */ | |
344 | static struct qe_firmware_info qe_firmware_info; | |
345 | ||
346 | /* | |
347 | * Set to 1 if QE firmware has been uploaded, and therefore | |
348 | * qe_firmware_info contains valid data. | |
349 | */ | |
350 | static int qe_firmware_uploaded; | |
351 | ||
352 | /* | |
353 | * Upload a QE microcode | |
354 | * | |
355 | * This function is a worker function for qe_upload_firmware(). It does | |
356 | * the actual uploading of the microcode. | |
357 | */ | |
358 | static void qe_upload_microcode(const void *base, | |
359 | const struct qe_microcode *ucode) | |
360 | { | |
361 | const __be32 *code = base + be32_to_cpu(ucode->code_offset); | |
362 | unsigned int i; | |
363 | ||
364 | if (ucode->major || ucode->minor || ucode->revision) | |
365 | printk(KERN_INFO "qe-firmware: " | |
366 | "uploading microcode '%s' version %u.%u.%u\n", | |
367 | ucode->id, ucode->major, ucode->minor, ucode->revision); | |
368 | else | |
369 | printk(KERN_INFO "qe-firmware: " | |
370 | "uploading microcode '%s'\n", ucode->id); | |
371 | ||
372 | /* Use auto-increment */ | |
373 | out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) | | |
374 | QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR); | |
375 | ||
376 | for (i = 0; i < be32_to_cpu(ucode->count); i++) | |
377 | out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i])); | |
378 | } | |
379 | ||
380 | /* | |
381 | * Upload a microcode to the I-RAM at a specific address. | |
382 | * | |
383 | * See Documentation/powerpc/qe-firmware.txt for information on QE microcode | |
384 | * uploading. | |
385 | * | |
386 | * Currently, only version 1 is supported, so the 'version' field must be | |
387 | * set to 1. | |
388 | * | |
389 | * The SOC model and revision are not validated, they are only displayed for | |
390 | * informational purposes. | |
391 | * | |
392 | * 'calc_size' is the calculated size, in bytes, of the firmware structure and | |
393 | * all of the microcode structures, minus the CRC. | |
394 | * | |
395 | * 'length' is the size that the structure says it is, including the CRC. | |
396 | */ | |
397 | int qe_upload_firmware(const struct qe_firmware *firmware) | |
398 | { | |
399 | unsigned int i; | |
400 | unsigned int j; | |
401 | u32 crc; | |
402 | size_t calc_size = sizeof(struct qe_firmware); | |
403 | size_t length; | |
404 | const struct qe_header *hdr; | |
405 | ||
406 | if (!firmware) { | |
407 | printk(KERN_ERR "qe-firmware: invalid pointer\n"); | |
408 | return -EINVAL; | |
409 | } | |
410 | ||
411 | hdr = &firmware->header; | |
412 | length = be32_to_cpu(hdr->length); | |
413 | ||
414 | /* Check the magic */ | |
415 | if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || | |
416 | (hdr->magic[2] != 'F')) { | |
417 | printk(KERN_ERR "qe-firmware: not a microcode\n"); | |
418 | return -EPERM; | |
419 | } | |
420 | ||
421 | /* Check the version */ | |
422 | if (hdr->version != 1) { | |
423 | printk(KERN_ERR "qe-firmware: unsupported version\n"); | |
424 | return -EPERM; | |
425 | } | |
426 | ||
427 | /* Validate some of the fields */ | |
6f913160 | 428 | if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) { |
bc556ba9 TT |
429 | printk(KERN_ERR "qe-firmware: invalid data\n"); |
430 | return -EINVAL; | |
431 | } | |
432 | ||
433 | /* Validate the length and check if there's a CRC */ | |
434 | calc_size += (firmware->count - 1) * sizeof(struct qe_microcode); | |
435 | ||
436 | for (i = 0; i < firmware->count; i++) | |
437 | /* | |
438 | * For situations where the second RISC uses the same microcode | |
439 | * as the first, the 'code_offset' and 'count' fields will be | |
440 | * zero, so it's okay to add those. | |
441 | */ | |
442 | calc_size += sizeof(__be32) * | |
443 | be32_to_cpu(firmware->microcode[i].count); | |
444 | ||
445 | /* Validate the length */ | |
446 | if (length != calc_size + sizeof(__be32)) { | |
447 | printk(KERN_ERR "qe-firmware: invalid length\n"); | |
448 | return -EPERM; | |
449 | } | |
450 | ||
451 | /* Validate the CRC */ | |
452 | crc = be32_to_cpu(*(__be32 *)((void *)firmware + calc_size)); | |
453 | if (crc != crc32(0, firmware, calc_size)) { | |
454 | printk(KERN_ERR "qe-firmware: firmware CRC is invalid\n"); | |
455 | return -EIO; | |
456 | } | |
457 | ||
458 | /* | |
459 | * If the microcode calls for it, split the I-RAM. | |
460 | */ | |
461 | if (!firmware->split) | |
462 | setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR); | |
463 | ||
464 | if (firmware->soc.model) | |
465 | printk(KERN_INFO | |
466 | "qe-firmware: firmware '%s' for %u V%u.%u\n", | |
467 | firmware->id, be16_to_cpu(firmware->soc.model), | |
468 | firmware->soc.major, firmware->soc.minor); | |
469 | else | |
470 | printk(KERN_INFO "qe-firmware: firmware '%s'\n", | |
471 | firmware->id); | |
472 | ||
473 | /* | |
474 | * The QE only supports one microcode per RISC, so clear out all the | |
475 | * saved microcode information and put in the new. | |
476 | */ | |
477 | memset(&qe_firmware_info, 0, sizeof(qe_firmware_info)); | |
478 | strcpy(qe_firmware_info.id, firmware->id); | |
479 | qe_firmware_info.extended_modes = firmware->extended_modes; | |
480 | memcpy(qe_firmware_info.vtraps, firmware->vtraps, | |
481 | sizeof(firmware->vtraps)); | |
482 | ||
483 | /* Loop through each microcode. */ | |
484 | for (i = 0; i < firmware->count; i++) { | |
485 | const struct qe_microcode *ucode = &firmware->microcode[i]; | |
486 | ||
487 | /* Upload a microcode if it's present */ | |
488 | if (ucode->code_offset) | |
489 | qe_upload_microcode(firmware, ucode); | |
490 | ||
491 | /* Program the traps for this processor */ | |
492 | for (j = 0; j < 16; j++) { | |
493 | u32 trap = be32_to_cpu(ucode->traps[j]); | |
494 | ||
495 | if (trap) | |
496 | out_be32(&qe_immr->rsp[i].tibcr[j], trap); | |
497 | } | |
498 | ||
499 | /* Enable traps */ | |
500 | out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr)); | |
501 | } | |
502 | ||
503 | qe_firmware_uploaded = 1; | |
504 | ||
505 | return 0; | |
506 | } | |
507 | EXPORT_SYMBOL(qe_upload_firmware); | |
508 | ||
509 | /* | |
510 | * Get info on the currently-loaded firmware | |
511 | * | |
512 | * This function also checks the device tree to see if the boot loader has | |
513 | * uploaded a firmware already. | |
514 | */ | |
515 | struct qe_firmware_info *qe_get_firmware_info(void) | |
516 | { | |
517 | static int initialized; | |
518 | struct property *prop; | |
519 | struct device_node *qe; | |
520 | struct device_node *fw = NULL; | |
521 | const char *sprop; | |
522 | unsigned int i; | |
523 | ||
524 | /* | |
525 | * If we haven't checked yet, and a driver hasn't uploaded a firmware | |
526 | * yet, then check the device tree for information. | |
527 | */ | |
86f4e5d4 IN |
528 | if (qe_firmware_uploaded) |
529 | return &qe_firmware_info; | |
530 | ||
531 | if (initialized) | |
bc556ba9 TT |
532 | return NULL; |
533 | ||
534 | initialized = 1; | |
535 | ||
536 | /* | |
537 | * Newer device trees have an "fsl,qe" compatible property for the QE | |
538 | * node, but we still need to support older device trees. | |
539 | */ | |
540 | qe = of_find_compatible_node(NULL, NULL, "fsl,qe"); | |
541 | if (!qe) { | |
542 | qe = of_find_node_by_type(NULL, "qe"); | |
543 | if (!qe) | |
544 | return NULL; | |
545 | } | |
546 | ||
547 | /* Find the 'firmware' child node */ | |
548 | for_each_child_of_node(qe, fw) { | |
549 | if (strcmp(fw->name, "firmware") == 0) | |
550 | break; | |
551 | } | |
552 | ||
553 | of_node_put(qe); | |
554 | ||
555 | /* Did we find the 'firmware' node? */ | |
556 | if (!fw) | |
557 | return NULL; | |
558 | ||
559 | qe_firmware_uploaded = 1; | |
560 | ||
561 | /* Copy the data into qe_firmware_info*/ | |
562 | sprop = of_get_property(fw, "id", NULL); | |
563 | if (sprop) | |
564 | strncpy(qe_firmware_info.id, sprop, | |
565 | sizeof(qe_firmware_info.id) - 1); | |
566 | ||
567 | prop = of_find_property(fw, "extended-modes", NULL); | |
568 | if (prop && (prop->length == sizeof(u64))) { | |
569 | const u64 *iprop = prop->value; | |
570 | ||
571 | qe_firmware_info.extended_modes = *iprop; | |
572 | } | |
573 | ||
574 | prop = of_find_property(fw, "virtual-traps", NULL); | |
575 | if (prop && (prop->length == 32)) { | |
576 | const u32 *iprop = prop->value; | |
577 | ||
578 | for (i = 0; i < ARRAY_SIZE(qe_firmware_info.vtraps); i++) | |
579 | qe_firmware_info.vtraps[i] = iprop[i]; | |
580 | } | |
581 | ||
582 | of_node_put(fw); | |
583 | ||
584 | return &qe_firmware_info; | |
585 | } | |
586 | EXPORT_SYMBOL(qe_get_firmware_info); | |
587 | ||
06c44350 HW |
588 | unsigned int qe_get_num_of_risc(void) |
589 | { | |
590 | struct device_node *qe; | |
591 | int size; | |
592 | unsigned int num_of_risc = 0; | |
593 | const u32 *prop; | |
594 | ||
595 | qe = of_find_compatible_node(NULL, NULL, "fsl,qe"); | |
596 | if (!qe) { | |
597 | /* Older devices trees did not have an "fsl,qe" | |
598 | * compatible property, so we need to look for | |
599 | * the QE node by name. | |
600 | */ | |
601 | qe = of_find_node_by_type(NULL, "qe"); | |
602 | if (!qe) | |
603 | return num_of_risc; | |
604 | } | |
605 | ||
606 | prop = of_get_property(qe, "fsl,qe-num-riscs", &size); | |
607 | if (prop && size == sizeof(*prop)) | |
608 | num_of_risc = *prop; | |
609 | ||
610 | of_node_put(qe); | |
611 | ||
612 | return num_of_risc; | |
613 | } | |
614 | EXPORT_SYMBOL(qe_get_num_of_risc); | |
615 | ||
98ca77af HW |
616 | unsigned int qe_get_num_of_snums(void) |
617 | { | |
618 | struct device_node *qe; | |
619 | int size; | |
620 | unsigned int num_of_snums; | |
621 | const u32 *prop; | |
622 | ||
623 | num_of_snums = 28; /* The default number of snum for threads is 28 */ | |
624 | qe = of_find_compatible_node(NULL, NULL, "fsl,qe"); | |
625 | if (!qe) { | |
626 | /* Older devices trees did not have an "fsl,qe" | |
627 | * compatible property, so we need to look for | |
628 | * the QE node by name. | |
629 | */ | |
630 | qe = of_find_node_by_type(NULL, "qe"); | |
631 | if (!qe) | |
632 | return num_of_snums; | |
633 | } | |
634 | ||
635 | prop = of_get_property(qe, "fsl,qe-num-snums", &size); | |
636 | if (prop && size == sizeof(*prop)) { | |
637 | num_of_snums = *prop; | |
638 | if ((num_of_snums < 28) || (num_of_snums > QE_NUM_OF_SNUM)) { | |
639 | /* No QE ever has fewer than 28 SNUMs */ | |
640 | pr_err("QE: number of snum is invalid\n"); | |
641 | return -EINVAL; | |
642 | } | |
643 | } | |
644 | ||
645 | of_node_put(qe); | |
646 | ||
647 | return num_of_snums; | |
648 | } | |
649 | EXPORT_SYMBOL(qe_get_num_of_snums); |