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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[net-next-2.6.git] / arch / powerpc / sysdev / ppc4xx_pci.c
CommitLineData
5738ec6d
BH		 1/*
2 * PCI / PCI-X / PCI-Express support for 4xx parts
3 *
4 * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
5 *
a2d2e1ec
BH		 6 * Most PCI Express code is coming from Stefan Roese implementation for
7 * arch/ppc in the Denx tree, slightly reworked by me.
8 *
9 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
10 *
11 * Some of that comes itself from a previous implementation for 440SPE only
12 * by Roland Dreier:
13 *
14 * Copyright (c) 2005 Cisco Systems. All rights reserved.
15 * Roland Dreier <rolandd@cisco.com>
16 *
5738ec6d
BH		 17 */
18
035ee428
BH		 19#undef DEBUG
20
5738ec6d
BH		 21#include <linux/kernel.h>
22#include <linux/pci.h>
23#include <linux/init.h>
24#include <linux/of.h>
a2d2e1ec
BH		 25#include <linux/bootmem.h>
26#include <linux/delay.h>
5a0e3ad6 27#include <linux/slab.h>
5738ec6d
BH		 28
29#include <asm/io.h>
30#include <asm/pci-bridge.h>
31#include <asm/machdep.h>
a2d2e1ec
BH		 32#include <asm/dcr.h>
33#include <asm/dcr-regs.h>
cc2e113b 34#include <mm/mmu_decl.h>
5738ec6d
BH		 35
36#include "ppc4xx_pci.h"
37
38static int dma_offset_set;
39
a2d2e1ec
BH		 40#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
41#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
42
8308c54d
JF		 43#define RES_TO_U32_LOW(val) \
44 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val))
45#define RES_TO_U32_HIGH(val) \
46 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0))
a2d2e1ec 47
accf5ef2
SR		 48static inline int ppc440spe_revA(void)
49{
50 /* Catch both 440SPe variants, with and without RAID6 support */
51 if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890)
52 return 1;
53 else
54 return 0;
55}
56
c839e0ef
BH		 57static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev)
58{
59 struct pci_controller *hose;
60 int i;
61
62 if (dev->devfn != 0 || dev->bus->self != NULL)
63 return;
64
65 hose = pci_bus_to_host(dev->bus);
66 if (hose == NULL)
67 return;
68
69 if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") &&
70 !of_device_is_compatible(hose->dn, "ibm,plb-pcix") &&
71 !of_device_is_compatible(hose->dn, "ibm,plb-pci"))
72 return;
73
5ce4b596
JB		 74 if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") ||
75 of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) {
76 hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM;
77 }
78
c839e0ef
BH		 79 /* Hide the PCI host BARs from the kernel as their content doesn't
80 * fit well in the resource management
81 */
82 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
83 dev->resource[i].start = dev->resource[i].end = 0;
84 dev->resource[i].flags = 0;
85 }
86
87 printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n",
88 pci_name(dev));
89}
90DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge);
91
5738ec6d
BH		 92static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
93 void __iomem *reg,
94 struct resource *res)
95{
96 u64 size;
97 const u32 *ranges;
98 int rlen;
99 int pna = of_n_addr_cells(hose->dn);
100 int np = pna + 5;
101
102 /* Default */
103 res->start = 0;
cc2e113b
IY		 104 size = 0x80000000;
105 res->end = size - 1;
5738ec6d
BH		 106 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
107
108 /* Get dma-ranges property */
109 ranges = of_get_property(hose->dn, "dma-ranges", &rlen);
110 if (ranges == NULL)
111 goto out;
112
113 /* Walk it */
114 while ((rlen -= np * 4) >= 0) {
115 u32 pci_space = ranges[0];
116 u64 pci_addr = of_read_number(ranges + 1, 2);
117 u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3);
118 size = of_read_number(ranges + pna + 3, 2);
119 ranges += np;
120 if (cpu_addr == OF_BAD_ADDR || size == 0)
121 continue;
122
123 /* We only care about memory */
124 if ((pci_space & 0x03000000) != 0x02000000)
125 continue;
126
127 /* We currently only support memory at 0, and pci_addr
128 * within 32 bits space
129 */
130 if (cpu_addr != 0 || pci_addr > 0xffffffff) {
131 printk(KERN_WARNING "%s: Ignored unsupported dma range"
132 " 0x%016llx...0x%016llx -> 0x%016llx\n",
133 hose->dn->full_name,
134 pci_addr, pci_addr + size - 1, cpu_addr);
135 continue;
136 }
137
138 /* Check if not prefetchable */
139 if (!(pci_space & 0x40000000))
140 res->flags &= ~IORESOURCE_PREFETCH;
141
142
143 /* Use that */
144 res->start = pci_addr;
5738ec6d 145 /* Beware of 32 bits resources */
8308c54d
JF		 146 if (sizeof(resource_size_t) == sizeof(u32) &&
147 (pci_addr + size) > 0x100000000ull)
5738ec6d
BH		 148 res->end = 0xffffffff;
149 else
5738ec6d
BH		 150 res->end = res->start + size - 1;
151 break;
152 }
153
154 /* We only support one global DMA offset */
155 if (dma_offset_set && pci_dram_offset != res->start) {
156 printk(KERN_ERR "%s: dma-ranges(s) mismatch\n",
157 hose->dn->full_name);
158 return -ENXIO;
159 }
160
161 /* Check that we can fit all of memory as we don't support
162 * DMA bounce buffers
163 */
164 if (size < total_memory) {
165 printk(KERN_ERR "%s: dma-ranges too small "
cc2e113b
IY		 166 "(size=%llx total_memory=%llx)\n",
167 hose->dn->full_name, size, (u64)total_memory);
5738ec6d
BH		 168 return -ENXIO;
169 }
170
171 /* Check we are a power of 2 size and that base is a multiple of size*/
cc2e113b 172 if ((size & (size - 1)) != 0 ||
5738ec6d
BH		 173 (res->start & (size - 1)) != 0) {
174 printk(KERN_ERR "%s: dma-ranges unaligned\n",
175 hose->dn->full_name);
176 return -ENXIO;
177 }
178
179 /* Check that we are fully contained within 32 bits space */
180 if (res->end > 0xffffffff) {
181 printk(KERN_ERR "%s: dma-ranges outside of 32 bits space\n",
182 hose->dn->full_name);
183 return -ENXIO;
184 }
185 out:
186 dma_offset_set = 1;
187 pci_dram_offset = res->start;
188
189 printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n",
190 pci_dram_offset);
191 return 0;
192}
193
194/*
195 * 4xx PCI 2.x part
196 */
c839e0ef 197
84d727a1
BH		 198static int __init ppc4xx_setup_one_pci_PMM(struct pci_controller *hose,
199 void __iomem *reg,
200 u64 plb_addr,
201 u64 pci_addr,
202 u64 size,
203 unsigned int flags,
204 int index)
205{
206 u32 ma, pcila, pciha;
207
1ac00cc2
BH		 208 /* Hack warning ! The "old" PCI 2.x cell only let us configure the low
209 * 32-bit of incoming PLB addresses. The top 4 bits of the 36-bit
210 * address are actually hard wired to a value that appears to depend
211 * on the specific SoC. For example, it's 0 on 440EP and 1 on 440EPx.
212 *
213 * The trick here is we just crop those top bits and ignore them when
214 * programming the chip. That means the device-tree has to be right
215 * for the specific part used (we don't print a warning if it's wrong
216 * but on the other hand, you'll crash quickly enough), but at least
217 * this code should work whatever the hard coded value is
218 */
219 plb_addr &= 0xffffffffull;
220
221 /* Note: Due to the above hack, the test below doesn't actually test
222 * if you address is above 4G, but it tests that address and
223 * (address + size) are both contained in the same 4G
224 */
84d727a1
BH		 225 if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) ||
226 size < 0x1000 || (plb_addr & (size - 1)) != 0) {
227 printk(KERN_WARNING "%s: Resource out of range\n",
228 hose->dn->full_name);
229 return -1;
230 }
231 ma = (0xffffffffu << ilog2(size)) | 1;
232 if (flags & IORESOURCE_PREFETCH)
233 ma |= 2;
234
235 pciha = RES_TO_U32_HIGH(pci_addr);
236 pcila = RES_TO_U32_LOW(pci_addr);
237
238 writel(plb_addr, reg + PCIL0_PMM0LA + (0x10 * index));
239 writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * index));
240 writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * index));
241 writel(ma, reg + PCIL0_PMM0MA + (0x10 * index));
242
243 return 0;
244}
245
c839e0ef
BH		 246static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
247 void __iomem *reg)
248{
84d727a1 249 int i, j, found_isa_hole = 0;
c839e0ef
BH		 250
251 /* Setup outbound memory windows */
252 for (i = j = 0; i < 3; i++) {
253 struct resource *res = &hose->mem_resources[i];
254
255 /* we only care about memory windows */
256 if (!(res->flags & IORESOURCE_MEM))
257 continue;
258 if (j > 2) {
259 printk(KERN_WARNING "%s: Too many ranges\n",
260 hose->dn->full_name);
261 break;
262 }
263
84d727a1
BH		 264 /* Configure the resource */
265 if (ppc4xx_setup_one_pci_PMM(hose, reg,
266 res->start,
267 res->start - hose->pci_mem_offset,
268 res->end + 1 - res->start,
269 res->flags,
270 j) == 0) {
271 j++;
272
273 /* If the resource PCI address is 0 then we have our
274 * ISA memory hole
275 */
276 if (res->start == hose->pci_mem_offset)
277 found_isa_hole = 1;
c839e0ef 278 }
c839e0ef 279 }
84d727a1
BH		 280
281 /* Handle ISA memory hole if not already covered */
282 if (j <= 2 && !found_isa_hole && hose->isa_mem_size)
283 if (ppc4xx_setup_one_pci_PMM(hose, reg, hose->isa_mem_phys, 0,
284 hose->isa_mem_size, 0, j) == 0)
285 printk(KERN_INFO "%s: Legacy ISA memory support enabled\n",
286 hose->dn->full_name);
c839e0ef
BH		 287}
288
289static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose,
290 void __iomem *reg,
291 const struct resource *res)
292{
293 resource_size_t size = res->end - res->start + 1;
294 u32 sa;
295
296 /* Calculate window size */
297 sa = (0xffffffffu << ilog2(size)) | 1;
298 sa |= 0x1;
299
300 /* RAM is always at 0 local for now */
301 writel(0, reg + PCIL0_PTM1LA);
302 writel(sa, reg + PCIL0_PTM1MS);
303
304 /* Map on PCI side */
305 early_write_config_dword(hose, hose->first_busno, 0,
306 PCI_BASE_ADDRESS_1, res->start);
307 early_write_config_dword(hose, hose->first_busno, 0,
308 PCI_BASE_ADDRESS_2, 0x00000000);
309 early_write_config_word(hose, hose->first_busno, 0,
310 PCI_COMMAND, 0x0006);
311}
312
5738ec6d
BH		 313static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
314{
315 /* NYI */
c839e0ef
BH		 316 struct resource rsrc_cfg;
317 struct resource rsrc_reg;
318 struct resource dma_window;
319 struct pci_controller *hose = NULL;
320 void __iomem *reg = NULL;
321 const int *bus_range;
322 int primary = 0;
323
5a013fc7
MF		 324 /* Check if device is enabled */
325 if (!of_device_is_available(np)) {
326 printk(KERN_INFO "%s: Port disabled via device-tree\n",
327 np->full_name);
328 return;
329 }
330
c839e0ef
BH		 331 /* Fetch config space registers address */
332 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
5a013fc7 333 printk(KERN_ERR "%s: Can't get PCI config register base !",
c839e0ef
BH		 334 np->full_name);
335 return;
336 }
337 /* Fetch host bridge internal registers address */
338 if (of_address_to_resource(np, 3, &rsrc_reg)) {
339 printk(KERN_ERR "%s: Can't get PCI internal register base !",
340 np->full_name);
341 return;
342 }
343
344 /* Check if primary bridge */
345 if (of_get_property(np, "primary", NULL))
346 primary = 1;
347
348 /* Get bus range if any */
349 bus_range = of_get_property(np, "bus-range", NULL);
350
351 /* Map registers */
352 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
353 if (reg == NULL) {
354 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
355 goto fail;
356 }
357
358 /* Allocate the host controller data structure */
359 hose = pcibios_alloc_controller(np);
360 if (!hose)
361 goto fail;
362
363 hose->first_busno = bus_range ? bus_range[0] : 0x0;
364 hose->last_busno = bus_range ? bus_range[1] : 0xff;
365
366 /* Setup config space */
367 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
368
369 /* Disable all windows */
370 writel(0, reg + PCIL0_PMM0MA);
371 writel(0, reg + PCIL0_PMM1MA);
372 writel(0, reg + PCIL0_PMM2MA);
373 writel(0, reg + PCIL0_PTM1MS);
374 writel(0, reg + PCIL0_PTM2MS);
375
376 /* Parse outbound mapping resources */
377 pci_process_bridge_OF_ranges(hose, np, primary);
378
379 /* Parse inbound mapping resources */
380 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
381 goto fail;
382
383 /* Configure outbound ranges POMs */
384 ppc4xx_configure_pci_PMMs(hose, reg);
385
386 /* Configure inbound ranges PIMs */
387 ppc4xx_configure_pci_PTMs(hose, reg, &dma_window);
388
389 /* We don't need the registers anymore */
390 iounmap(reg);
391 return;
392
393 fail:
394 if (hose)
395 pcibios_free_controller(hose);
396 if (reg)
397 iounmap(reg);
5738ec6d
BH		 398}
399
400/*
401 * 4xx PCI-X part
402 */
403
84d727a1
BH		 404static int __init ppc4xx_setup_one_pcix_POM(struct pci_controller *hose,
405 void __iomem *reg,
406 u64 plb_addr,
407 u64 pci_addr,
408 u64 size,
409 unsigned int flags,
410 int index)
411{
412 u32 lah, lal, pciah, pcial, sa;
413
414 if (!is_power_of_2(size) || size < 0x1000 ||
415 (plb_addr & (size - 1)) != 0) {
416 printk(KERN_WARNING "%s: Resource out of range\n",
417 hose->dn->full_name);
418 return -1;
419 }
420
421 /* Calculate register values */
422 lah = RES_TO_U32_HIGH(plb_addr);
423 lal = RES_TO_U32_LOW(plb_addr);
424 pciah = RES_TO_U32_HIGH(pci_addr);
425 pcial = RES_TO_U32_LOW(pci_addr);
426 sa = (0xffffffffu << ilog2(size)) | 0x1;
427
428 /* Program register values */
429 if (index == 0) {
430 writel(lah, reg + PCIX0_POM0LAH);
431 writel(lal, reg + PCIX0_POM0LAL);
432 writel(pciah, reg + PCIX0_POM0PCIAH);
433 writel(pcial, reg + PCIX0_POM0PCIAL);
434 writel(sa, reg + PCIX0_POM0SA);
435 } else {
436 writel(lah, reg + PCIX0_POM1LAH);
437 writel(lal, reg + PCIX0_POM1LAL);
438 writel(pciah, reg + PCIX0_POM1PCIAH);
439 writel(pcial, reg + PCIX0_POM1PCIAL);
440 writel(sa, reg + PCIX0_POM1SA);
441 }
442
443 return 0;
444}
445
5738ec6d
BH		 446static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
447 void __iomem *reg)
448{
84d727a1 449 int i, j, found_isa_hole = 0;
5738ec6d
BH		 450
451 /* Setup outbound memory windows */
452 for (i = j = 0; i < 3; i++) {
453 struct resource *res = &hose->mem_resources[i];
454
455 /* we only care about memory windows */
456 if (!(res->flags & IORESOURCE_MEM))
457 continue;
458 if (j > 1) {
459 printk(KERN_WARNING "%s: Too many ranges\n",
460 hose->dn->full_name);
461 break;
462 }
463
84d727a1
BH		 464 /* Configure the resource */
465 if (ppc4xx_setup_one_pcix_POM(hose, reg,
466 res->start,
467 res->start - hose->pci_mem_offset,
468 res->end + 1 - res->start,
469 res->flags,
470 j) == 0) {
471 j++;
472
473 /* If the resource PCI address is 0 then we have our
474 * ISA memory hole
475 */
476 if (res->start == hose->pci_mem_offset)
477 found_isa_hole = 1;
5738ec6d 478 }
5738ec6d 479 }
84d727a1
BH		 480
481 /* Handle ISA memory hole if not already covered */
482 if (j <= 1 && !found_isa_hole && hose->isa_mem_size)
483 if (ppc4xx_setup_one_pcix_POM(hose, reg, hose->isa_mem_phys, 0,
484 hose->isa_mem_size, 0, j) == 0)
485 printk(KERN_INFO "%s: Legacy ISA memory support enabled\n",
486 hose->dn->full_name);
5738ec6d
BH		 487}
488
489static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose,
490 void __iomem *reg,
491 const struct resource *res,
492 int big_pim,
493 int enable_msi_hole)
494{
495 resource_size_t size = res->end - res->start + 1;
496 u32 sa;
497
498 /* RAM is always at 0 */
499 writel(0x00000000, reg + PCIX0_PIM0LAH);
500 writel(0x00000000, reg + PCIX0_PIM0LAL);
501
502 /* Calculate window size */
503 sa = (0xffffffffu << ilog2(size)) | 1;
504 sa |= 0x1;
505 if (res->flags & IORESOURCE_PREFETCH)
506 sa |= 0x2;
507 if (enable_msi_hole)
508 sa |= 0x4;
509 writel(sa, reg + PCIX0_PIM0SA);
510 if (big_pim)
511 writel(0xffffffff, reg + PCIX0_PIM0SAH);
512
513 /* Map on PCI side */
514 writel(0x00000000, reg + PCIX0_BAR0H);
515 writel(res->start, reg + PCIX0_BAR0L);
516 writew(0x0006, reg + PCIX0_COMMAND);
517}
518
519static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
520{
521 struct resource rsrc_cfg;
522 struct resource rsrc_reg;
523 struct resource dma_window;
524 struct pci_controller *hose = NULL;
525 void __iomem *reg = NULL;
526 const int *bus_range;
527 int big_pim = 0, msi = 0, primary = 0;
528
529 /* Fetch config space registers address */
530 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
531 printk(KERN_ERR "%s:Can't get PCI-X config register base !",
532 np->full_name);
533 return;
534 }
535 /* Fetch host bridge internal registers address */
536 if (of_address_to_resource(np, 3, &rsrc_reg)) {
537 printk(KERN_ERR "%s: Can't get PCI-X internal register base !",
538 np->full_name);
539 return;
540 }
541
542 /* Check if it supports large PIMs (440GX) */
543 if (of_get_property(np, "large-inbound-windows", NULL))
544 big_pim = 1;
545
546 /* Check if we should enable MSIs inbound hole */
547 if (of_get_property(np, "enable-msi-hole", NULL))
548 msi = 1;
549
550 /* Check if primary bridge */
551 if (of_get_property(np, "primary", NULL))
552 primary = 1;
553
554 /* Get bus range if any */
555 bus_range = of_get_property(np, "bus-range", NULL);
556
557 /* Map registers */
558 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
559 if (reg == NULL) {
560 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
561 goto fail;
562 }
563
564 /* Allocate the host controller data structure */
565 hose = pcibios_alloc_controller(np);
566 if (!hose)
567 goto fail;
568
569 hose->first_busno = bus_range ? bus_range[0] : 0x0;
570 hose->last_busno = bus_range ? bus_range[1] : 0xff;
571
572 /* Setup config space */
d234b3c3
SO		 573 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4,
574 PPC_INDIRECT_TYPE_SET_CFG_TYPE);
5738ec6d
BH		 575
576 /* Disable all windows */
577 writel(0, reg + PCIX0_POM0SA);
578 writel(0, reg + PCIX0_POM1SA);
579 writel(0, reg + PCIX0_POM2SA);
580 writel(0, reg + PCIX0_PIM0SA);
581 writel(0, reg + PCIX0_PIM1SA);
582 writel(0, reg + PCIX0_PIM2SA);
583 if (big_pim) {
584 writel(0, reg + PCIX0_PIM0SAH);
585 writel(0, reg + PCIX0_PIM2SAH);
586 }
587
588 /* Parse outbound mapping resources */
589 pci_process_bridge_OF_ranges(hose, np, primary);
590
591 /* Parse inbound mapping resources */
592 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
593 goto fail;
594
595 /* Configure outbound ranges POMs */
596 ppc4xx_configure_pcix_POMs(hose, reg);
597
598 /* Configure inbound ranges PIMs */
599 ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi);
600
601 /* We don't need the registers anymore */
602 iounmap(reg);
603 return;
604
605 fail:
606 if (hose)
607 pcibios_free_controller(hose);
608 if (reg)
609 iounmap(reg);
610}
611
a2d2e1ec
BH		 612#ifdef CONFIG_PPC4xx_PCI_EXPRESS
613
5738ec6d
BH		 614/*
615 * 4xx PCI-Express part
a2d2e1ec
BH		 616 *
617 * We support 3 parts currently based on the compatible property:
618 *
accf5ef2 619 * ibm,plb-pciex-440spe
a2d2e1ec 620 * ibm,plb-pciex-405ex
66b7e504 621 * ibm,plb-pciex-460ex
a2d2e1ec
BH		 622 *
623 * Anything else will be rejected for now as they are all subtly
624 * different unfortunately.
625 *
5738ec6d 626 */
a2d2e1ec 627
78994e24 628#define MAX_PCIE_BUS_MAPPED 0x40
a2d2e1ec
BH		 629
630struct ppc4xx_pciex_port
631{
632 struct pci_controller *hose;
633 struct device_node *node;
634 unsigned int index;
635 int endpoint;
035ee428
BH		 636 int link;
637 int has_ibpre;
a2d2e1ec
BH		 638 unsigned int sdr_base;
639 dcr_host_t dcrs;
640 struct resource cfg_space;
641 struct resource utl_regs;
035ee428 642 void __iomem *utl_base;
a2d2e1ec
BH		 643};
644
645static struct ppc4xx_pciex_port *ppc4xx_pciex_ports;
646static unsigned int ppc4xx_pciex_port_count;
647
648struct ppc4xx_pciex_hwops
649{
650 int (*core_init)(struct device_node *np);
651 int (*port_init_hw)(struct ppc4xx_pciex_port *port);
652 int (*setup_utl)(struct ppc4xx_pciex_port *port);
653};
654
655static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops;
656
657#ifdef CONFIG_44x
658
659/* Check various reset bits of the 440SPe PCIe core */
660static int __init ppc440spe_pciex_check_reset(struct device_node *np)
661{
662 u32 valPE0, valPE1, valPE2;
663 int err = 0;
664
665 /* SDR0_PEGPLLLCT1 reset */
666 if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) {
667 /*
668 * the PCIe core was probably already initialised
669 * by firmware - let's re-reset RCSSET regs
670 *
671 * -- Shouldn't we also re-reset the whole thing ? -- BenH
672 */
673 pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n");
674 mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000);
675 mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000);
676 mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000);
677 }
678
679 valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET);
680 valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET);
681 valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET);
682
683 /* SDR0_PExRCSSET rstgu */
684 if (!(valPE0 & 0x01000000) ||
685 !(valPE1 & 0x01000000) ||
686 !(valPE2 & 0x01000000)) {
687 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
688 err = -1;
689 }
690
691 /* SDR0_PExRCSSET rstdl */
692 if (!(valPE0 & 0x00010000) ||
693 !(valPE1 & 0x00010000) ||
694 !(valPE2 & 0x00010000)) {
695 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
696 err = -1;
697 }
698
699 /* SDR0_PExRCSSET rstpyn */
700 if ((valPE0 & 0x00001000) ||
701 (valPE1 & 0x00001000) ||
702 (valPE2 & 0x00001000)) {
703 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
704 err = -1;
705 }
706
707 /* SDR0_PExRCSSET hldplb */
708 if ((valPE0 & 0x10000000) ||
709 (valPE1 & 0x10000000) ||
710 (valPE2 & 0x10000000)) {
711 printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
712 err = -1;
713 }
714
715 /* SDR0_PExRCSSET rdy */
716 if ((valPE0 & 0x00100000) ||
717 (valPE1 & 0x00100000) ||
718 (valPE2 & 0x00100000)) {
719 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
720 err = -1;
721 }
722
723 /* SDR0_PExRCSSET shutdown */
724 if ((valPE0 & 0x00000100) ||
725 (valPE1 & 0x00000100) ||
726 (valPE2 & 0x00000100)) {
727 printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
728 err = -1;
729 }
730
731 return err;
732}
733
734/* Global PCIe core initializations for 440SPe core */
735static int __init ppc440spe_pciex_core_init(struct device_node *np)
736{
737 int time_out = 20;
738
739 /* Set PLL clock receiver to LVPECL */
6e42b21b 740 dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
a2d2e1ec
BH		 741
742 /* Shouldn't we do all the calibration stuff etc... here ? */
743 if (ppc440spe_pciex_check_reset(np))
744 return -ENXIO;
745
746 if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) {
747 printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration "
748 "failed (0x%08x)\n",
749 mfdcri(SDR0, PESDR0_PLLLCT2));
750 return -1;
751 }
752
753 /* De-assert reset of PCIe PLL, wait for lock */
6e42b21b 754 dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
a2d2e1ec
BH		 755 udelay(3);
756
757 while (time_out) {
758 if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) {
759 time_out--;
760 udelay(1);
761 } else
762 break;
763 }
764 if (!time_out) {
765 printk(KERN_INFO "PCIE: VCO output not locked\n");
766 return -1;
767 }
768
769 pr_debug("PCIE initialization OK\n");
770
771 return 3;
772}
773
774static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
775{
776 u32 val = 1 << 24;
777
778 if (port->endpoint)
779 val = PTYPE_LEGACY_ENDPOINT << 20;
780 else
781 val = PTYPE_ROOT_PORT << 20;
782
783 if (port->index == 0)
784 val |= LNKW_X8 << 12;
785 else
786 val |= LNKW_X4 << 12;
787
788 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
789 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);
accf5ef2 790 if (ppc440spe_revA())
a2d2e1ec
BH		 791 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);
792 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);
793 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);
794 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);
795 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);
796 if (port->index == 0) {
797 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,
798 0x35000000);
799 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,
800 0x35000000);
801 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,
802 0x35000000);
803 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
804 0x35000000);
805 }
6e42b21b
VB		 806 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
807 (1 << 24) | (1 << 16), 1 << 12);
a2d2e1ec
BH		 808
809 return 0;
810}
811
035ee428
BH		 812static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
813{
814 return ppc440spe_pciex_init_port_hw(port);
815}
816
817static int ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
a2d2e1ec 818{
035ee428
BH		 819 int rc = ppc440spe_pciex_init_port_hw(port);
820
821 port->has_ibpre = 1;
822
823 return rc;
824}
a2d2e1ec 825
035ee428
BH		 826static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port)
827{
a2d2e1ec
BH		 828 /* XXX Check what that value means... I hate magic */
829 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800);
830
a2d2e1ec
BH		 831 /*
832 * Set buffer allocations and then assert VRB and TXE.
833 */
035ee428
BH		 834 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
835 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
836 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000);
837 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000);
838 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000);
839 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000);
840 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
841 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
a2d2e1ec 842
035ee428
BH		 843 return 0;
844}
845
846static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port)
847{
848 /* Report CRS to the operating system */
849 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
a2d2e1ec
BH		 850
851 return 0;
852}
853
854static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
855{
856 .core_init = ppc440spe_pciex_core_init,
035ee428 857 .port_init_hw = ppc440speA_pciex_init_port_hw,
a2d2e1ec
BH		 858 .setup_utl = ppc440speA_pciex_init_utl,
859};
860
861static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
862{
863 .core_init = ppc440spe_pciex_core_init,
035ee428
BH		 864 .port_init_hw = ppc440speB_pciex_init_port_hw,
865 .setup_utl = ppc440speB_pciex_init_utl,
a2d2e1ec
BH		 866};
867
66b7e504
SR		 868static int __init ppc460ex_pciex_core_init(struct device_node *np)
869{
870 /* Nothing to do, return 2 ports */
871 return 2;
872}
873
874static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
875{
876 u32 val;
877 u32 utlset1;
878
5f91925c 879 if (port->endpoint)
66b7e504 880 val = PTYPE_LEGACY_ENDPOINT << 20;
5f91925c 881 else
66b7e504 882 val = PTYPE_ROOT_PORT << 20;
66b7e504
SR		 883
884 if (port->index == 0) {
885 val |= LNKW_X1 << 12;
5f91925c 886 utlset1 = 0x20000000;
66b7e504
SR		 887 } else {
888 val |= LNKW_X4 << 12;
5f91925c 889 utlset1 = 0x20101101;
66b7e504
SR		 890 }
891
892 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
893 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
894 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
895
896 switch (port->index) {
897 case 0:
898 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
e30c9875 899 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
66b7e504
SR		 900 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
901
902 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);
903 break;
904
905 case 1:
906 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);
907 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
908 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
909 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
e30c9875
TM		 910 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130);
911 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130);
912 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130);
913 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130);
66b7e504
SR		 914 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
915 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
916 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);
917 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);
918
919 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000);
920 break;
921 }
922
923 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
924 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
925 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
926
927 /* Poll for PHY reset */
928 /* XXX FIXME add timeout */
929 switch (port->index) {
930 case 0:
931 while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1))
932 udelay(10);
933 break;
934 case 1:
935 while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1))
936 udelay(10);
937 break;
938 }
939
940 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
941 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
942 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
943 PESDRx_RCSSET_RSTPYN);
944
945 port->has_ibpre = 1;
946
947 return 0;
948}
949
950static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
951{
952 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
953
954 /*
955 * Set buffer allocations and then assert VRB and TXE.
956 */
957 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c);
958 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
959 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
960 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
961 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000);
962 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
963 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
964 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000);
965 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
966
967 return 0;
968}
969
970static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
971{
972 .core_init = ppc460ex_pciex_core_init,
973 .port_init_hw = ppc460ex_pciex_init_port_hw,
974 .setup_utl = ppc460ex_pciex_init_utl,
975};
976
e2efc09e
TM		 977static int __init ppc460sx_pciex_core_init(struct device_node *np)
978{
979 /* HSS drive amplitude */
980 mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211);
981 mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211);
982 mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211);
983 mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211);
984 mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211);
985 mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211);
986 mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211);
987 mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211);
988
989 mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211);
990 mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211);
991 mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211);
992 mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211);
993
994 mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211);
995 mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211);
996 mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211);
997 mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211);
998
999 /* HSS TX pre-emphasis */
1000 mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987);
1001 mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987);
1002 mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987);
1003 mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987);
1004 mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987);
1005 mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987);
1006 mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987);
1007 mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987);
1008
1009 mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987);
1010 mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987);
1011 mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987);
1012 mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987);
1013
1014 mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987);
1015 mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987);
1016 mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987);
1017 mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987);
1018
1019 /* HSS TX calibration control */
1020 mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222);
1021 mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000);
1022 mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000);
1023
1024 /* HSS TX slew control */
1025 mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF);
1026 mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000);
1027 mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000);
1028
1029 udelay(100);
1030
1031 /* De-assert PLLRESET */
1032 dcri_clrset(SDR0, PESDR0_PLLLCT2, 0x00000100, 0);
1033
1034 /* Reset DL, UTL, GPL before configuration */
1035 mtdcri(SDR0, PESDR0_460SX_RCSSET,
1036 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
1037 mtdcri(SDR0, PESDR1_460SX_RCSSET,
1038 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
1039 mtdcri(SDR0, PESDR2_460SX_RCSSET,
1040 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
1041
1042 udelay(100);
1043
1044 /*
1045 * If bifurcation is not enabled, u-boot would have disabled the
1046 * third PCIe port
1047 */
1048 if (((mfdcri(SDR0, PESDR1_460SX_HSSCTLSET) & 0x00000001) ==
1049 0x00000001)) {
1050 printk(KERN_INFO "PCI: PCIE bifurcation setup successfully.\n");
1051 printk(KERN_INFO "PCI: Total 3 PCIE ports are present\n");
1052 return 3;
1053 }
1054
1055 printk(KERN_INFO "PCI: Total 2 PCIE ports are present\n");
1056 return 2;
1057}
1058
1059static int ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1060{
1061
1062 if (port->endpoint)
1063 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
1064 0x01000000, 0);
1065 else
1066 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
1067 0, 0x01000000);
1068
1069 /*Gen-1*/
1070 mtdcri(SDR0, port->sdr_base + PESDRn_460SX_RCEI, 0x08000000);
1071
1072 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
1073 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL),
1074 PESDRx_RCSSET_RSTPYN);
1075
1076 port->has_ibpre = 1;
1077
1078 return 0;
1079}
1080
1081static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port)
1082{
1083 /* Max 128 Bytes */
1084 out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000);
1085 return 0;
1086}
1087
1088static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = {
1089 .core_init = ppc460sx_pciex_core_init,
1090 .port_init_hw = ppc460sx_pciex_init_port_hw,
1091 .setup_utl = ppc460sx_pciex_init_utl,
1092};
1093
a2d2e1ec
BH		 1094#endif /* CONFIG_44x */
1095
1096#ifdef CONFIG_40x
1097
1098static int __init ppc405ex_pciex_core_init(struct device_node *np)
1099{
1100 /* Nothing to do, return 2 ports */
1101 return 2;
1102}
1103
1104static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port)
1105{
1106 /* Assert the PE0_PHY reset */
1107 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);
1108 msleep(1);
1109
1110 /* deassert the PE0_hotreset */
1111 if (port->endpoint)
1112 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);
1113 else
1114 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);
1115
1116 /* poll for phy !reset */
1117 /* XXX FIXME add timeout */
1118 while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000))
1119 ;
1120
1121 /* deassert the PE0_gpl_utl_reset */
1122 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);
1123}
1124
1125static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1126{
1127 u32 val;
1128
1129 if (port->endpoint)
1130 val = PTYPE_LEGACY_ENDPOINT;
1131 else
1132 val = PTYPE_ROOT_PORT;
1133
1134 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,
1135 1 << 24 | val << 20 | LNKW_X1 << 12);
1136
1137 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
1138 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
1139 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);
1140 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);
1141
1142 /*
1143 * Only reset the PHY when no link is currently established.
1144 * This is for the Atheros PCIe board which has problems to establish
1145 * the link (again) after this PHY reset. All other currently tested
1146 * PCIe boards don't show this problem.
1147 * This has to be re-tested and fixed in a later release!
1148 */
a2d2e1ec
BH		 1149 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
1150 if (!(val & 0x00001000))
1151 ppc405ex_pcie_phy_reset(port);
a2d2e1ec
BH		 1152
1153 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */
1154
55aaf6ec
SR		 1155 port->has_ibpre = 1;
1156
a2d2e1ec
BH		 1157 return 0;
1158}
1159
1160static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
1161{
a2d2e1ec
BH		 1162 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
1163
a2d2e1ec
BH		 1164 /*
1165 * Set buffer allocations and then assert VRB and TXE.
1166 */
035ee428
BH		 1167 out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000);
1168 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
1169 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
1170 out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000);
1171 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
1172 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
1173 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
1174 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
a2d2e1ec 1175
035ee428 1176 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
a2d2e1ec
BH		 1177
1178 return 0;
1179}
1180
1181static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
1182{
1183 .core_init = ppc405ex_pciex_core_init,
1184 .port_init_hw = ppc405ex_pciex_init_port_hw,
1185 .setup_utl = ppc405ex_pciex_init_utl,
1186};
1187
1188#endif /* CONFIG_40x */
1189
1190
1191/* Check that the core has been initied and if not, do it */
1192static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
1193{
1194 static int core_init;
1195 int count = -ENODEV;
1196
1197 if (core_init++)
1198 return 0;
1199
1200#ifdef CONFIG_44x
accf5ef2
SR		 1201 if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) {
1202 if (ppc440spe_revA())
1203 ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops;
1204 else
1205 ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
1206 }
66b7e504
SR		 1207 if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
1208 ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
e2efc09e
TM		 1209 if (of_device_is_compatible(np, "ibm,plb-pciex-460sx"))
1210 ppc4xx_pciex_hwops = &ppc460sx_pcie_hwops;
a2d2e1ec
BH		 1211#endif /* CONFIG_44x */
1212#ifdef CONFIG_40x
1213 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
1214 ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops;
1215#endif
1216 if (ppc4xx_pciex_hwops == NULL) {
1217 printk(KERN_WARNING "PCIE: unknown host type %s\n",
1218 np->full_name);
1219 return -ENODEV;
1220 }
1221
1222 count = ppc4xx_pciex_hwops->core_init(np);
1223 if (count > 0) {
1224 ppc4xx_pciex_ports =
1225 kzalloc(count * sizeof(struct ppc4xx_pciex_port),
1226 GFP_KERNEL);
1227 if (ppc4xx_pciex_ports) {
1228 ppc4xx_pciex_port_count = count;
1229 return 0;
1230 }
1231 printk(KERN_WARNING "PCIE: failed to allocate ports array\n");
1232 return -ENOMEM;
1233 }
1234 return -ENODEV;
1235}
1236
1237static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port)
1238{
1239 /* We map PCI Express configuration based on the reg property */
1240 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH,
1241 RES_TO_U32_HIGH(port->cfg_space.start));
1242 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL,
1243 RES_TO_U32_LOW(port->cfg_space.start));
1244
1245 /* XXX FIXME: Use size from reg property. For now, map 512M */
1246 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001);
1247
1248 /* We map UTL registers based on the reg property */
1249 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH,
1250 RES_TO_U32_HIGH(port->utl_regs.start));
1251 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL,
1252 RES_TO_U32_LOW(port->utl_regs.start));
1253
1254 /* XXX FIXME: Use size from reg property */
1255 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001);
1256
1257 /* Disable all other outbound windows */
1258 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0);
1259 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0);
1260 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0);
1261 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
1262}
1263
035ee428
BH		 1264static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
1265 unsigned int sdr_offset,
1266 unsigned int mask,
1267 unsigned int value,
1268 int timeout_ms)
a2d2e1ec 1269{
a2d2e1ec
BH		 1270 u32 val;
1271
035ee428
BH		 1272 while(timeout_ms--) {
1273 val = mfdcri(SDR0, port->sdr_base + sdr_offset);
1274 if ((val & mask) == value) {
1275 pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
1276 port->index, sdr_offset, timeout_ms, val);
1277 return 0;
1278 }
1279 msleep(1);
1280 }
1281 return -1;
1282}
1283
1284static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1285{
1286 int rc = 0;
a2d2e1ec
BH		 1287
1288 /* Init HW */
1289 if (ppc4xx_pciex_hwops->port_init_hw)
1290 rc = ppc4xx_pciex_hwops->port_init_hw(port);
1291 if (rc != 0)
1292 return rc;
1293
035ee428 1294 printk(KERN_INFO "PCIE%d: Checking link...\n",
a2d2e1ec 1295 port->index);
a2d2e1ec 1296
035ee428
BH		 1297 /* Wait for reset to complete */
1298 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
1299 printk(KERN_WARNING "PCIE%d: PGRST failed\n",
1300 port->index);
a2d2e1ec
BH		 1301 return -1;
1302 }
1303
035ee428
BH		 1304 /* Check for card presence detect if supported, if not, just wait for
1305 * link unconditionally.
1306 *
1307 * note that we don't fail if there is no link, we just filter out
1308 * config space accesses. That way, it will be easier to implement
1309 * hotplug later on.
a2d2e1ec 1310 */
035ee428
BH		 1311 if (!port->has_ibpre ||
1312 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1313 1 << 28, 1 << 28, 100)) {
1314 printk(KERN_INFO
1315 "PCIE%d: Device detected, waiting for link...\n",
a2d2e1ec 1316 port->index);
035ee428
BH		 1317 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1318 0x1000, 0x1000, 2000))
1319 printk(KERN_WARNING
1320 "PCIE%d: Link up failed\n", port->index);
1321 else {
1322 printk(KERN_INFO
1323 "PCIE%d: link is up !\n", port->index);
1324 port->link = 1;
1325 }
1326 } else
1327 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
a2d2e1ec
BH		 1328
1329 /*
1330 * Initialize mapping: disable all regions and configure
1331 * CFG and REG regions based on resources in the device tree
1332 */
1333 ppc4xx_pciex_port_init_mapping(port);
1334
1335 /*
035ee428
BH		 1336 * Map UTL
1337 */
1338 port->utl_base = ioremap(port->utl_regs.start, 0x100);
1339 BUG_ON(port->utl_base == NULL);
1340
1341 /*
1342 * Setup UTL registers --BenH.
a2d2e1ec
BH		 1343 */
1344 if (ppc4xx_pciex_hwops->setup_utl)
1345 ppc4xx_pciex_hwops->setup_utl(port);
1346
1347 /*
1348 * Check for VC0 active and assert RDY.
1349 */
035ee428
BH		 1350 if (port->link &&
1351 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
1352 1 << 16, 1 << 16, 5000)) {
1353 printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index);
1354 port->link = 0;
a2d2e1ec 1355 }
035ee428 1356
6e42b21b 1357 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
a2d2e1ec
BH		 1358 msleep(100);
1359
1360 return 0;
1361}
1362
1363static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port,
1364 struct pci_bus *bus,
1365 unsigned int devfn)
1366{
1367 static int message;
1368
1369 /* Endpoint can not generate upstream(remote) config cycles */
1370 if (port->endpoint && bus->number != port->hose->first_busno)
1371 return PCIBIOS_DEVICE_NOT_FOUND;
1372
1373 /* Check we are within the mapped range */
1374 if (bus->number > port->hose->last_busno) {
1375 if (!message) {
1376 printk(KERN_WARNING "Warning! Probing bus %u"
1377 " out of range !\n", bus->number);
1378 message++;
1379 }
1380 return PCIBIOS_DEVICE_NOT_FOUND;
1381 }
1382
1383 /* The root complex has only one device / function */
1384 if (bus->number == port->hose->first_busno && devfn != 0)
1385 return PCIBIOS_DEVICE_NOT_FOUND;
1386
1387 /* The other side of the RC has only one device as well */
1388 if (bus->number == (port->hose->first_busno + 1) &&
1389 PCI_SLOT(devfn) != 0)
1390 return PCIBIOS_DEVICE_NOT_FOUND;
1391
035ee428
BH		 1392 /* Check if we have a link */
1393 if ((bus->number != port->hose->first_busno) && !port->link)
1394 return PCIBIOS_DEVICE_NOT_FOUND;
1395
a2d2e1ec
BH		 1396 return 0;
1397}
1398
1399static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port,
1400 struct pci_bus *bus,
1401 unsigned int devfn)
1402{
1403 int relbus;
1404
1405 /* Remove the casts when we finally remove the stupid volatile
1406 * in struct pci_controller
1407 */
1408 if (bus->number == port->hose->first_busno)
1409 return (void __iomem *)port->hose->cfg_addr;
1410
1411 relbus = bus->number - (port->hose->first_busno + 1);
1412 return (void __iomem *)port->hose->cfg_data +
1413 ((relbus << 20) | (devfn << 12));
1414}
1415
1416static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
1417 int offset, int len, u32 *val)
1418{
f159edae 1419 struct pci_controller *hose = pci_bus_to_host(bus);
a2d2e1ec
BH		 1420 struct ppc4xx_pciex_port *port =
1421 &ppc4xx_pciex_ports[hose->indirect_type];
1422 void __iomem *addr;
1423 u32 gpl_cfg;
1424
1425 BUG_ON(hose != port->hose);
1426
1427 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1428 return PCIBIOS_DEVICE_NOT_FOUND;
1429
1430 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1431
1432 /*
1433 * Reading from configuration space of non-existing device can
1434 * generate transaction errors. For the read duration we suppress
1435 * assertion of machine check exceptions to avoid those.
1436 */
1437 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1438 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1439
035ee428
BH		 1440 /* Make sure no CRS is recorded */
1441 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000);
1442
a2d2e1ec
BH		 1443 switch (len) {
1444 case 1:
1445 *val = in_8((u8 *)(addr + offset));
1446 break;
1447 case 2:
1448 *val = in_le16((u16 *)(addr + offset));
1449 break;
1450 default:
1451 *val = in_le32((u32 *)(addr + offset));
1452 break;
1453 }
1454
1455 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x"
1456 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1457 bus->number, hose->first_busno, hose->last_busno,
1458 devfn, offset, len, addr + offset, *val);
1459
035ee428
BH		 1460 /* Check for CRS (440SPe rev B does that for us but heh ..) */
1461 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) {
1462 pr_debug("Got CRS !\n");
1463 if (len != 4 || offset != 0)
1464 return PCIBIOS_DEVICE_NOT_FOUND;
1465 *val = 0xffff0001;
1466 }
1467
a2d2e1ec
BH		 1468 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1469
1470 return PCIBIOS_SUCCESSFUL;
1471}
1472
1473static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
1474 int offset, int len, u32 val)
1475{
f159edae 1476 struct pci_controller *hose = pci_bus_to_host(bus);
a2d2e1ec
BH		 1477 struct ppc4xx_pciex_port *port =
1478 &ppc4xx_pciex_ports[hose->indirect_type];
1479 void __iomem *addr;
1480 u32 gpl_cfg;
1481
1482 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1483 return PCIBIOS_DEVICE_NOT_FOUND;
1484
1485 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1486
1487 /*
1488 * Reading from configuration space of non-existing device can
1489 * generate transaction errors. For the read duration we suppress
1490 * assertion of machine check exceptions to avoid those.
1491 */
1492 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1493 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1494
1495 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x"
1496 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1497 bus->number, hose->first_busno, hose->last_busno,
1498 devfn, offset, len, addr + offset, val);
1499
1500 switch (len) {
1501 case 1:
1502 out_8((u8 *)(addr + offset), val);
1503 break;
1504 case 2:
1505 out_le16((u16 *)(addr + offset), val);
1506 break;
1507 default:
1508 out_le32((u32 *)(addr + offset), val);
1509 break;
1510 }
1511
1512 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1513
1514 return PCIBIOS_SUCCESSFUL;
1515}
1516
1517static struct pci_ops ppc4xx_pciex_pci_ops =
1518{
1519 .read = ppc4xx_pciex_read_config,
1520 .write = ppc4xx_pciex_write_config,
1521};
1522
84d727a1
BH		 1523static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port *port,
1524 struct pci_controller *hose,
1525 void __iomem *mbase,
1526 u64 plb_addr,
1527 u64 pci_addr,
1528 u64 size,
1529 unsigned int flags,
1530 int index)
1531{
1532 u32 lah, lal, pciah, pcial, sa;
1533
1534 if (!is_power_of_2(size) ||
1535 (index < 2 && size < 0x100000) ||
1536 (index == 2 && size < 0x100) ||
1537 (plb_addr & (size - 1)) != 0) {
1538 printk(KERN_WARNING "%s: Resource out of range\n",
1539 hose->dn->full_name);
1540 return -1;
1541 }
1542
1543 /* Calculate register values */
1544 lah = RES_TO_U32_HIGH(plb_addr);
1545 lal = RES_TO_U32_LOW(plb_addr);
1546 pciah = RES_TO_U32_HIGH(pci_addr);
1547 pcial = RES_TO_U32_LOW(pci_addr);
1548 sa = (0xffffffffu << ilog2(size)) | 0x1;
1549
1550 /* Program register values */
1551 switch (index) {
1552 case 0:
1553 out_le32(mbase + PECFG_POM0LAH, pciah);
1554 out_le32(mbase + PECFG_POM0LAL, pcial);
1555 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);
1556 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);
1557 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);
1558 /* Note that 3 here means enabled | single region */
1559 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, sa | 3);
1560 break;
1561 case 1:
1562 out_le32(mbase + PECFG_POM1LAH, pciah);
1563 out_le32(mbase + PECFG_POM1LAL, pcial);
1564 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);
1565 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);
1566 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);
1567 /* Note that 3 here means enabled | single region */
1568 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, sa | 3);
1569 break;
1570 case 2:
1571 out_le32(mbase + PECFG_POM2LAH, pciah);
1572 out_le32(mbase + PECFG_POM2LAL, pcial);
1573 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah);
1574 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);
1575 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);
1576 /* Note that 3 here means enabled | IO space !!! */
1577 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, sa | 3);
1578 break;
1579 }
1580
1581 return 0;
1582}
1583
a2d2e1ec
BH		 1584static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
1585 struct pci_controller *hose,
1586 void __iomem *mbase)
1587{
84d727a1 1588 int i, j, found_isa_hole = 0;
a2d2e1ec
BH		 1589
1590 /* Setup outbound memory windows */
1591 for (i = j = 0; i < 3; i++) {
1592 struct resource *res = &hose->mem_resources[i];
1593
1594 /* we only care about memory windows */
1595 if (!(res->flags & IORESOURCE_MEM))
1596 continue;
1597 if (j > 1) {
1598 printk(KERN_WARNING "%s: Too many ranges\n",
1599 port->node->full_name);
1600 break;
1601 }
1602
84d727a1
BH		 1603 /* Configure the resource */
1604 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1605 res->start,
1606 res->start - hose->pci_mem_offset,
1607 res->end + 1 - res->start,
1608 res->flags,
1609 j) == 0) {
1610 j++;
1611
1612 /* If the resource PCI address is 0 then we have our
1613 * ISA memory hole
1614 */
1615 if (res->start == hose->pci_mem_offset)
1616 found_isa_hole = 1;
a2d2e1ec 1617 }
a2d2e1ec
BH		 1618 }
1619
84d727a1
BH		 1620 /* Handle ISA memory hole if not already covered */
1621 if (j <= 1 && !found_isa_hole && hose->isa_mem_size)
1622 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1623 hose->isa_mem_phys, 0,
1624 hose->isa_mem_size, 0, j) == 0)
1625 printk(KERN_INFO "%s: Legacy ISA memory support enabled\n",
1626 hose->dn->full_name);
1627
1628 /* Configure IO, always 64K starting at 0. We hard wire it to 64K !
1629 * Note also that it -has- to be region index 2 on this HW
1630 */
1631 if (hose->io_resource.flags & IORESOURCE_IO)
1632 ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1633 hose->io_base_phys, 0,
1634 0x10000, IORESOURCE_IO, 2);
a2d2e1ec
BH		 1635}
1636
1637static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
1638 struct pci_controller *hose,
1639 void __iomem *mbase,
1640 struct resource *res)
1641{
1642 resource_size_t size = res->end - res->start + 1;
1643 u64 sa;
1644
80daac3f
SR		 1645 if (port->endpoint) {
1646 resource_size_t ep_addr = 0;
1647 resource_size_t ep_size = 32 << 20;
1648
1649 /* Currently we map a fixed 64MByte window to PLB address
1650 * 0 (SDRAM). This should probably be configurable via a dts
1651 * property.
1652 */
1653
1654 /* Calculate window size */
d258e64e 1655 sa = (0xffffffffffffffffull << ilog2(ep_size));
80daac3f
SR		 1656
1657 /* Setup BAR0 */
1658 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1659 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) |
1660 PCI_BASE_ADDRESS_MEM_TYPE_64);
a2d2e1ec 1661
80daac3f
SR		 1662 /* Disable BAR1 & BAR2 */
1663 out_le32(mbase + PECFG_BAR1MPA, 0);
1664 out_le32(mbase + PECFG_BAR2HMPA, 0);
1665 out_le32(mbase + PECFG_BAR2LMPA, 0);
a2d2e1ec 1666
80daac3f
SR		 1667 out_le32(mbase + PECFG_PIM01SAH, RES_TO_U32_HIGH(sa));
1668 out_le32(mbase + PECFG_PIM01SAL, RES_TO_U32_LOW(sa));
1669
1670 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr));
1671 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(ep_addr));
1672 } else {
1673 /* Calculate window size */
d258e64e 1674 sa = (0xffffffffffffffffull << ilog2(size));
80daac3f
SR		 1675 if (res->flags & IORESOURCE_PREFETCH)
1676 sa |= 0x8;
1677
1678 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1679 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa));
1680
1681 /* The setup of the split looks weird to me ... let's see
1682 * if it works
1683 */
1684 out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
1685 out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
1686 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
1687 out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
1688 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
1689 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
1690
1691 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start));
1692 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start));
1693 }
a2d2e1ec
BH		 1694
1695 /* Enable inbound mapping */
1696 out_le32(mbase + PECFG_PIMEN, 0x1);
1697
a2d2e1ec
BH		 1698 /* Enable I/O, Mem, and Busmaster cycles */
1699 out_le16(mbase + PCI_COMMAND,
1700 in_le16(mbase + PCI_COMMAND) |
1701 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1702}
1703
1704static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port)
1705{
1706 struct resource dma_window;
1707 struct pci_controller *hose = NULL;
1708 const int *bus_range;
1709 int primary = 0, busses;
1710 void __iomem *mbase = NULL, *cfg_data = NULL;
80daac3f
SR		 1711 const u32 *pval;
1712 u32 val;
a2d2e1ec
BH		 1713
1714 /* Check if primary bridge */
1715 if (of_get_property(port->node, "primary", NULL))
1716 primary = 1;
1717
1718 /* Get bus range if any */
1719 bus_range = of_get_property(port->node, "bus-range", NULL);
1720
1721 /* Allocate the host controller data structure */
1722 hose = pcibios_alloc_controller(port->node);
1723 if (!hose)
1724 goto fail;
1725
1726 /* We stick the port number in "indirect_type" so the config space
1727 * ops can retrieve the port data structure easily
1728 */
1729 hose->indirect_type = port->index;
1730
1731 /* Get bus range */
1732 hose->first_busno = bus_range ? bus_range[0] : 0x0;
1733 hose->last_busno = bus_range ? bus_range[1] : 0xff;
1734
1735 /* Because of how big mapping the config space is (1M per bus), we
1736 * limit how many busses we support. In the long run, we could replace
1737 * that with something akin to kmap_atomic instead. We set aside 1 bus
1738 * for the host itself too.
1739 */
1740 busses = hose->last_busno - hose->first_busno; /* This is off by 1 */
1741 if (busses > MAX_PCIE_BUS_MAPPED) {
1742 busses = MAX_PCIE_BUS_MAPPED;
1743 hose->last_busno = hose->first_busno + busses;
1744 }
1745
80daac3f
SR		 1746 if (!port->endpoint) {
1747 /* Only map the external config space in cfg_data for
1748 * PCIe root-complexes. External space is 1M per bus
1749 */
1750 cfg_data = ioremap(port->cfg_space.start +
1751 (hose->first_busno + 1) * 0x100000,
1752 busses * 0x100000);
1753 if (cfg_data == NULL) {
1754 printk(KERN_ERR "%s: Can't map external config space !",
1755 port->node->full_name);
1756 goto fail;
1757 }
1758 hose->cfg_data = cfg_data;
1759 }
1760
1761 /* Always map the host config space in cfg_addr.
1762 * Internal space is 4K
a2d2e1ec 1763 */
a2d2e1ec 1764 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
80daac3f
SR		 1765 if (mbase == NULL) {
1766 printk(KERN_ERR "%s: Can't map internal config space !",
a2d2e1ec
BH		 1767 port->node->full_name);
1768 goto fail;
1769 }
a2d2e1ec
BH		 1770 hose->cfg_addr = mbase;
1771
1772 pr_debug("PCIE %s, bus %d..%d\n", port->node->full_name,
1773 hose->first_busno, hose->last_busno);
1774 pr_debug(" config space mapped at: root @0x%p, other @0x%p\n",
1775 hose->cfg_addr, hose->cfg_data);
1776
1777 /* Setup config space */
1778 hose->ops = &ppc4xx_pciex_pci_ops;
1779 port->hose = hose;
1780 mbase = (void __iomem *)hose->cfg_addr;
1781
80daac3f
SR		 1782 if (!port->endpoint) {
1783 /*
1784 * Set bus numbers on our root port
1785 */
1786 out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno);
1787 out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1);
1788 out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno);
1789 }
a2d2e1ec
BH		 1790
1791 /*
1792 * OMRs are already reset, also disable PIMs
1793 */
1794 out_le32(mbase + PECFG_PIMEN, 0);
1795
1796 /* Parse outbound mapping resources */
1797 pci_process_bridge_OF_ranges(hose, port->node, primary);
1798
1799 /* Parse inbound mapping resources */
1800 if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0)
1801 goto fail;
1802
1803 /* Configure outbound ranges POMs */
1804 ppc4xx_configure_pciex_POMs(port, hose, mbase);
1805
1806 /* Configure inbound ranges PIMs */
1807 ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window);
1808
1809 /* The root complex doesn't show up if we don't set some vendor
80daac3f
SR		 1810 * and device IDs into it. The defaults below are the same bogus
1811 * one that the initial code in arch/ppc had. This can be
1812 * overwritten by setting the "vendor-id/device-id" properties
1813 * in the pciex node.
a2d2e1ec 1814 */
a2d2e1ec 1815
80daac3f
SR		 1816 /* Get the (optional) vendor-/device-id from the device-tree */
1817 pval = of_get_property(port->node, "vendor-id", NULL);
1818 if (pval) {
1819 val = *pval;
1820 } else {
1821 if (!port->endpoint)
1822 val = 0xaaa0 + port->index;
1823 else
1824 val = 0xeee0 + port->index;
1825 }
1826 out_le16(mbase + 0x200, val);
1827
1828 pval = of_get_property(port->node, "device-id", NULL);
1829 if (pval) {
1830 val = *pval;
1831 } else {
1832 if (!port->endpoint)
1833 val = 0xbed0 + port->index;
1834 else
1835 val = 0xfed0 + port->index;
1836 }
1837 out_le16(mbase + 0x202, val);
1838
1839 if (!port->endpoint) {
1840 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
1841 out_le32(mbase + 0x208, 0x06040001);
1842
1843 printk(KERN_INFO "PCIE%d: successfully set as root-complex\n",
1844 port->index);
1845 } else {
1846 /* Set Class Code to Processor/PPC */
1847 out_le32(mbase + 0x208, 0x0b200001);
1848
1849 printk(KERN_INFO "PCIE%d: successfully set as endpoint\n",
1850 port->index);
1851 }
a2d2e1ec 1852
a2d2e1ec
BH		 1853 return;
1854 fail:
1855 if (hose)
1856 pcibios_free_controller(hose);
1857 if (cfg_data)
1858 iounmap(cfg_data);
1859 if (mbase)
1860 iounmap(mbase);
1861}
1862
5738ec6d
BH		 1863static void __init ppc4xx_probe_pciex_bridge(struct device_node *np)
1864{
a2d2e1ec
BH		 1865 struct ppc4xx_pciex_port *port;
1866 const u32 *pval;
1867 int portno;
1868 unsigned int dcrs;
80daac3f 1869 const char *val;
a2d2e1ec
BH		 1870
1871 /* First, proceed to core initialization as we assume there's
1872 * only one PCIe core in the system
1873 */
1874 if (ppc4xx_pciex_check_core_init(np))
1875 return;
1876
1877 /* Get the port number from the device-tree */
1878 pval = of_get_property(np, "port", NULL);
1879 if (pval == NULL) {
1880 printk(KERN_ERR "PCIE: Can't find port number for %s\n",
1881 np->full_name);
1882 return;
1883 }
1884 portno = *pval;
1885 if (portno >= ppc4xx_pciex_port_count) {
1886 printk(KERN_ERR "PCIE: port number out of range for %s\n",
1887 np->full_name);
1888 return;
1889 }
1890 port = &ppc4xx_pciex_ports[portno];
1891 port->index = portno;
995ada8d
SR		 1892
1893 /*
1894 * Check if device is enabled
1895 */
1896 if (!of_device_is_available(np)) {
1897 printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index);
1898 return;
1899 }
1900
a2d2e1ec
BH		 1901 port->node = of_node_get(np);
1902 pval = of_get_property(np, "sdr-base", NULL);
1903 if (pval == NULL) {
1904 printk(KERN_ERR "PCIE: missing sdr-base for %s\n",
1905 np->full_name);
1906 return;
1907 }
1908 port->sdr_base = *pval;
1909
80daac3f
SR		 1910 /* Check if device_type property is set to "pci" or "pci-endpoint".
1911 * Resulting from this setup this PCIe port will be configured
1912 * as root-complex or as endpoint.
1913 */
1914 val = of_get_property(port->node, "device_type", NULL);
1915 if (!strcmp(val, "pci-endpoint")) {
1916 port->endpoint = 1;
1917 } else if (!strcmp(val, "pci")) {
1918 port->endpoint = 0;
1919 } else {
1920 printk(KERN_ERR "PCIE: missing or incorrect device_type for %s\n",
1921 np->full_name);
1922 return;
1923 }
035ee428 1924
a2d2e1ec
BH		 1925 /* Fetch config space registers address */
1926 if (of_address_to_resource(np, 0, &port->cfg_space)) {
1927 printk(KERN_ERR "%s: Can't get PCI-E config space !",
1928 np->full_name);
1929 return;
1930 }
1931 /* Fetch host bridge internal registers address */
1932 if (of_address_to_resource(np, 1, &port->utl_regs)) {
1933 printk(KERN_ERR "%s: Can't get UTL register base !",
1934 np->full_name);
1935 return;
1936 }
1937
1938 /* Map DCRs */
1939 dcrs = dcr_resource_start(np, 0);
1940 if (dcrs == 0) {
1941 printk(KERN_ERR "%s: Can't get DCR register base !",
1942 np->full_name);
1943 return;
1944 }
1945 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
1946
1947 /* Initialize the port specific registers */
035ee428
BH		 1948 if (ppc4xx_pciex_port_init(port)) {
1949 printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index);
a2d2e1ec 1950 return;
035ee428 1951 }
a2d2e1ec
BH		 1952
1953 /* Setup the linux hose data structure */
1954 ppc4xx_pciex_port_setup_hose(port);
5738ec6d
BH		 1955}
1956
a2d2e1ec
BH		 1957#endif /* CONFIG_PPC4xx_PCI_EXPRESS */
1958
5738ec6d
BH		 1959static int __init ppc4xx_pci_find_bridges(void)
1960{
1961 struct device_node *np;
1962
41b6a085
BH		 1963 ppc_pci_flags |= PPC_PCI_ENABLE_PROC_DOMAINS | PPC_PCI_COMPAT_DOMAIN_0;
1964
a2d2e1ec 1965#ifdef CONFIG_PPC4xx_PCI_EXPRESS
5738ec6d
BH		 1966 for_each_compatible_node(np, NULL, "ibm,plb-pciex")
1967 ppc4xx_probe_pciex_bridge(np);
a2d2e1ec 1968#endif
5738ec6d
BH		 1969 for_each_compatible_node(np, NULL, "ibm,plb-pcix")
1970 ppc4xx_probe_pcix_bridge(np);
1971 for_each_compatible_node(np, NULL, "ibm,plb-pci")
1972 ppc4xx_probe_pci_bridge(np);
1973
1974 return 0;
1975}
1976arch_initcall(ppc4xx_pci_find_bridges);
1977
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