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5738ec6d BH |
1 | /* |
2 | * PCI / PCI-X / PCI-Express support for 4xx parts | |
3 | * | |
4 | * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp. | |
5 | * | |
a2d2e1ec BH |
6 | * Most PCI Express code is coming from Stefan Roese implementation for |
7 | * arch/ppc in the Denx tree, slightly reworked by me. | |
8 | * | |
9 | * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de> | |
10 | * | |
11 | * Some of that comes itself from a previous implementation for 440SPE only | |
12 | * by Roland Dreier: | |
13 | * | |
14 | * Copyright (c) 2005 Cisco Systems. All rights reserved. | |
15 | * Roland Dreier <rolandd@cisco.com> | |
16 | * | |
5738ec6d BH |
17 | */ |
18 | ||
035ee428 BH |
19 | #undef DEBUG |
20 | ||
5738ec6d BH |
21 | #include <linux/kernel.h> |
22 | #include <linux/pci.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/of.h> | |
a2d2e1ec BH |
25 | #include <linux/bootmem.h> |
26 | #include <linux/delay.h> | |
5a0e3ad6 | 27 | #include <linux/slab.h> |
5738ec6d BH |
28 | |
29 | #include <asm/io.h> | |
30 | #include <asm/pci-bridge.h> | |
31 | #include <asm/machdep.h> | |
a2d2e1ec BH |
32 | #include <asm/dcr.h> |
33 | #include <asm/dcr-regs.h> | |
cc2e113b | 34 | #include <mm/mmu_decl.h> |
5738ec6d BH |
35 | |
36 | #include "ppc4xx_pci.h" | |
37 | ||
38 | static int dma_offset_set; | |
39 | ||
a2d2e1ec BH |
40 | #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL)) |
41 | #define U64_TO_U32_HIGH(val) ((u32)((val) >> 32)) | |
42 | ||
8308c54d JF |
43 | #define RES_TO_U32_LOW(val) \ |
44 | ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val)) | |
45 | #define RES_TO_U32_HIGH(val) \ | |
46 | ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0)) | |
a2d2e1ec | 47 | |
accf5ef2 SR |
48 | static inline int ppc440spe_revA(void) |
49 | { | |
50 | /* Catch both 440SPe variants, with and without RAID6 support */ | |
51 | if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890) | |
52 | return 1; | |
53 | else | |
54 | return 0; | |
55 | } | |
56 | ||
c839e0ef BH |
57 | static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev) |
58 | { | |
59 | struct pci_controller *hose; | |
60 | int i; | |
61 | ||
62 | if (dev->devfn != 0 || dev->bus->self != NULL) | |
63 | return; | |
64 | ||
65 | hose = pci_bus_to_host(dev->bus); | |
66 | if (hose == NULL) | |
67 | return; | |
68 | ||
69 | if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") && | |
70 | !of_device_is_compatible(hose->dn, "ibm,plb-pcix") && | |
71 | !of_device_is_compatible(hose->dn, "ibm,plb-pci")) | |
72 | return; | |
73 | ||
5ce4b596 JB |
74 | if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") || |
75 | of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) { | |
76 | hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM; | |
77 | } | |
78 | ||
c839e0ef BH |
79 | /* Hide the PCI host BARs from the kernel as their content doesn't |
80 | * fit well in the resource management | |
81 | */ | |
82 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
83 | dev->resource[i].start = dev->resource[i].end = 0; | |
84 | dev->resource[i].flags = 0; | |
85 | } | |
86 | ||
87 | printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n", | |
88 | pci_name(dev)); | |
89 | } | |
90 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge); | |
91 | ||
5738ec6d BH |
92 | static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose, |
93 | void __iomem *reg, | |
94 | struct resource *res) | |
95 | { | |
96 | u64 size; | |
97 | const u32 *ranges; | |
98 | int rlen; | |
99 | int pna = of_n_addr_cells(hose->dn); | |
100 | int np = pna + 5; | |
101 | ||
102 | /* Default */ | |
103 | res->start = 0; | |
cc2e113b IY |
104 | size = 0x80000000; |
105 | res->end = size - 1; | |
5738ec6d BH |
106 | res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; |
107 | ||
108 | /* Get dma-ranges property */ | |
109 | ranges = of_get_property(hose->dn, "dma-ranges", &rlen); | |
110 | if (ranges == NULL) | |
111 | goto out; | |
112 | ||
113 | /* Walk it */ | |
114 | while ((rlen -= np * 4) >= 0) { | |
115 | u32 pci_space = ranges[0]; | |
116 | u64 pci_addr = of_read_number(ranges + 1, 2); | |
117 | u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3); | |
118 | size = of_read_number(ranges + pna + 3, 2); | |
119 | ranges += np; | |
120 | if (cpu_addr == OF_BAD_ADDR || size == 0) | |
121 | continue; | |
122 | ||
123 | /* We only care about memory */ | |
124 | if ((pci_space & 0x03000000) != 0x02000000) | |
125 | continue; | |
126 | ||
127 | /* We currently only support memory at 0, and pci_addr | |
128 | * within 32 bits space | |
129 | */ | |
130 | if (cpu_addr != 0 || pci_addr > 0xffffffff) { | |
131 | printk(KERN_WARNING "%s: Ignored unsupported dma range" | |
132 | " 0x%016llx...0x%016llx -> 0x%016llx\n", | |
133 | hose->dn->full_name, | |
134 | pci_addr, pci_addr + size - 1, cpu_addr); | |
135 | continue; | |
136 | } | |
137 | ||
138 | /* Check if not prefetchable */ | |
139 | if (!(pci_space & 0x40000000)) | |
140 | res->flags &= ~IORESOURCE_PREFETCH; | |
141 | ||
142 | ||
143 | /* Use that */ | |
144 | res->start = pci_addr; | |
5738ec6d | 145 | /* Beware of 32 bits resources */ |
8308c54d JF |
146 | if (sizeof(resource_size_t) == sizeof(u32) && |
147 | (pci_addr + size) > 0x100000000ull) | |
5738ec6d BH |
148 | res->end = 0xffffffff; |
149 | else | |
5738ec6d BH |
150 | res->end = res->start + size - 1; |
151 | break; | |
152 | } | |
153 | ||
154 | /* We only support one global DMA offset */ | |
155 | if (dma_offset_set && pci_dram_offset != res->start) { | |
156 | printk(KERN_ERR "%s: dma-ranges(s) mismatch\n", | |
157 | hose->dn->full_name); | |
158 | return -ENXIO; | |
159 | } | |
160 | ||
161 | /* Check that we can fit all of memory as we don't support | |
162 | * DMA bounce buffers | |
163 | */ | |
164 | if (size < total_memory) { | |
165 | printk(KERN_ERR "%s: dma-ranges too small " | |
cc2e113b IY |
166 | "(size=%llx total_memory=%llx)\n", |
167 | hose->dn->full_name, size, (u64)total_memory); | |
5738ec6d BH |
168 | return -ENXIO; |
169 | } | |
170 | ||
171 | /* Check we are a power of 2 size and that base is a multiple of size*/ | |
cc2e113b | 172 | if ((size & (size - 1)) != 0 || |
5738ec6d BH |
173 | (res->start & (size - 1)) != 0) { |
174 | printk(KERN_ERR "%s: dma-ranges unaligned\n", | |
175 | hose->dn->full_name); | |
176 | return -ENXIO; | |
177 | } | |
178 | ||
179 | /* Check that we are fully contained within 32 bits space */ | |
180 | if (res->end > 0xffffffff) { | |
181 | printk(KERN_ERR "%s: dma-ranges outside of 32 bits space\n", | |
182 | hose->dn->full_name); | |
183 | return -ENXIO; | |
184 | } | |
185 | out: | |
186 | dma_offset_set = 1; | |
187 | pci_dram_offset = res->start; | |
188 | ||
189 | printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n", | |
190 | pci_dram_offset); | |
191 | return 0; | |
192 | } | |
193 | ||
194 | /* | |
195 | * 4xx PCI 2.x part | |
196 | */ | |
c839e0ef | 197 | |
84d727a1 BH |
198 | static int __init ppc4xx_setup_one_pci_PMM(struct pci_controller *hose, |
199 | void __iomem *reg, | |
200 | u64 plb_addr, | |
201 | u64 pci_addr, | |
202 | u64 size, | |
203 | unsigned int flags, | |
204 | int index) | |
205 | { | |
206 | u32 ma, pcila, pciha; | |
207 | ||
1ac00cc2 BH |
208 | /* Hack warning ! The "old" PCI 2.x cell only let us configure the low |
209 | * 32-bit of incoming PLB addresses. The top 4 bits of the 36-bit | |
210 | * address are actually hard wired to a value that appears to depend | |
211 | * on the specific SoC. For example, it's 0 on 440EP and 1 on 440EPx. | |
212 | * | |
213 | * The trick here is we just crop those top bits and ignore them when | |
214 | * programming the chip. That means the device-tree has to be right | |
215 | * for the specific part used (we don't print a warning if it's wrong | |
216 | * but on the other hand, you'll crash quickly enough), but at least | |
217 | * this code should work whatever the hard coded value is | |
218 | */ | |
219 | plb_addr &= 0xffffffffull; | |
220 | ||
221 | /* Note: Due to the above hack, the test below doesn't actually test | |
222 | * if you address is above 4G, but it tests that address and | |
223 | * (address + size) are both contained in the same 4G | |
224 | */ | |
84d727a1 BH |
225 | if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) || |
226 | size < 0x1000 || (plb_addr & (size - 1)) != 0) { | |
227 | printk(KERN_WARNING "%s: Resource out of range\n", | |
228 | hose->dn->full_name); | |
229 | return -1; | |
230 | } | |
231 | ma = (0xffffffffu << ilog2(size)) | 1; | |
232 | if (flags & IORESOURCE_PREFETCH) | |
233 | ma |= 2; | |
234 | ||
235 | pciha = RES_TO_U32_HIGH(pci_addr); | |
236 | pcila = RES_TO_U32_LOW(pci_addr); | |
237 | ||
238 | writel(plb_addr, reg + PCIL0_PMM0LA + (0x10 * index)); | |
239 | writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * index)); | |
240 | writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * index)); | |
241 | writel(ma, reg + PCIL0_PMM0MA + (0x10 * index)); | |
242 | ||
243 | return 0; | |
244 | } | |
245 | ||
c839e0ef BH |
246 | static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose, |
247 | void __iomem *reg) | |
248 | { | |
84d727a1 | 249 | int i, j, found_isa_hole = 0; |
c839e0ef BH |
250 | |
251 | /* Setup outbound memory windows */ | |
252 | for (i = j = 0; i < 3; i++) { | |
253 | struct resource *res = &hose->mem_resources[i]; | |
254 | ||
255 | /* we only care about memory windows */ | |
256 | if (!(res->flags & IORESOURCE_MEM)) | |
257 | continue; | |
258 | if (j > 2) { | |
259 | printk(KERN_WARNING "%s: Too many ranges\n", | |
260 | hose->dn->full_name); | |
261 | break; | |
262 | } | |
263 | ||
84d727a1 BH |
264 | /* Configure the resource */ |
265 | if (ppc4xx_setup_one_pci_PMM(hose, reg, | |
266 | res->start, | |
267 | res->start - hose->pci_mem_offset, | |
268 | res->end + 1 - res->start, | |
269 | res->flags, | |
270 | j) == 0) { | |
271 | j++; | |
272 | ||
273 | /* If the resource PCI address is 0 then we have our | |
274 | * ISA memory hole | |
275 | */ | |
276 | if (res->start == hose->pci_mem_offset) | |
277 | found_isa_hole = 1; | |
c839e0ef | 278 | } |
c839e0ef | 279 | } |
84d727a1 BH |
280 | |
281 | /* Handle ISA memory hole if not already covered */ | |
282 | if (j <= 2 && !found_isa_hole && hose->isa_mem_size) | |
283 | if (ppc4xx_setup_one_pci_PMM(hose, reg, hose->isa_mem_phys, 0, | |
284 | hose->isa_mem_size, 0, j) == 0) | |
285 | printk(KERN_INFO "%s: Legacy ISA memory support enabled\n", | |
286 | hose->dn->full_name); | |
c839e0ef BH |
287 | } |
288 | ||
289 | static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose, | |
290 | void __iomem *reg, | |
291 | const struct resource *res) | |
292 | { | |
293 | resource_size_t size = res->end - res->start + 1; | |
294 | u32 sa; | |
295 | ||
296 | /* Calculate window size */ | |
297 | sa = (0xffffffffu << ilog2(size)) | 1; | |
298 | sa |= 0x1; | |
299 | ||
300 | /* RAM is always at 0 local for now */ | |
301 | writel(0, reg + PCIL0_PTM1LA); | |
302 | writel(sa, reg + PCIL0_PTM1MS); | |
303 | ||
304 | /* Map on PCI side */ | |
305 | early_write_config_dword(hose, hose->first_busno, 0, | |
306 | PCI_BASE_ADDRESS_1, res->start); | |
307 | early_write_config_dword(hose, hose->first_busno, 0, | |
308 | PCI_BASE_ADDRESS_2, 0x00000000); | |
309 | early_write_config_word(hose, hose->first_busno, 0, | |
310 | PCI_COMMAND, 0x0006); | |
311 | } | |
312 | ||
5738ec6d BH |
313 | static void __init ppc4xx_probe_pci_bridge(struct device_node *np) |
314 | { | |
315 | /* NYI */ | |
c839e0ef BH |
316 | struct resource rsrc_cfg; |
317 | struct resource rsrc_reg; | |
318 | struct resource dma_window; | |
319 | struct pci_controller *hose = NULL; | |
320 | void __iomem *reg = NULL; | |
321 | const int *bus_range; | |
322 | int primary = 0; | |
323 | ||
5a013fc7 MF |
324 | /* Check if device is enabled */ |
325 | if (!of_device_is_available(np)) { | |
326 | printk(KERN_INFO "%s: Port disabled via device-tree\n", | |
327 | np->full_name); | |
328 | return; | |
329 | } | |
330 | ||
c839e0ef BH |
331 | /* Fetch config space registers address */ |
332 | if (of_address_to_resource(np, 0, &rsrc_cfg)) { | |
5a013fc7 | 333 | printk(KERN_ERR "%s: Can't get PCI config register base !", |
c839e0ef BH |
334 | np->full_name); |
335 | return; | |
336 | } | |
337 | /* Fetch host bridge internal registers address */ | |
338 | if (of_address_to_resource(np, 3, &rsrc_reg)) { | |
339 | printk(KERN_ERR "%s: Can't get PCI internal register base !", | |
340 | np->full_name); | |
341 | return; | |
342 | } | |
343 | ||
344 | /* Check if primary bridge */ | |
345 | if (of_get_property(np, "primary", NULL)) | |
346 | primary = 1; | |
347 | ||
348 | /* Get bus range if any */ | |
349 | bus_range = of_get_property(np, "bus-range", NULL); | |
350 | ||
351 | /* Map registers */ | |
352 | reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start); | |
353 | if (reg == NULL) { | |
354 | printk(KERN_ERR "%s: Can't map registers !", np->full_name); | |
355 | goto fail; | |
356 | } | |
357 | ||
358 | /* Allocate the host controller data structure */ | |
359 | hose = pcibios_alloc_controller(np); | |
360 | if (!hose) | |
361 | goto fail; | |
362 | ||
363 | hose->first_busno = bus_range ? bus_range[0] : 0x0; | |
364 | hose->last_busno = bus_range ? bus_range[1] : 0xff; | |
365 | ||
366 | /* Setup config space */ | |
367 | setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0); | |
368 | ||
369 | /* Disable all windows */ | |
370 | writel(0, reg + PCIL0_PMM0MA); | |
371 | writel(0, reg + PCIL0_PMM1MA); | |
372 | writel(0, reg + PCIL0_PMM2MA); | |
373 | writel(0, reg + PCIL0_PTM1MS); | |
374 | writel(0, reg + PCIL0_PTM2MS); | |
375 | ||
376 | /* Parse outbound mapping resources */ | |
377 | pci_process_bridge_OF_ranges(hose, np, primary); | |
378 | ||
379 | /* Parse inbound mapping resources */ | |
380 | if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0) | |
381 | goto fail; | |
382 | ||
383 | /* Configure outbound ranges POMs */ | |
384 | ppc4xx_configure_pci_PMMs(hose, reg); | |
385 | ||
386 | /* Configure inbound ranges PIMs */ | |
387 | ppc4xx_configure_pci_PTMs(hose, reg, &dma_window); | |
388 | ||
389 | /* We don't need the registers anymore */ | |
390 | iounmap(reg); | |
391 | return; | |
392 | ||
393 | fail: | |
394 | if (hose) | |
395 | pcibios_free_controller(hose); | |
396 | if (reg) | |
397 | iounmap(reg); | |
5738ec6d BH |
398 | } |
399 | ||
400 | /* | |
401 | * 4xx PCI-X part | |
402 | */ | |
403 | ||
84d727a1 BH |
404 | static int __init ppc4xx_setup_one_pcix_POM(struct pci_controller *hose, |
405 | void __iomem *reg, | |
406 | u64 plb_addr, | |
407 | u64 pci_addr, | |
408 | u64 size, | |
409 | unsigned int flags, | |
410 | int index) | |
411 | { | |
412 | u32 lah, lal, pciah, pcial, sa; | |
413 | ||
414 | if (!is_power_of_2(size) || size < 0x1000 || | |
415 | (plb_addr & (size - 1)) != 0) { | |
416 | printk(KERN_WARNING "%s: Resource out of range\n", | |
417 | hose->dn->full_name); | |
418 | return -1; | |
419 | } | |
420 | ||
421 | /* Calculate register values */ | |
422 | lah = RES_TO_U32_HIGH(plb_addr); | |
423 | lal = RES_TO_U32_LOW(plb_addr); | |
424 | pciah = RES_TO_U32_HIGH(pci_addr); | |
425 | pcial = RES_TO_U32_LOW(pci_addr); | |
426 | sa = (0xffffffffu << ilog2(size)) | 0x1; | |
427 | ||
428 | /* Program register values */ | |
429 | if (index == 0) { | |
430 | writel(lah, reg + PCIX0_POM0LAH); | |
431 | writel(lal, reg + PCIX0_POM0LAL); | |
432 | writel(pciah, reg + PCIX0_POM0PCIAH); | |
433 | writel(pcial, reg + PCIX0_POM0PCIAL); | |
434 | writel(sa, reg + PCIX0_POM0SA); | |
435 | } else { | |
436 | writel(lah, reg + PCIX0_POM1LAH); | |
437 | writel(lal, reg + PCIX0_POM1LAL); | |
438 | writel(pciah, reg + PCIX0_POM1PCIAH); | |
439 | writel(pcial, reg + PCIX0_POM1PCIAL); | |
440 | writel(sa, reg + PCIX0_POM1SA); | |
441 | } | |
442 | ||
443 | return 0; | |
444 | } | |
445 | ||
5738ec6d BH |
446 | static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose, |
447 | void __iomem *reg) | |
448 | { | |
84d727a1 | 449 | int i, j, found_isa_hole = 0; |
5738ec6d BH |
450 | |
451 | /* Setup outbound memory windows */ | |
452 | for (i = j = 0; i < 3; i++) { | |
453 | struct resource *res = &hose->mem_resources[i]; | |
454 | ||
455 | /* we only care about memory windows */ | |
456 | if (!(res->flags & IORESOURCE_MEM)) | |
457 | continue; | |
458 | if (j > 1) { | |
459 | printk(KERN_WARNING "%s: Too many ranges\n", | |
460 | hose->dn->full_name); | |
461 | break; | |
462 | } | |
463 | ||
84d727a1 BH |
464 | /* Configure the resource */ |
465 | if (ppc4xx_setup_one_pcix_POM(hose, reg, | |
466 | res->start, | |
467 | res->start - hose->pci_mem_offset, | |
468 | res->end + 1 - res->start, | |
469 | res->flags, | |
470 | j) == 0) { | |
471 | j++; | |
472 | ||
473 | /* If the resource PCI address is 0 then we have our | |
474 | * ISA memory hole | |
475 | */ | |
476 | if (res->start == hose->pci_mem_offset) | |
477 | found_isa_hole = 1; | |
5738ec6d | 478 | } |
5738ec6d | 479 | } |
84d727a1 BH |
480 | |
481 | /* Handle ISA memory hole if not already covered */ | |
482 | if (j <= 1 && !found_isa_hole && hose->isa_mem_size) | |
483 | if (ppc4xx_setup_one_pcix_POM(hose, reg, hose->isa_mem_phys, 0, | |
484 | hose->isa_mem_size, 0, j) == 0) | |
485 | printk(KERN_INFO "%s: Legacy ISA memory support enabled\n", | |
486 | hose->dn->full_name); | |
5738ec6d BH |
487 | } |
488 | ||
489 | static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose, | |
490 | void __iomem *reg, | |
491 | const struct resource *res, | |
492 | int big_pim, | |
493 | int enable_msi_hole) | |
494 | { | |
495 | resource_size_t size = res->end - res->start + 1; | |
496 | u32 sa; | |
497 | ||
498 | /* RAM is always at 0 */ | |
499 | writel(0x00000000, reg + PCIX0_PIM0LAH); | |
500 | writel(0x00000000, reg + PCIX0_PIM0LAL); | |
501 | ||
502 | /* Calculate window size */ | |
503 | sa = (0xffffffffu << ilog2(size)) | 1; | |
504 | sa |= 0x1; | |
505 | if (res->flags & IORESOURCE_PREFETCH) | |
506 | sa |= 0x2; | |
507 | if (enable_msi_hole) | |
508 | sa |= 0x4; | |
509 | writel(sa, reg + PCIX0_PIM0SA); | |
510 | if (big_pim) | |
511 | writel(0xffffffff, reg + PCIX0_PIM0SAH); | |
512 | ||
513 | /* Map on PCI side */ | |
514 | writel(0x00000000, reg + PCIX0_BAR0H); | |
515 | writel(res->start, reg + PCIX0_BAR0L); | |
516 | writew(0x0006, reg + PCIX0_COMMAND); | |
517 | } | |
518 | ||
519 | static void __init ppc4xx_probe_pcix_bridge(struct device_node *np) | |
520 | { | |
521 | struct resource rsrc_cfg; | |
522 | struct resource rsrc_reg; | |
523 | struct resource dma_window; | |
524 | struct pci_controller *hose = NULL; | |
525 | void __iomem *reg = NULL; | |
526 | const int *bus_range; | |
527 | int big_pim = 0, msi = 0, primary = 0; | |
528 | ||
529 | /* Fetch config space registers address */ | |
530 | if (of_address_to_resource(np, 0, &rsrc_cfg)) { | |
531 | printk(KERN_ERR "%s:Can't get PCI-X config register base !", | |
532 | np->full_name); | |
533 | return; | |
534 | } | |
535 | /* Fetch host bridge internal registers address */ | |
536 | if (of_address_to_resource(np, 3, &rsrc_reg)) { | |
537 | printk(KERN_ERR "%s: Can't get PCI-X internal register base !", | |
538 | np->full_name); | |
539 | return; | |
540 | } | |
541 | ||
542 | /* Check if it supports large PIMs (440GX) */ | |
543 | if (of_get_property(np, "large-inbound-windows", NULL)) | |
544 | big_pim = 1; | |
545 | ||
546 | /* Check if we should enable MSIs inbound hole */ | |
547 | if (of_get_property(np, "enable-msi-hole", NULL)) | |
548 | msi = 1; | |
549 | ||
550 | /* Check if primary bridge */ | |
551 | if (of_get_property(np, "primary", NULL)) | |
552 | primary = 1; | |
553 | ||
554 | /* Get bus range if any */ | |
555 | bus_range = of_get_property(np, "bus-range", NULL); | |
556 | ||
557 | /* Map registers */ | |
558 | reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start); | |
559 | if (reg == NULL) { | |
560 | printk(KERN_ERR "%s: Can't map registers !", np->full_name); | |
561 | goto fail; | |
562 | } | |
563 | ||
564 | /* Allocate the host controller data structure */ | |
565 | hose = pcibios_alloc_controller(np); | |
566 | if (!hose) | |
567 | goto fail; | |
568 | ||
569 | hose->first_busno = bus_range ? bus_range[0] : 0x0; | |
570 | hose->last_busno = bus_range ? bus_range[1] : 0xff; | |
571 | ||
572 | /* Setup config space */ | |
d234b3c3 SO |
573 | setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, |
574 | PPC_INDIRECT_TYPE_SET_CFG_TYPE); | |
5738ec6d BH |
575 | |
576 | /* Disable all windows */ | |
577 | writel(0, reg + PCIX0_POM0SA); | |
578 | writel(0, reg + PCIX0_POM1SA); | |
579 | writel(0, reg + PCIX0_POM2SA); | |
580 | writel(0, reg + PCIX0_PIM0SA); | |
581 | writel(0, reg + PCIX0_PIM1SA); | |
582 | writel(0, reg + PCIX0_PIM2SA); | |
583 | if (big_pim) { | |
584 | writel(0, reg + PCIX0_PIM0SAH); | |
585 | writel(0, reg + PCIX0_PIM2SAH); | |
586 | } | |
587 | ||
588 | /* Parse outbound mapping resources */ | |
589 | pci_process_bridge_OF_ranges(hose, np, primary); | |
590 | ||
591 | /* Parse inbound mapping resources */ | |
592 | if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0) | |
593 | goto fail; | |
594 | ||
595 | /* Configure outbound ranges POMs */ | |
596 | ppc4xx_configure_pcix_POMs(hose, reg); | |
597 | ||
598 | /* Configure inbound ranges PIMs */ | |
599 | ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi); | |
600 | ||
601 | /* We don't need the registers anymore */ | |
602 | iounmap(reg); | |
603 | return; | |
604 | ||
605 | fail: | |
606 | if (hose) | |
607 | pcibios_free_controller(hose); | |
608 | if (reg) | |
609 | iounmap(reg); | |
610 | } | |
611 | ||
a2d2e1ec BH |
612 | #ifdef CONFIG_PPC4xx_PCI_EXPRESS |
613 | ||
5738ec6d BH |
614 | /* |
615 | * 4xx PCI-Express part | |
a2d2e1ec BH |
616 | * |
617 | * We support 3 parts currently based on the compatible property: | |
618 | * | |
accf5ef2 | 619 | * ibm,plb-pciex-440spe |
a2d2e1ec | 620 | * ibm,plb-pciex-405ex |
66b7e504 | 621 | * ibm,plb-pciex-460ex |
a2d2e1ec BH |
622 | * |
623 | * Anything else will be rejected for now as they are all subtly | |
624 | * different unfortunately. | |
625 | * | |
5738ec6d | 626 | */ |
a2d2e1ec | 627 | |
78994e24 | 628 | #define MAX_PCIE_BUS_MAPPED 0x40 |
a2d2e1ec BH |
629 | |
630 | struct ppc4xx_pciex_port | |
631 | { | |
632 | struct pci_controller *hose; | |
633 | struct device_node *node; | |
634 | unsigned int index; | |
635 | int endpoint; | |
035ee428 BH |
636 | int link; |
637 | int has_ibpre; | |
a2d2e1ec BH |
638 | unsigned int sdr_base; |
639 | dcr_host_t dcrs; | |
640 | struct resource cfg_space; | |
641 | struct resource utl_regs; | |
035ee428 | 642 | void __iomem *utl_base; |
a2d2e1ec BH |
643 | }; |
644 | ||
645 | static struct ppc4xx_pciex_port *ppc4xx_pciex_ports; | |
646 | static unsigned int ppc4xx_pciex_port_count; | |
647 | ||
648 | struct ppc4xx_pciex_hwops | |
649 | { | |
650 | int (*core_init)(struct device_node *np); | |
651 | int (*port_init_hw)(struct ppc4xx_pciex_port *port); | |
652 | int (*setup_utl)(struct ppc4xx_pciex_port *port); | |
653 | }; | |
654 | ||
655 | static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops; | |
656 | ||
657 | #ifdef CONFIG_44x | |
658 | ||
659 | /* Check various reset bits of the 440SPe PCIe core */ | |
660 | static int __init ppc440spe_pciex_check_reset(struct device_node *np) | |
661 | { | |
662 | u32 valPE0, valPE1, valPE2; | |
663 | int err = 0; | |
664 | ||
665 | /* SDR0_PEGPLLLCT1 reset */ | |
666 | if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) { | |
667 | /* | |
668 | * the PCIe core was probably already initialised | |
669 | * by firmware - let's re-reset RCSSET regs | |
670 | * | |
671 | * -- Shouldn't we also re-reset the whole thing ? -- BenH | |
672 | */ | |
673 | pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n"); | |
674 | mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000); | |
675 | mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000); | |
676 | mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000); | |
677 | } | |
678 | ||
679 | valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET); | |
680 | valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET); | |
681 | valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET); | |
682 | ||
683 | /* SDR0_PExRCSSET rstgu */ | |
684 | if (!(valPE0 & 0x01000000) || | |
685 | !(valPE1 & 0x01000000) || | |
686 | !(valPE2 & 0x01000000)) { | |
687 | printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n"); | |
688 | err = -1; | |
689 | } | |
690 | ||
691 | /* SDR0_PExRCSSET rstdl */ | |
692 | if (!(valPE0 & 0x00010000) || | |
693 | !(valPE1 & 0x00010000) || | |
694 | !(valPE2 & 0x00010000)) { | |
695 | printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n"); | |
696 | err = -1; | |
697 | } | |
698 | ||
699 | /* SDR0_PExRCSSET rstpyn */ | |
700 | if ((valPE0 & 0x00001000) || | |
701 | (valPE1 & 0x00001000) || | |
702 | (valPE2 & 0x00001000)) { | |
703 | printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n"); | |
704 | err = -1; | |
705 | } | |
706 | ||
707 | /* SDR0_PExRCSSET hldplb */ | |
708 | if ((valPE0 & 0x10000000) || | |
709 | (valPE1 & 0x10000000) || | |
710 | (valPE2 & 0x10000000)) { | |
711 | printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n"); | |
712 | err = -1; | |
713 | } | |
714 | ||
715 | /* SDR0_PExRCSSET rdy */ | |
716 | if ((valPE0 & 0x00100000) || | |
717 | (valPE1 & 0x00100000) || | |
718 | (valPE2 & 0x00100000)) { | |
719 | printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n"); | |
720 | err = -1; | |
721 | } | |
722 | ||
723 | /* SDR0_PExRCSSET shutdown */ | |
724 | if ((valPE0 & 0x00000100) || | |
725 | (valPE1 & 0x00000100) || | |
726 | (valPE2 & 0x00000100)) { | |
727 | printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n"); | |
728 | err = -1; | |
729 | } | |
730 | ||
731 | return err; | |
732 | } | |
733 | ||
734 | /* Global PCIe core initializations for 440SPe core */ | |
735 | static int __init ppc440spe_pciex_core_init(struct device_node *np) | |
736 | { | |
737 | int time_out = 20; | |
738 | ||
739 | /* Set PLL clock receiver to LVPECL */ | |
6e42b21b | 740 | dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28); |
a2d2e1ec BH |
741 | |
742 | /* Shouldn't we do all the calibration stuff etc... here ? */ | |
743 | if (ppc440spe_pciex_check_reset(np)) | |
744 | return -ENXIO; | |
745 | ||
746 | if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) { | |
747 | printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration " | |
748 | "failed (0x%08x)\n", | |
749 | mfdcri(SDR0, PESDR0_PLLLCT2)); | |
750 | return -1; | |
751 | } | |
752 | ||
753 | /* De-assert reset of PCIe PLL, wait for lock */ | |
6e42b21b | 754 | dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0); |
a2d2e1ec BH |
755 | udelay(3); |
756 | ||
757 | while (time_out) { | |
758 | if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) { | |
759 | time_out--; | |
760 | udelay(1); | |
761 | } else | |
762 | break; | |
763 | } | |
764 | if (!time_out) { | |
765 | printk(KERN_INFO "PCIE: VCO output not locked\n"); | |
766 | return -1; | |
767 | } | |
768 | ||
769 | pr_debug("PCIE initialization OK\n"); | |
770 | ||
771 | return 3; | |
772 | } | |
773 | ||
774 | static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port) | |
775 | { | |
776 | u32 val = 1 << 24; | |
777 | ||
778 | if (port->endpoint) | |
779 | val = PTYPE_LEGACY_ENDPOINT << 20; | |
780 | else | |
781 | val = PTYPE_ROOT_PORT << 20; | |
782 | ||
783 | if (port->index == 0) | |
784 | val |= LNKW_X8 << 12; | |
785 | else | |
786 | val |= LNKW_X4 << 12; | |
787 | ||
788 | mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); | |
789 | mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222); | |
accf5ef2 | 790 | if (ppc440spe_revA()) |
a2d2e1ec BH |
791 | mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000); |
792 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000); | |
793 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000); | |
794 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000); | |
795 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000); | |
796 | if (port->index == 0) { | |
797 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1, | |
798 | 0x35000000); | |
799 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1, | |
800 | 0x35000000); | |
801 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1, | |
802 | 0x35000000); | |
803 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1, | |
804 | 0x35000000); | |
805 | } | |
6e42b21b VB |
806 | dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, |
807 | (1 << 24) | (1 << 16), 1 << 12); | |
a2d2e1ec BH |
808 | |
809 | return 0; | |
810 | } | |
811 | ||
035ee428 BH |
812 | static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port) |
813 | { | |
814 | return ppc440spe_pciex_init_port_hw(port); | |
815 | } | |
816 | ||
817 | static int ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port) | |
a2d2e1ec | 818 | { |
035ee428 BH |
819 | int rc = ppc440spe_pciex_init_port_hw(port); |
820 | ||
821 | port->has_ibpre = 1; | |
822 | ||
823 | return rc; | |
824 | } | |
a2d2e1ec | 825 | |
035ee428 BH |
826 | static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port) |
827 | { | |
a2d2e1ec BH |
828 | /* XXX Check what that value means... I hate magic */ |
829 | dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800); | |
830 | ||
a2d2e1ec BH |
831 | /* |
832 | * Set buffer allocations and then assert VRB and TXE. | |
833 | */ | |
035ee428 BH |
834 | out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); |
835 | out_be32(port->utl_base + PEUTL_INTR, 0x02000000); | |
836 | out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000); | |
837 | out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000); | |
838 | out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000); | |
839 | out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000); | |
840 | out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000); | |
841 | out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); | |
a2d2e1ec | 842 | |
035ee428 BH |
843 | return 0; |
844 | } | |
845 | ||
846 | static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port) | |
847 | { | |
848 | /* Report CRS to the operating system */ | |
849 | out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000); | |
a2d2e1ec BH |
850 | |
851 | return 0; | |
852 | } | |
853 | ||
854 | static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata = | |
855 | { | |
856 | .core_init = ppc440spe_pciex_core_init, | |
035ee428 | 857 | .port_init_hw = ppc440speA_pciex_init_port_hw, |
a2d2e1ec BH |
858 | .setup_utl = ppc440speA_pciex_init_utl, |
859 | }; | |
860 | ||
861 | static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata = | |
862 | { | |
863 | .core_init = ppc440spe_pciex_core_init, | |
035ee428 BH |
864 | .port_init_hw = ppc440speB_pciex_init_port_hw, |
865 | .setup_utl = ppc440speB_pciex_init_utl, | |
a2d2e1ec BH |
866 | }; |
867 | ||
66b7e504 SR |
868 | static int __init ppc460ex_pciex_core_init(struct device_node *np) |
869 | { | |
870 | /* Nothing to do, return 2 ports */ | |
871 | return 2; | |
872 | } | |
873 | ||
874 | static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port) | |
875 | { | |
876 | u32 val; | |
877 | u32 utlset1; | |
878 | ||
5f91925c | 879 | if (port->endpoint) |
66b7e504 | 880 | val = PTYPE_LEGACY_ENDPOINT << 20; |
5f91925c | 881 | else |
66b7e504 | 882 | val = PTYPE_ROOT_PORT << 20; |
66b7e504 SR |
883 | |
884 | if (port->index == 0) { | |
885 | val |= LNKW_X1 << 12; | |
5f91925c | 886 | utlset1 = 0x20000000; |
66b7e504 SR |
887 | } else { |
888 | val |= LNKW_X4 << 12; | |
5f91925c | 889 | utlset1 = 0x20101101; |
66b7e504 SR |
890 | } |
891 | ||
892 | mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); | |
893 | mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1); | |
894 | mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000); | |
895 | ||
896 | switch (port->index) { | |
897 | case 0: | |
898 | mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230); | |
e30c9875 | 899 | mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130); |
66b7e504 SR |
900 | mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006); |
901 | ||
902 | mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000); | |
903 | break; | |
904 | ||
905 | case 1: | |
906 | mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230); | |
907 | mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230); | |
908 | mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230); | |
909 | mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230); | |
e30c9875 TM |
910 | mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130); |
911 | mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130); | |
912 | mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130); | |
913 | mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130); | |
66b7e504 SR |
914 | mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006); |
915 | mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006); | |
916 | mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006); | |
917 | mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006); | |
918 | ||
919 | mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000); | |
920 | break; | |
921 | } | |
922 | ||
923 | mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, | |
924 | mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | | |
925 | (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN)); | |
926 | ||
927 | /* Poll for PHY reset */ | |
928 | /* XXX FIXME add timeout */ | |
929 | switch (port->index) { | |
930 | case 0: | |
931 | while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1)) | |
932 | udelay(10); | |
933 | break; | |
934 | case 1: | |
935 | while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1)) | |
936 | udelay(10); | |
937 | break; | |
938 | } | |
939 | ||
940 | mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, | |
941 | (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) & | |
942 | ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) | | |
943 | PESDRx_RCSSET_RSTPYN); | |
944 | ||
945 | port->has_ibpre = 1; | |
946 | ||
947 | return 0; | |
948 | } | |
949 | ||
950 | static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port) | |
951 | { | |
952 | dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0); | |
953 | ||
954 | /* | |
955 | * Set buffer allocations and then assert VRB and TXE. | |
956 | */ | |
957 | out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c); | |
958 | out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); | |
959 | out_be32(port->utl_base + PEUTL_INTR, 0x02000000); | |
960 | out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000); | |
961 | out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000); | |
962 | out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000); | |
963 | out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000); | |
964 | out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000); | |
965 | out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); | |
966 | ||
967 | return 0; | |
968 | } | |
969 | ||
970 | static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata = | |
971 | { | |
972 | .core_init = ppc460ex_pciex_core_init, | |
973 | .port_init_hw = ppc460ex_pciex_init_port_hw, | |
974 | .setup_utl = ppc460ex_pciex_init_utl, | |
975 | }; | |
976 | ||
a2d2e1ec BH |
977 | #endif /* CONFIG_44x */ |
978 | ||
979 | #ifdef CONFIG_40x | |
980 | ||
981 | static int __init ppc405ex_pciex_core_init(struct device_node *np) | |
982 | { | |
983 | /* Nothing to do, return 2 ports */ | |
984 | return 2; | |
985 | } | |
986 | ||
987 | static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port) | |
988 | { | |
989 | /* Assert the PE0_PHY reset */ | |
990 | mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000); | |
991 | msleep(1); | |
992 | ||
993 | /* deassert the PE0_hotreset */ | |
994 | if (port->endpoint) | |
995 | mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000); | |
996 | else | |
997 | mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000); | |
998 | ||
999 | /* poll for phy !reset */ | |
1000 | /* XXX FIXME add timeout */ | |
1001 | while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000)) | |
1002 | ; | |
1003 | ||
1004 | /* deassert the PE0_gpl_utl_reset */ | |
1005 | mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000); | |
1006 | } | |
1007 | ||
1008 | static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port) | |
1009 | { | |
1010 | u32 val; | |
1011 | ||
1012 | if (port->endpoint) | |
1013 | val = PTYPE_LEGACY_ENDPOINT; | |
1014 | else | |
1015 | val = PTYPE_ROOT_PORT; | |
1016 | ||
1017 | mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, | |
1018 | 1 << 24 | val << 20 | LNKW_X1 << 12); | |
1019 | ||
1020 | mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000); | |
1021 | mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000); | |
1022 | mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000); | |
1023 | mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003); | |
1024 | ||
1025 | /* | |
1026 | * Only reset the PHY when no link is currently established. | |
1027 | * This is for the Atheros PCIe board which has problems to establish | |
1028 | * the link (again) after this PHY reset. All other currently tested | |
1029 | * PCIe boards don't show this problem. | |
1030 | * This has to be re-tested and fixed in a later release! | |
1031 | */ | |
a2d2e1ec BH |
1032 | val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); |
1033 | if (!(val & 0x00001000)) | |
1034 | ppc405ex_pcie_phy_reset(port); | |
a2d2e1ec BH |
1035 | |
1036 | dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */ | |
1037 | ||
55aaf6ec SR |
1038 | port->has_ibpre = 1; |
1039 | ||
a2d2e1ec BH |
1040 | return 0; |
1041 | } | |
1042 | ||
1043 | static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port) | |
1044 | { | |
a2d2e1ec BH |
1045 | dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0); |
1046 | ||
a2d2e1ec BH |
1047 | /* |
1048 | * Set buffer allocations and then assert VRB and TXE. | |
1049 | */ | |
035ee428 BH |
1050 | out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000); |
1051 | out_be32(port->utl_base + PEUTL_INTR, 0x02000000); | |
1052 | out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000); | |
1053 | out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000); | |
1054 | out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000); | |
1055 | out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000); | |
1056 | out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000); | |
1057 | out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); | |
a2d2e1ec | 1058 | |
035ee428 | 1059 | out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000); |
a2d2e1ec BH |
1060 | |
1061 | return 0; | |
1062 | } | |
1063 | ||
1064 | static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata = | |
1065 | { | |
1066 | .core_init = ppc405ex_pciex_core_init, | |
1067 | .port_init_hw = ppc405ex_pciex_init_port_hw, | |
1068 | .setup_utl = ppc405ex_pciex_init_utl, | |
1069 | }; | |
1070 | ||
1071 | #endif /* CONFIG_40x */ | |
1072 | ||
1073 | ||
1074 | /* Check that the core has been initied and if not, do it */ | |
1075 | static int __init ppc4xx_pciex_check_core_init(struct device_node *np) | |
1076 | { | |
1077 | static int core_init; | |
1078 | int count = -ENODEV; | |
1079 | ||
1080 | if (core_init++) | |
1081 | return 0; | |
1082 | ||
1083 | #ifdef CONFIG_44x | |
accf5ef2 SR |
1084 | if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) { |
1085 | if (ppc440spe_revA()) | |
1086 | ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops; | |
1087 | else | |
1088 | ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops; | |
1089 | } | |
66b7e504 SR |
1090 | if (of_device_is_compatible(np, "ibm,plb-pciex-460ex")) |
1091 | ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops; | |
a2d2e1ec BH |
1092 | #endif /* CONFIG_44x */ |
1093 | #ifdef CONFIG_40x | |
1094 | if (of_device_is_compatible(np, "ibm,plb-pciex-405ex")) | |
1095 | ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops; | |
1096 | #endif | |
1097 | if (ppc4xx_pciex_hwops == NULL) { | |
1098 | printk(KERN_WARNING "PCIE: unknown host type %s\n", | |
1099 | np->full_name); | |
1100 | return -ENODEV; | |
1101 | } | |
1102 | ||
1103 | count = ppc4xx_pciex_hwops->core_init(np); | |
1104 | if (count > 0) { | |
1105 | ppc4xx_pciex_ports = | |
1106 | kzalloc(count * sizeof(struct ppc4xx_pciex_port), | |
1107 | GFP_KERNEL); | |
1108 | if (ppc4xx_pciex_ports) { | |
1109 | ppc4xx_pciex_port_count = count; | |
1110 | return 0; | |
1111 | } | |
1112 | printk(KERN_WARNING "PCIE: failed to allocate ports array\n"); | |
1113 | return -ENOMEM; | |
1114 | } | |
1115 | return -ENODEV; | |
1116 | } | |
1117 | ||
1118 | static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port) | |
1119 | { | |
1120 | /* We map PCI Express configuration based on the reg property */ | |
1121 | dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH, | |
1122 | RES_TO_U32_HIGH(port->cfg_space.start)); | |
1123 | dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL, | |
1124 | RES_TO_U32_LOW(port->cfg_space.start)); | |
1125 | ||
1126 | /* XXX FIXME: Use size from reg property. For now, map 512M */ | |
1127 | dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001); | |
1128 | ||
1129 | /* We map UTL registers based on the reg property */ | |
1130 | dcr_write(port->dcrs, DCRO_PEGPL_REGBAH, | |
1131 | RES_TO_U32_HIGH(port->utl_regs.start)); | |
1132 | dcr_write(port->dcrs, DCRO_PEGPL_REGBAL, | |
1133 | RES_TO_U32_LOW(port->utl_regs.start)); | |
1134 | ||
1135 | /* XXX FIXME: Use size from reg property */ | |
1136 | dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001); | |
1137 | ||
1138 | /* Disable all other outbound windows */ | |
1139 | dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0); | |
1140 | dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0); | |
1141 | dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0); | |
1142 | dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0); | |
1143 | } | |
1144 | ||
035ee428 BH |
1145 | static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port, |
1146 | unsigned int sdr_offset, | |
1147 | unsigned int mask, | |
1148 | unsigned int value, | |
1149 | int timeout_ms) | |
a2d2e1ec | 1150 | { |
a2d2e1ec BH |
1151 | u32 val; |
1152 | ||
035ee428 BH |
1153 | while(timeout_ms--) { |
1154 | val = mfdcri(SDR0, port->sdr_base + sdr_offset); | |
1155 | if ((val & mask) == value) { | |
1156 | pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n", | |
1157 | port->index, sdr_offset, timeout_ms, val); | |
1158 | return 0; | |
1159 | } | |
1160 | msleep(1); | |
1161 | } | |
1162 | return -1; | |
1163 | } | |
1164 | ||
1165 | static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port) | |
1166 | { | |
1167 | int rc = 0; | |
a2d2e1ec BH |
1168 | |
1169 | /* Init HW */ | |
1170 | if (ppc4xx_pciex_hwops->port_init_hw) | |
1171 | rc = ppc4xx_pciex_hwops->port_init_hw(port); | |
1172 | if (rc != 0) | |
1173 | return rc; | |
1174 | ||
035ee428 | 1175 | printk(KERN_INFO "PCIE%d: Checking link...\n", |
a2d2e1ec | 1176 | port->index); |
a2d2e1ec | 1177 | |
035ee428 BH |
1178 | /* Wait for reset to complete */ |
1179 | if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) { | |
1180 | printk(KERN_WARNING "PCIE%d: PGRST failed\n", | |
1181 | port->index); | |
a2d2e1ec BH |
1182 | return -1; |
1183 | } | |
1184 | ||
035ee428 BH |
1185 | /* Check for card presence detect if supported, if not, just wait for |
1186 | * link unconditionally. | |
1187 | * | |
1188 | * note that we don't fail if there is no link, we just filter out | |
1189 | * config space accesses. That way, it will be easier to implement | |
1190 | * hotplug later on. | |
a2d2e1ec | 1191 | */ |
035ee428 BH |
1192 | if (!port->has_ibpre || |
1193 | !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP, | |
1194 | 1 << 28, 1 << 28, 100)) { | |
1195 | printk(KERN_INFO | |
1196 | "PCIE%d: Device detected, waiting for link...\n", | |
a2d2e1ec | 1197 | port->index); |
035ee428 BH |
1198 | if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP, |
1199 | 0x1000, 0x1000, 2000)) | |
1200 | printk(KERN_WARNING | |
1201 | "PCIE%d: Link up failed\n", port->index); | |
1202 | else { | |
1203 | printk(KERN_INFO | |
1204 | "PCIE%d: link is up !\n", port->index); | |
1205 | port->link = 1; | |
1206 | } | |
1207 | } else | |
1208 | printk(KERN_INFO "PCIE%d: No device detected.\n", port->index); | |
a2d2e1ec BH |
1209 | |
1210 | /* | |
1211 | * Initialize mapping: disable all regions and configure | |
1212 | * CFG and REG regions based on resources in the device tree | |
1213 | */ | |
1214 | ppc4xx_pciex_port_init_mapping(port); | |
1215 | ||
1216 | /* | |
035ee428 BH |
1217 | * Map UTL |
1218 | */ | |
1219 | port->utl_base = ioremap(port->utl_regs.start, 0x100); | |
1220 | BUG_ON(port->utl_base == NULL); | |
1221 | ||
1222 | /* | |
1223 | * Setup UTL registers --BenH. | |
a2d2e1ec BH |
1224 | */ |
1225 | if (ppc4xx_pciex_hwops->setup_utl) | |
1226 | ppc4xx_pciex_hwops->setup_utl(port); | |
1227 | ||
1228 | /* | |
1229 | * Check for VC0 active and assert RDY. | |
1230 | */ | |
035ee428 BH |
1231 | if (port->link && |
1232 | ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, | |
1233 | 1 << 16, 1 << 16, 5000)) { | |
1234 | printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index); | |
1235 | port->link = 0; | |
a2d2e1ec | 1236 | } |
035ee428 | 1237 | |
6e42b21b | 1238 | dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20); |
a2d2e1ec BH |
1239 | msleep(100); |
1240 | ||
1241 | return 0; | |
1242 | } | |
1243 | ||
1244 | static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port, | |
1245 | struct pci_bus *bus, | |
1246 | unsigned int devfn) | |
1247 | { | |
1248 | static int message; | |
1249 | ||
1250 | /* Endpoint can not generate upstream(remote) config cycles */ | |
1251 | if (port->endpoint && bus->number != port->hose->first_busno) | |
1252 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1253 | ||
1254 | /* Check we are within the mapped range */ | |
1255 | if (bus->number > port->hose->last_busno) { | |
1256 | if (!message) { | |
1257 | printk(KERN_WARNING "Warning! Probing bus %u" | |
1258 | " out of range !\n", bus->number); | |
1259 | message++; | |
1260 | } | |
1261 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1262 | } | |
1263 | ||
1264 | /* The root complex has only one device / function */ | |
1265 | if (bus->number == port->hose->first_busno && devfn != 0) | |
1266 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1267 | ||
1268 | /* The other side of the RC has only one device as well */ | |
1269 | if (bus->number == (port->hose->first_busno + 1) && | |
1270 | PCI_SLOT(devfn) != 0) | |
1271 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1272 | ||
035ee428 BH |
1273 | /* Check if we have a link */ |
1274 | if ((bus->number != port->hose->first_busno) && !port->link) | |
1275 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1276 | ||
a2d2e1ec BH |
1277 | return 0; |
1278 | } | |
1279 | ||
1280 | static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port, | |
1281 | struct pci_bus *bus, | |
1282 | unsigned int devfn) | |
1283 | { | |
1284 | int relbus; | |
1285 | ||
1286 | /* Remove the casts when we finally remove the stupid volatile | |
1287 | * in struct pci_controller | |
1288 | */ | |
1289 | if (bus->number == port->hose->first_busno) | |
1290 | return (void __iomem *)port->hose->cfg_addr; | |
1291 | ||
1292 | relbus = bus->number - (port->hose->first_busno + 1); | |
1293 | return (void __iomem *)port->hose->cfg_data + | |
1294 | ((relbus << 20) | (devfn << 12)); | |
1295 | } | |
1296 | ||
1297 | static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn, | |
1298 | int offset, int len, u32 *val) | |
1299 | { | |
f159edae | 1300 | struct pci_controller *hose = pci_bus_to_host(bus); |
a2d2e1ec BH |
1301 | struct ppc4xx_pciex_port *port = |
1302 | &ppc4xx_pciex_ports[hose->indirect_type]; | |
1303 | void __iomem *addr; | |
1304 | u32 gpl_cfg; | |
1305 | ||
1306 | BUG_ON(hose != port->hose); | |
1307 | ||
1308 | if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0) | |
1309 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1310 | ||
1311 | addr = ppc4xx_pciex_get_config_base(port, bus, devfn); | |
1312 | ||
1313 | /* | |
1314 | * Reading from configuration space of non-existing device can | |
1315 | * generate transaction errors. For the read duration we suppress | |
1316 | * assertion of machine check exceptions to avoid those. | |
1317 | */ | |
1318 | gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG); | |
1319 | dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA); | |
1320 | ||
035ee428 BH |
1321 | /* Make sure no CRS is recorded */ |
1322 | out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000); | |
1323 | ||
a2d2e1ec BH |
1324 | switch (len) { |
1325 | case 1: | |
1326 | *val = in_8((u8 *)(addr + offset)); | |
1327 | break; | |
1328 | case 2: | |
1329 | *val = in_le16((u16 *)(addr + offset)); | |
1330 | break; | |
1331 | default: | |
1332 | *val = in_le32((u32 *)(addr + offset)); | |
1333 | break; | |
1334 | } | |
1335 | ||
1336 | pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x" | |
1337 | " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n", | |
1338 | bus->number, hose->first_busno, hose->last_busno, | |
1339 | devfn, offset, len, addr + offset, *val); | |
1340 | ||
035ee428 BH |
1341 | /* Check for CRS (440SPe rev B does that for us but heh ..) */ |
1342 | if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) { | |
1343 | pr_debug("Got CRS !\n"); | |
1344 | if (len != 4 || offset != 0) | |
1345 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1346 | *val = 0xffff0001; | |
1347 | } | |
1348 | ||
a2d2e1ec BH |
1349 | dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg); |
1350 | ||
1351 | return PCIBIOS_SUCCESSFUL; | |
1352 | } | |
1353 | ||
1354 | static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn, | |
1355 | int offset, int len, u32 val) | |
1356 | { | |
f159edae | 1357 | struct pci_controller *hose = pci_bus_to_host(bus); |
a2d2e1ec BH |
1358 | struct ppc4xx_pciex_port *port = |
1359 | &ppc4xx_pciex_ports[hose->indirect_type]; | |
1360 | void __iomem *addr; | |
1361 | u32 gpl_cfg; | |
1362 | ||
1363 | if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0) | |
1364 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1365 | ||
1366 | addr = ppc4xx_pciex_get_config_base(port, bus, devfn); | |
1367 | ||
1368 | /* | |
1369 | * Reading from configuration space of non-existing device can | |
1370 | * generate transaction errors. For the read duration we suppress | |
1371 | * assertion of machine check exceptions to avoid those. | |
1372 | */ | |
1373 | gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG); | |
1374 | dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA); | |
1375 | ||
1376 | pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x" | |
1377 | " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n", | |
1378 | bus->number, hose->first_busno, hose->last_busno, | |
1379 | devfn, offset, len, addr + offset, val); | |
1380 | ||
1381 | switch (len) { | |
1382 | case 1: | |
1383 | out_8((u8 *)(addr + offset), val); | |
1384 | break; | |
1385 | case 2: | |
1386 | out_le16((u16 *)(addr + offset), val); | |
1387 | break; | |
1388 | default: | |
1389 | out_le32((u32 *)(addr + offset), val); | |
1390 | break; | |
1391 | } | |
1392 | ||
1393 | dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg); | |
1394 | ||
1395 | return PCIBIOS_SUCCESSFUL; | |
1396 | } | |
1397 | ||
1398 | static struct pci_ops ppc4xx_pciex_pci_ops = | |
1399 | { | |
1400 | .read = ppc4xx_pciex_read_config, | |
1401 | .write = ppc4xx_pciex_write_config, | |
1402 | }; | |
1403 | ||
84d727a1 BH |
1404 | static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port *port, |
1405 | struct pci_controller *hose, | |
1406 | void __iomem *mbase, | |
1407 | u64 plb_addr, | |
1408 | u64 pci_addr, | |
1409 | u64 size, | |
1410 | unsigned int flags, | |
1411 | int index) | |
1412 | { | |
1413 | u32 lah, lal, pciah, pcial, sa; | |
1414 | ||
1415 | if (!is_power_of_2(size) || | |
1416 | (index < 2 && size < 0x100000) || | |
1417 | (index == 2 && size < 0x100) || | |
1418 | (plb_addr & (size - 1)) != 0) { | |
1419 | printk(KERN_WARNING "%s: Resource out of range\n", | |
1420 | hose->dn->full_name); | |
1421 | return -1; | |
1422 | } | |
1423 | ||
1424 | /* Calculate register values */ | |
1425 | lah = RES_TO_U32_HIGH(plb_addr); | |
1426 | lal = RES_TO_U32_LOW(plb_addr); | |
1427 | pciah = RES_TO_U32_HIGH(pci_addr); | |
1428 | pcial = RES_TO_U32_LOW(pci_addr); | |
1429 | sa = (0xffffffffu << ilog2(size)) | 0x1; | |
1430 | ||
1431 | /* Program register values */ | |
1432 | switch (index) { | |
1433 | case 0: | |
1434 | out_le32(mbase + PECFG_POM0LAH, pciah); | |
1435 | out_le32(mbase + PECFG_POM0LAL, pcial); | |
1436 | dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah); | |
1437 | dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal); | |
1438 | dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff); | |
1439 | /* Note that 3 here means enabled | single region */ | |
1440 | dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, sa | 3); | |
1441 | break; | |
1442 | case 1: | |
1443 | out_le32(mbase + PECFG_POM1LAH, pciah); | |
1444 | out_le32(mbase + PECFG_POM1LAL, pcial); | |
1445 | dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah); | |
1446 | dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal); | |
1447 | dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff); | |
1448 | /* Note that 3 here means enabled | single region */ | |
1449 | dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, sa | 3); | |
1450 | break; | |
1451 | case 2: | |
1452 | out_le32(mbase + PECFG_POM2LAH, pciah); | |
1453 | out_le32(mbase + PECFG_POM2LAL, pcial); | |
1454 | dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah); | |
1455 | dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal); | |
1456 | dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff); | |
1457 | /* Note that 3 here means enabled | IO space !!! */ | |
1458 | dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, sa | 3); | |
1459 | break; | |
1460 | } | |
1461 | ||
1462 | return 0; | |
1463 | } | |
1464 | ||
a2d2e1ec BH |
1465 | static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port, |
1466 | struct pci_controller *hose, | |
1467 | void __iomem *mbase) | |
1468 | { | |
84d727a1 | 1469 | int i, j, found_isa_hole = 0; |
a2d2e1ec BH |
1470 | |
1471 | /* Setup outbound memory windows */ | |
1472 | for (i = j = 0; i < 3; i++) { | |
1473 | struct resource *res = &hose->mem_resources[i]; | |
1474 | ||
1475 | /* we only care about memory windows */ | |
1476 | if (!(res->flags & IORESOURCE_MEM)) | |
1477 | continue; | |
1478 | if (j > 1) { | |
1479 | printk(KERN_WARNING "%s: Too many ranges\n", | |
1480 | port->node->full_name); | |
1481 | break; | |
1482 | } | |
1483 | ||
84d727a1 BH |
1484 | /* Configure the resource */ |
1485 | if (ppc4xx_setup_one_pciex_POM(port, hose, mbase, | |
1486 | res->start, | |
1487 | res->start - hose->pci_mem_offset, | |
1488 | res->end + 1 - res->start, | |
1489 | res->flags, | |
1490 | j) == 0) { | |
1491 | j++; | |
1492 | ||
1493 | /* If the resource PCI address is 0 then we have our | |
1494 | * ISA memory hole | |
1495 | */ | |
1496 | if (res->start == hose->pci_mem_offset) | |
1497 | found_isa_hole = 1; | |
a2d2e1ec | 1498 | } |
a2d2e1ec BH |
1499 | } |
1500 | ||
84d727a1 BH |
1501 | /* Handle ISA memory hole if not already covered */ |
1502 | if (j <= 1 && !found_isa_hole && hose->isa_mem_size) | |
1503 | if (ppc4xx_setup_one_pciex_POM(port, hose, mbase, | |
1504 | hose->isa_mem_phys, 0, | |
1505 | hose->isa_mem_size, 0, j) == 0) | |
1506 | printk(KERN_INFO "%s: Legacy ISA memory support enabled\n", | |
1507 | hose->dn->full_name); | |
1508 | ||
1509 | /* Configure IO, always 64K starting at 0. We hard wire it to 64K ! | |
1510 | * Note also that it -has- to be region index 2 on this HW | |
1511 | */ | |
1512 | if (hose->io_resource.flags & IORESOURCE_IO) | |
1513 | ppc4xx_setup_one_pciex_POM(port, hose, mbase, | |
1514 | hose->io_base_phys, 0, | |
1515 | 0x10000, IORESOURCE_IO, 2); | |
a2d2e1ec BH |
1516 | } |
1517 | ||
1518 | static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port, | |
1519 | struct pci_controller *hose, | |
1520 | void __iomem *mbase, | |
1521 | struct resource *res) | |
1522 | { | |
1523 | resource_size_t size = res->end - res->start + 1; | |
1524 | u64 sa; | |
1525 | ||
80daac3f SR |
1526 | if (port->endpoint) { |
1527 | resource_size_t ep_addr = 0; | |
1528 | resource_size_t ep_size = 32 << 20; | |
1529 | ||
1530 | /* Currently we map a fixed 64MByte window to PLB address | |
1531 | * 0 (SDRAM). This should probably be configurable via a dts | |
1532 | * property. | |
1533 | */ | |
1534 | ||
1535 | /* Calculate window size */ | |
d258e64e | 1536 | sa = (0xffffffffffffffffull << ilog2(ep_size)); |
80daac3f SR |
1537 | |
1538 | /* Setup BAR0 */ | |
1539 | out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa)); | |
1540 | out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) | | |
1541 | PCI_BASE_ADDRESS_MEM_TYPE_64); | |
a2d2e1ec | 1542 | |
80daac3f SR |
1543 | /* Disable BAR1 & BAR2 */ |
1544 | out_le32(mbase + PECFG_BAR1MPA, 0); | |
1545 | out_le32(mbase + PECFG_BAR2HMPA, 0); | |
1546 | out_le32(mbase + PECFG_BAR2LMPA, 0); | |
a2d2e1ec | 1547 | |
80daac3f SR |
1548 | out_le32(mbase + PECFG_PIM01SAH, RES_TO_U32_HIGH(sa)); |
1549 | out_le32(mbase + PECFG_PIM01SAL, RES_TO_U32_LOW(sa)); | |
1550 | ||
1551 | out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr)); | |
1552 | out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(ep_addr)); | |
1553 | } else { | |
1554 | /* Calculate window size */ | |
d258e64e | 1555 | sa = (0xffffffffffffffffull << ilog2(size)); |
80daac3f SR |
1556 | if (res->flags & IORESOURCE_PREFETCH) |
1557 | sa |= 0x8; | |
1558 | ||
1559 | out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa)); | |
1560 | out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa)); | |
1561 | ||
1562 | /* The setup of the split looks weird to me ... let's see | |
1563 | * if it works | |
1564 | */ | |
1565 | out_le32(mbase + PECFG_PIM0LAL, 0x00000000); | |
1566 | out_le32(mbase + PECFG_PIM0LAH, 0x00000000); | |
1567 | out_le32(mbase + PECFG_PIM1LAL, 0x00000000); | |
1568 | out_le32(mbase + PECFG_PIM1LAH, 0x00000000); | |
1569 | out_le32(mbase + PECFG_PIM01SAH, 0xffff0000); | |
1570 | out_le32(mbase + PECFG_PIM01SAL, 0x00000000); | |
1571 | ||
1572 | out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start)); | |
1573 | out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start)); | |
1574 | } | |
a2d2e1ec BH |
1575 | |
1576 | /* Enable inbound mapping */ | |
1577 | out_le32(mbase + PECFG_PIMEN, 0x1); | |
1578 | ||
a2d2e1ec BH |
1579 | /* Enable I/O, Mem, and Busmaster cycles */ |
1580 | out_le16(mbase + PCI_COMMAND, | |
1581 | in_le16(mbase + PCI_COMMAND) | | |
1582 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
1583 | } | |
1584 | ||
1585 | static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port) | |
1586 | { | |
1587 | struct resource dma_window; | |
1588 | struct pci_controller *hose = NULL; | |
1589 | const int *bus_range; | |
1590 | int primary = 0, busses; | |
1591 | void __iomem *mbase = NULL, *cfg_data = NULL; | |
80daac3f SR |
1592 | const u32 *pval; |
1593 | u32 val; | |
a2d2e1ec BH |
1594 | |
1595 | /* Check if primary bridge */ | |
1596 | if (of_get_property(port->node, "primary", NULL)) | |
1597 | primary = 1; | |
1598 | ||
1599 | /* Get bus range if any */ | |
1600 | bus_range = of_get_property(port->node, "bus-range", NULL); | |
1601 | ||
1602 | /* Allocate the host controller data structure */ | |
1603 | hose = pcibios_alloc_controller(port->node); | |
1604 | if (!hose) | |
1605 | goto fail; | |
1606 | ||
1607 | /* We stick the port number in "indirect_type" so the config space | |
1608 | * ops can retrieve the port data structure easily | |
1609 | */ | |
1610 | hose->indirect_type = port->index; | |
1611 | ||
1612 | /* Get bus range */ | |
1613 | hose->first_busno = bus_range ? bus_range[0] : 0x0; | |
1614 | hose->last_busno = bus_range ? bus_range[1] : 0xff; | |
1615 | ||
1616 | /* Because of how big mapping the config space is (1M per bus), we | |
1617 | * limit how many busses we support. In the long run, we could replace | |
1618 | * that with something akin to kmap_atomic instead. We set aside 1 bus | |
1619 | * for the host itself too. | |
1620 | */ | |
1621 | busses = hose->last_busno - hose->first_busno; /* This is off by 1 */ | |
1622 | if (busses > MAX_PCIE_BUS_MAPPED) { | |
1623 | busses = MAX_PCIE_BUS_MAPPED; | |
1624 | hose->last_busno = hose->first_busno + busses; | |
1625 | } | |
1626 | ||
80daac3f SR |
1627 | if (!port->endpoint) { |
1628 | /* Only map the external config space in cfg_data for | |
1629 | * PCIe root-complexes. External space is 1M per bus | |
1630 | */ | |
1631 | cfg_data = ioremap(port->cfg_space.start + | |
1632 | (hose->first_busno + 1) * 0x100000, | |
1633 | busses * 0x100000); | |
1634 | if (cfg_data == NULL) { | |
1635 | printk(KERN_ERR "%s: Can't map external config space !", | |
1636 | port->node->full_name); | |
1637 | goto fail; | |
1638 | } | |
1639 | hose->cfg_data = cfg_data; | |
1640 | } | |
1641 | ||
1642 | /* Always map the host config space in cfg_addr. | |
1643 | * Internal space is 4K | |
a2d2e1ec | 1644 | */ |
a2d2e1ec | 1645 | mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000); |
80daac3f SR |
1646 | if (mbase == NULL) { |
1647 | printk(KERN_ERR "%s: Can't map internal config space !", | |
a2d2e1ec BH |
1648 | port->node->full_name); |
1649 | goto fail; | |
1650 | } | |
a2d2e1ec BH |
1651 | hose->cfg_addr = mbase; |
1652 | ||
1653 | pr_debug("PCIE %s, bus %d..%d\n", port->node->full_name, | |
1654 | hose->first_busno, hose->last_busno); | |
1655 | pr_debug(" config space mapped at: root @0x%p, other @0x%p\n", | |
1656 | hose->cfg_addr, hose->cfg_data); | |
1657 | ||
1658 | /* Setup config space */ | |
1659 | hose->ops = &ppc4xx_pciex_pci_ops; | |
1660 | port->hose = hose; | |
1661 | mbase = (void __iomem *)hose->cfg_addr; | |
1662 | ||
80daac3f SR |
1663 | if (!port->endpoint) { |
1664 | /* | |
1665 | * Set bus numbers on our root port | |
1666 | */ | |
1667 | out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno); | |
1668 | out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1); | |
1669 | out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno); | |
1670 | } | |
a2d2e1ec BH |
1671 | |
1672 | /* | |
1673 | * OMRs are already reset, also disable PIMs | |
1674 | */ | |
1675 | out_le32(mbase + PECFG_PIMEN, 0); | |
1676 | ||
1677 | /* Parse outbound mapping resources */ | |
1678 | pci_process_bridge_OF_ranges(hose, port->node, primary); | |
1679 | ||
1680 | /* Parse inbound mapping resources */ | |
1681 | if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0) | |
1682 | goto fail; | |
1683 | ||
1684 | /* Configure outbound ranges POMs */ | |
1685 | ppc4xx_configure_pciex_POMs(port, hose, mbase); | |
1686 | ||
1687 | /* Configure inbound ranges PIMs */ | |
1688 | ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window); | |
1689 | ||
1690 | /* The root complex doesn't show up if we don't set some vendor | |
80daac3f SR |
1691 | * and device IDs into it. The defaults below are the same bogus |
1692 | * one that the initial code in arch/ppc had. This can be | |
1693 | * overwritten by setting the "vendor-id/device-id" properties | |
1694 | * in the pciex node. | |
a2d2e1ec | 1695 | */ |
a2d2e1ec | 1696 | |
80daac3f SR |
1697 | /* Get the (optional) vendor-/device-id from the device-tree */ |
1698 | pval = of_get_property(port->node, "vendor-id", NULL); | |
1699 | if (pval) { | |
1700 | val = *pval; | |
1701 | } else { | |
1702 | if (!port->endpoint) | |
1703 | val = 0xaaa0 + port->index; | |
1704 | else | |
1705 | val = 0xeee0 + port->index; | |
1706 | } | |
1707 | out_le16(mbase + 0x200, val); | |
1708 | ||
1709 | pval = of_get_property(port->node, "device-id", NULL); | |
1710 | if (pval) { | |
1711 | val = *pval; | |
1712 | } else { | |
1713 | if (!port->endpoint) | |
1714 | val = 0xbed0 + port->index; | |
1715 | else | |
1716 | val = 0xfed0 + port->index; | |
1717 | } | |
1718 | out_le16(mbase + 0x202, val); | |
1719 | ||
1720 | if (!port->endpoint) { | |
1721 | /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ | |
1722 | out_le32(mbase + 0x208, 0x06040001); | |
1723 | ||
1724 | printk(KERN_INFO "PCIE%d: successfully set as root-complex\n", | |
1725 | port->index); | |
1726 | } else { | |
1727 | /* Set Class Code to Processor/PPC */ | |
1728 | out_le32(mbase + 0x208, 0x0b200001); | |
1729 | ||
1730 | printk(KERN_INFO "PCIE%d: successfully set as endpoint\n", | |
1731 | port->index); | |
1732 | } | |
a2d2e1ec | 1733 | |
a2d2e1ec BH |
1734 | return; |
1735 | fail: | |
1736 | if (hose) | |
1737 | pcibios_free_controller(hose); | |
1738 | if (cfg_data) | |
1739 | iounmap(cfg_data); | |
1740 | if (mbase) | |
1741 | iounmap(mbase); | |
1742 | } | |
1743 | ||
5738ec6d BH |
1744 | static void __init ppc4xx_probe_pciex_bridge(struct device_node *np) |
1745 | { | |
a2d2e1ec BH |
1746 | struct ppc4xx_pciex_port *port; |
1747 | const u32 *pval; | |
1748 | int portno; | |
1749 | unsigned int dcrs; | |
80daac3f | 1750 | const char *val; |
a2d2e1ec BH |
1751 | |
1752 | /* First, proceed to core initialization as we assume there's | |
1753 | * only one PCIe core in the system | |
1754 | */ | |
1755 | if (ppc4xx_pciex_check_core_init(np)) | |
1756 | return; | |
1757 | ||
1758 | /* Get the port number from the device-tree */ | |
1759 | pval = of_get_property(np, "port", NULL); | |
1760 | if (pval == NULL) { | |
1761 | printk(KERN_ERR "PCIE: Can't find port number for %s\n", | |
1762 | np->full_name); | |
1763 | return; | |
1764 | } | |
1765 | portno = *pval; | |
1766 | if (portno >= ppc4xx_pciex_port_count) { | |
1767 | printk(KERN_ERR "PCIE: port number out of range for %s\n", | |
1768 | np->full_name); | |
1769 | return; | |
1770 | } | |
1771 | port = &ppc4xx_pciex_ports[portno]; | |
1772 | port->index = portno; | |
995ada8d SR |
1773 | |
1774 | /* | |
1775 | * Check if device is enabled | |
1776 | */ | |
1777 | if (!of_device_is_available(np)) { | |
1778 | printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index); | |
1779 | return; | |
1780 | } | |
1781 | ||
a2d2e1ec BH |
1782 | port->node = of_node_get(np); |
1783 | pval = of_get_property(np, "sdr-base", NULL); | |
1784 | if (pval == NULL) { | |
1785 | printk(KERN_ERR "PCIE: missing sdr-base for %s\n", | |
1786 | np->full_name); | |
1787 | return; | |
1788 | } | |
1789 | port->sdr_base = *pval; | |
1790 | ||
80daac3f SR |
1791 | /* Check if device_type property is set to "pci" or "pci-endpoint". |
1792 | * Resulting from this setup this PCIe port will be configured | |
1793 | * as root-complex or as endpoint. | |
1794 | */ | |
1795 | val = of_get_property(port->node, "device_type", NULL); | |
1796 | if (!strcmp(val, "pci-endpoint")) { | |
1797 | port->endpoint = 1; | |
1798 | } else if (!strcmp(val, "pci")) { | |
1799 | port->endpoint = 0; | |
1800 | } else { | |
1801 | printk(KERN_ERR "PCIE: missing or incorrect device_type for %s\n", | |
1802 | np->full_name); | |
1803 | return; | |
1804 | } | |
035ee428 | 1805 | |
a2d2e1ec BH |
1806 | /* Fetch config space registers address */ |
1807 | if (of_address_to_resource(np, 0, &port->cfg_space)) { | |
1808 | printk(KERN_ERR "%s: Can't get PCI-E config space !", | |
1809 | np->full_name); | |
1810 | return; | |
1811 | } | |
1812 | /* Fetch host bridge internal registers address */ | |
1813 | if (of_address_to_resource(np, 1, &port->utl_regs)) { | |
1814 | printk(KERN_ERR "%s: Can't get UTL register base !", | |
1815 | np->full_name); | |
1816 | return; | |
1817 | } | |
1818 | ||
1819 | /* Map DCRs */ | |
1820 | dcrs = dcr_resource_start(np, 0); | |
1821 | if (dcrs == 0) { | |
1822 | printk(KERN_ERR "%s: Can't get DCR register base !", | |
1823 | np->full_name); | |
1824 | return; | |
1825 | } | |
1826 | port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0)); | |
1827 | ||
1828 | /* Initialize the port specific registers */ | |
035ee428 BH |
1829 | if (ppc4xx_pciex_port_init(port)) { |
1830 | printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index); | |
a2d2e1ec | 1831 | return; |
035ee428 | 1832 | } |
a2d2e1ec BH |
1833 | |
1834 | /* Setup the linux hose data structure */ | |
1835 | ppc4xx_pciex_port_setup_hose(port); | |
5738ec6d BH |
1836 | } |
1837 | ||
a2d2e1ec BH |
1838 | #endif /* CONFIG_PPC4xx_PCI_EXPRESS */ |
1839 | ||
5738ec6d BH |
1840 | static int __init ppc4xx_pci_find_bridges(void) |
1841 | { | |
1842 | struct device_node *np; | |
1843 | ||
41b6a085 BH |
1844 | ppc_pci_flags |= PPC_PCI_ENABLE_PROC_DOMAINS | PPC_PCI_COMPAT_DOMAIN_0; |
1845 | ||
a2d2e1ec | 1846 | #ifdef CONFIG_PPC4xx_PCI_EXPRESS |
5738ec6d BH |
1847 | for_each_compatible_node(np, NULL, "ibm,plb-pciex") |
1848 | ppc4xx_probe_pciex_bridge(np); | |
a2d2e1ec | 1849 | #endif |
5738ec6d BH |
1850 | for_each_compatible_node(np, NULL, "ibm,plb-pcix") |
1851 | ppc4xx_probe_pcix_bridge(np); | |
1852 | for_each_compatible_node(np, NULL, "ibm,plb-pci") | |
1853 | ppc4xx_probe_pci_bridge(np); | |
1854 | ||
1855 | return 0; | |
1856 | } | |
1857 | arch_initcall(ppc4xx_pci_find_bridges); | |
1858 |