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powerpc/4xx: Fix resource issue in warp-nand.c
[net-next-2.6.git] / arch / powerpc / sysdev / ppc4xx_pci.c
CommitLineData
5738ec6d
BH		 1/*
2 * PCI / PCI-X / PCI-Express support for 4xx parts
3 *
4 * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
5 *
a2d2e1ec
BH		 6 * Most PCI Express code is coming from Stefan Roese implementation for
7 * arch/ppc in the Denx tree, slightly reworked by me.
8 *
9 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
10 *
11 * Some of that comes itself from a previous implementation for 440SPE only
12 * by Roland Dreier:
13 *
14 * Copyright (c) 2005 Cisco Systems. All rights reserved.
15 * Roland Dreier <rolandd@cisco.com>
16 *
5738ec6d
BH		 17 */
18
035ee428
BH		 19#undef DEBUG
20
5738ec6d
BH		 21#include <linux/kernel.h>
22#include <linux/pci.h>
23#include <linux/init.h>
24#include <linux/of.h>
a2d2e1ec
BH		 25#include <linux/bootmem.h>
26#include <linux/delay.h>
5738ec6d
BH		 27
28#include <asm/io.h>
29#include <asm/pci-bridge.h>
30#include <asm/machdep.h>
a2d2e1ec
BH		 31#include <asm/dcr.h>
32#include <asm/dcr-regs.h>
5738ec6d
BH		 33
34#include "ppc4xx_pci.h"
35
36static int dma_offset_set;
37
38/* Move that to a useable header */
39extern unsigned long total_memory;
40
a2d2e1ec
BH		 41#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
42#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
43
44#ifdef CONFIG_RESOURCES_64BIT
45#define RES_TO_U32_LOW(val) U64_TO_U32_LOW(val)
46#define RES_TO_U32_HIGH(val) U64_TO_U32_HIGH(val)
47#else
48#define RES_TO_U32_LOW(val) (val)
49#define RES_TO_U32_HIGH(val) (0)
50#endif
51
accf5ef2
SR		 52static inline int ppc440spe_revA(void)
53{
54 /* Catch both 440SPe variants, with and without RAID6 support */
55 if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890)
56 return 1;
57 else
58 return 0;
59}
60
c839e0ef
BH		 61static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev)
62{
63 struct pci_controller *hose;
64 int i;
65
66 if (dev->devfn != 0 || dev->bus->self != NULL)
67 return;
68
69 hose = pci_bus_to_host(dev->bus);
70 if (hose == NULL)
71 return;
72
73 if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") &&
74 !of_device_is_compatible(hose->dn, "ibm,plb-pcix") &&
75 !of_device_is_compatible(hose->dn, "ibm,plb-pci"))
76 return;
77
78 /* Hide the PCI host BARs from the kernel as their content doesn't
79 * fit well in the resource management
80 */
81 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
82 dev->resource[i].start = dev->resource[i].end = 0;
83 dev->resource[i].flags = 0;
84 }
85
86 printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n",
87 pci_name(dev));
88}
89DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge);
90
5738ec6d
BH		 91static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
92 void __iomem *reg,
93 struct resource *res)
94{
95 u64 size;
96 const u32 *ranges;
97 int rlen;
98 int pna = of_n_addr_cells(hose->dn);
99 int np = pna + 5;
100
101 /* Default */
102 res->start = 0;
103 res->end = size = 0x80000000;
104 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
105
106 /* Get dma-ranges property */
107 ranges = of_get_property(hose->dn, "dma-ranges", &rlen);
108 if (ranges == NULL)
109 goto out;
110
111 /* Walk it */
112 while ((rlen -= np * 4) >= 0) {
113 u32 pci_space = ranges[0];
114 u64 pci_addr = of_read_number(ranges + 1, 2);
115 u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3);
116 size = of_read_number(ranges + pna + 3, 2);
117 ranges += np;
118 if (cpu_addr == OF_BAD_ADDR || size == 0)
119 continue;
120
121 /* We only care about memory */
122 if ((pci_space & 0x03000000) != 0x02000000)
123 continue;
124
125 /* We currently only support memory at 0, and pci_addr
126 * within 32 bits space
127 */
128 if (cpu_addr != 0 || pci_addr > 0xffffffff) {
129 printk(KERN_WARNING "%s: Ignored unsupported dma range"
130 " 0x%016llx...0x%016llx -> 0x%016llx\n",
131 hose->dn->full_name,
132 pci_addr, pci_addr + size - 1, cpu_addr);
133 continue;
134 }
135
136 /* Check if not prefetchable */
137 if (!(pci_space & 0x40000000))
138 res->flags &= ~IORESOURCE_PREFETCH;
139
140
141 /* Use that */
142 res->start = pci_addr;
143#ifndef CONFIG_RESOURCES_64BIT
144 /* Beware of 32 bits resources */
145 if ((pci_addr + size) > 0x100000000ull)
146 res->end = 0xffffffff;
147 else
148#endif
149 res->end = res->start + size - 1;
150 break;
151 }
152
153 /* We only support one global DMA offset */
154 if (dma_offset_set && pci_dram_offset != res->start) {
155 printk(KERN_ERR "%s: dma-ranges(s) mismatch\n",
156 hose->dn->full_name);
157 return -ENXIO;
158 }
159
160 /* Check that we can fit all of memory as we don't support
161 * DMA bounce buffers
162 */
163 if (size < total_memory) {
164 printk(KERN_ERR "%s: dma-ranges too small "
165 "(size=%llx total_memory=%lx)\n",
166 hose->dn->full_name, size, total_memory);
167 return -ENXIO;
168 }
169
170 /* Check we are a power of 2 size and that base is a multiple of size*/
171 if (!is_power_of_2(size) ||
172 (res->start & (size - 1)) != 0) {
173 printk(KERN_ERR "%s: dma-ranges unaligned\n",
174 hose->dn->full_name);
175 return -ENXIO;
176 }
177
178 /* Check that we are fully contained within 32 bits space */
179 if (res->end > 0xffffffff) {
180 printk(KERN_ERR "%s: dma-ranges outside of 32 bits space\n",
181 hose->dn->full_name);
182 return -ENXIO;
183 }
184 out:
185 dma_offset_set = 1;
186 pci_dram_offset = res->start;
187
188 printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n",
189 pci_dram_offset);
190 return 0;
191}
192
193/*
194 * 4xx PCI 2.x part
195 */
c839e0ef
BH		 196
197static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
198 void __iomem *reg)
199{
200 u32 la, ma, pcila, pciha;
201 int i, j;
202
203 /* Setup outbound memory windows */
204 for (i = j = 0; i < 3; i++) {
205 struct resource *res = &hose->mem_resources[i];
206
207 /* we only care about memory windows */
208 if (!(res->flags & IORESOURCE_MEM))
209 continue;
210 if (j > 2) {
211 printk(KERN_WARNING "%s: Too many ranges\n",
212 hose->dn->full_name);
213 break;
214 }
215
216 /* Calculate register values */
217 la = res->start;
a2d2e1ec
BH		 218 pciha = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
219 pcila = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
c839e0ef
BH		 220
221 ma = res->end + 1 - res->start;
222 if (!is_power_of_2(ma) || ma < 0x1000 || ma > 0xffffffffu) {
223 printk(KERN_WARNING "%s: Resource out of range\n",
224 hose->dn->full_name);
225 continue;
226 }
227 ma = (0xffffffffu << ilog2(ma)) | 0x1;
228 if (res->flags & IORESOURCE_PREFETCH)
229 ma |= 0x2;
230
231 /* Program register values */
232 writel(la, reg + PCIL0_PMM0LA + (0x10 * j));
233 writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * j));
234 writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * j));
235 writel(ma, reg + PCIL0_PMM0MA + (0x10 * j));
236 j++;
237 }
238}
239
240static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose,
241 void __iomem *reg,
242 const struct resource *res)
243{
244 resource_size_t size = res->end - res->start + 1;
245 u32 sa;
246
247 /* Calculate window size */
248 sa = (0xffffffffu << ilog2(size)) | 1;
249 sa |= 0x1;
250
251 /* RAM is always at 0 local for now */
252 writel(0, reg + PCIL0_PTM1LA);
253 writel(sa, reg + PCIL0_PTM1MS);
254
255 /* Map on PCI side */
256 early_write_config_dword(hose, hose->first_busno, 0,
257 PCI_BASE_ADDRESS_1, res->start);
258 early_write_config_dword(hose, hose->first_busno, 0,
259 PCI_BASE_ADDRESS_2, 0x00000000);
260 early_write_config_word(hose, hose->first_busno, 0,
261 PCI_COMMAND, 0x0006);
262}
263
5738ec6d
BH		 264static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
265{
266 /* NYI */
c839e0ef
BH		 267 struct resource rsrc_cfg;
268 struct resource rsrc_reg;
269 struct resource dma_window;
270 struct pci_controller *hose = NULL;
271 void __iomem *reg = NULL;
272 const int *bus_range;
273 int primary = 0;
274
275 /* Fetch config space registers address */
276 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
277 printk(KERN_ERR "%s:Can't get PCI config register base !",
278 np->full_name);
279 return;
280 }
281 /* Fetch host bridge internal registers address */
282 if (of_address_to_resource(np, 3, &rsrc_reg)) {
283 printk(KERN_ERR "%s: Can't get PCI internal register base !",
284 np->full_name);
285 return;
286 }
287
288 /* Check if primary bridge */
289 if (of_get_property(np, "primary", NULL))
290 primary = 1;
291
292 /* Get bus range if any */
293 bus_range = of_get_property(np, "bus-range", NULL);
294
295 /* Map registers */
296 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
297 if (reg == NULL) {
298 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
299 goto fail;
300 }
301
302 /* Allocate the host controller data structure */
303 hose = pcibios_alloc_controller(np);
304 if (!hose)
305 goto fail;
306
307 hose->first_busno = bus_range ? bus_range[0] : 0x0;
308 hose->last_busno = bus_range ? bus_range[1] : 0xff;
309
310 /* Setup config space */
311 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
312
313 /* Disable all windows */
314 writel(0, reg + PCIL0_PMM0MA);
315 writel(0, reg + PCIL0_PMM1MA);
316 writel(0, reg + PCIL0_PMM2MA);
317 writel(0, reg + PCIL0_PTM1MS);
318 writel(0, reg + PCIL0_PTM2MS);
319
320 /* Parse outbound mapping resources */
321 pci_process_bridge_OF_ranges(hose, np, primary);
322
323 /* Parse inbound mapping resources */
324 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
325 goto fail;
326
327 /* Configure outbound ranges POMs */
328 ppc4xx_configure_pci_PMMs(hose, reg);
329
330 /* Configure inbound ranges PIMs */
331 ppc4xx_configure_pci_PTMs(hose, reg, &dma_window);
332
333 /* We don't need the registers anymore */
334 iounmap(reg);
335 return;
336
337 fail:
338 if (hose)
339 pcibios_free_controller(hose);
340 if (reg)
341 iounmap(reg);
5738ec6d
BH		 342}
343
344/*
345 * 4xx PCI-X part
346 */
347
348static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
349 void __iomem *reg)
350{
351 u32 lah, lal, pciah, pcial, sa;
352 int i, j;
353
354 /* Setup outbound memory windows */
355 for (i = j = 0; i < 3; i++) {
356 struct resource *res = &hose->mem_resources[i];
357
358 /* we only care about memory windows */
359 if (!(res->flags & IORESOURCE_MEM))
360 continue;
361 if (j > 1) {
362 printk(KERN_WARNING "%s: Too many ranges\n",
363 hose->dn->full_name);
364 break;
365 }
366
367 /* Calculate register values */
a2d2e1ec
BH		 368 lah = RES_TO_U32_HIGH(res->start);
369 lal = RES_TO_U32_LOW(res->start);
370 pciah = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
371 pcial = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
5738ec6d
BH		 372 sa = res->end + 1 - res->start;
373 if (!is_power_of_2(sa) || sa < 0x100000 ||
374 sa > 0xffffffffu) {
375 printk(KERN_WARNING "%s: Resource out of range\n",
376 hose->dn->full_name);
377 continue;
378 }
379 sa = (0xffffffffu << ilog2(sa)) | 0x1;
380
381 /* Program register values */
382 if (j == 0) {
383 writel(lah, reg + PCIX0_POM0LAH);
384 writel(lal, reg + PCIX0_POM0LAL);
385 writel(pciah, reg + PCIX0_POM0PCIAH);
386 writel(pcial, reg + PCIX0_POM0PCIAL);
387 writel(sa, reg + PCIX0_POM0SA);
388 } else {
389 writel(lah, reg + PCIX0_POM1LAH);
390 writel(lal, reg + PCIX0_POM1LAL);
391 writel(pciah, reg + PCIX0_POM1PCIAH);
392 writel(pcial, reg + PCIX0_POM1PCIAL);
393 writel(sa, reg + PCIX0_POM1SA);
394 }
395 j++;
396 }
397}
398
399static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose,
400 void __iomem *reg,
401 const struct resource *res,
402 int big_pim,
403 int enable_msi_hole)
404{
405 resource_size_t size = res->end - res->start + 1;
406 u32 sa;
407
408 /* RAM is always at 0 */
409 writel(0x00000000, reg + PCIX0_PIM0LAH);
410 writel(0x00000000, reg + PCIX0_PIM0LAL);
411
412 /* Calculate window size */
413 sa = (0xffffffffu << ilog2(size)) | 1;
414 sa |= 0x1;
415 if (res->flags & IORESOURCE_PREFETCH)
416 sa |= 0x2;
417 if (enable_msi_hole)
418 sa |= 0x4;
419 writel(sa, reg + PCIX0_PIM0SA);
420 if (big_pim)
421 writel(0xffffffff, reg + PCIX0_PIM0SAH);
422
423 /* Map on PCI side */
424 writel(0x00000000, reg + PCIX0_BAR0H);
425 writel(res->start, reg + PCIX0_BAR0L);
426 writew(0x0006, reg + PCIX0_COMMAND);
427}
428
429static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
430{
431 struct resource rsrc_cfg;
432 struct resource rsrc_reg;
433 struct resource dma_window;
434 struct pci_controller *hose = NULL;
435 void __iomem *reg = NULL;
436 const int *bus_range;
437 int big_pim = 0, msi = 0, primary = 0;
438
439 /* Fetch config space registers address */
440 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
441 printk(KERN_ERR "%s:Can't get PCI-X config register base !",
442 np->full_name);
443 return;
444 }
445 /* Fetch host bridge internal registers address */
446 if (of_address_to_resource(np, 3, &rsrc_reg)) {
447 printk(KERN_ERR "%s: Can't get PCI-X internal register base !",
448 np->full_name);
449 return;
450 }
451
452 /* Check if it supports large PIMs (440GX) */
453 if (of_get_property(np, "large-inbound-windows", NULL))
454 big_pim = 1;
455
456 /* Check if we should enable MSIs inbound hole */
457 if (of_get_property(np, "enable-msi-hole", NULL))
458 msi = 1;
459
460 /* Check if primary bridge */
461 if (of_get_property(np, "primary", NULL))
462 primary = 1;
463
464 /* Get bus range if any */
465 bus_range = of_get_property(np, "bus-range", NULL);
466
467 /* Map registers */
468 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
469 if (reg == NULL) {
470 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
471 goto fail;
472 }
473
474 /* Allocate the host controller data structure */
475 hose = pcibios_alloc_controller(np);
476 if (!hose)
477 goto fail;
478
479 hose->first_busno = bus_range ? bus_range[0] : 0x0;
480 hose->last_busno = bus_range ? bus_range[1] : 0xff;
481
482 /* Setup config space */
483 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
484
485 /* Disable all windows */
486 writel(0, reg + PCIX0_POM0SA);
487 writel(0, reg + PCIX0_POM1SA);
488 writel(0, reg + PCIX0_POM2SA);
489 writel(0, reg + PCIX0_PIM0SA);
490 writel(0, reg + PCIX0_PIM1SA);
491 writel(0, reg + PCIX0_PIM2SA);
492 if (big_pim) {
493 writel(0, reg + PCIX0_PIM0SAH);
494 writel(0, reg + PCIX0_PIM2SAH);
495 }
496
497 /* Parse outbound mapping resources */
498 pci_process_bridge_OF_ranges(hose, np, primary);
499
500 /* Parse inbound mapping resources */
501 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
502 goto fail;
503
504 /* Configure outbound ranges POMs */
505 ppc4xx_configure_pcix_POMs(hose, reg);
506
507 /* Configure inbound ranges PIMs */
508 ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi);
509
510 /* We don't need the registers anymore */
511 iounmap(reg);
512 return;
513
514 fail:
515 if (hose)
516 pcibios_free_controller(hose);
517 if (reg)
518 iounmap(reg);
519}
520
a2d2e1ec
BH		 521#ifdef CONFIG_PPC4xx_PCI_EXPRESS
522
5738ec6d
BH		 523/*
524 * 4xx PCI-Express part
a2d2e1ec
BH		 525 *
526 * We support 3 parts currently based on the compatible property:
527 *
accf5ef2 528 * ibm,plb-pciex-440spe
a2d2e1ec 529 * ibm,plb-pciex-405ex
66b7e504 530 * ibm,plb-pciex-460ex
a2d2e1ec
BH		 531 *
532 * Anything else will be rejected for now as they are all subtly
533 * different unfortunately.
534 *
5738ec6d 535 */
a2d2e1ec 536
78994e24 537#define MAX_PCIE_BUS_MAPPED 0x40
a2d2e1ec
BH		 538
539struct ppc4xx_pciex_port
540{
541 struct pci_controller *hose;
542 struct device_node *node;
543 unsigned int index;
544 int endpoint;
035ee428
BH		 545 int link;
546 int has_ibpre;
a2d2e1ec
BH		 547 unsigned int sdr_base;
548 dcr_host_t dcrs;
549 struct resource cfg_space;
550 struct resource utl_regs;
035ee428 551 void __iomem *utl_base;
a2d2e1ec
BH		 552};
553
554static struct ppc4xx_pciex_port *ppc4xx_pciex_ports;
555static unsigned int ppc4xx_pciex_port_count;
556
557struct ppc4xx_pciex_hwops
558{
559 int (*core_init)(struct device_node *np);
560 int (*port_init_hw)(struct ppc4xx_pciex_port *port);
561 int (*setup_utl)(struct ppc4xx_pciex_port *port);
562};
563
564static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops;
565
566#ifdef CONFIG_44x
567
568/* Check various reset bits of the 440SPe PCIe core */
569static int __init ppc440spe_pciex_check_reset(struct device_node *np)
570{
571 u32 valPE0, valPE1, valPE2;
572 int err = 0;
573
574 /* SDR0_PEGPLLLCT1 reset */
575 if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) {
576 /*
577 * the PCIe core was probably already initialised
578 * by firmware - let's re-reset RCSSET regs
579 *
580 * -- Shouldn't we also re-reset the whole thing ? -- BenH
581 */
582 pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n");
583 mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000);
584 mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000);
585 mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000);
586 }
587
588 valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET);
589 valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET);
590 valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET);
591
592 /* SDR0_PExRCSSET rstgu */
593 if (!(valPE0 & 0x01000000) ||
594 !(valPE1 & 0x01000000) ||
595 !(valPE2 & 0x01000000)) {
596 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
597 err = -1;
598 }
599
600 /* SDR0_PExRCSSET rstdl */
601 if (!(valPE0 & 0x00010000) ||
602 !(valPE1 & 0x00010000) ||
603 !(valPE2 & 0x00010000)) {
604 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
605 err = -1;
606 }
607
608 /* SDR0_PExRCSSET rstpyn */
609 if ((valPE0 & 0x00001000) ||
610 (valPE1 & 0x00001000) ||
611 (valPE2 & 0x00001000)) {
612 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
613 err = -1;
614 }
615
616 /* SDR0_PExRCSSET hldplb */
617 if ((valPE0 & 0x10000000) ||
618 (valPE1 & 0x10000000) ||
619 (valPE2 & 0x10000000)) {
620 printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
621 err = -1;
622 }
623
624 /* SDR0_PExRCSSET rdy */
625 if ((valPE0 & 0x00100000) ||
626 (valPE1 & 0x00100000) ||
627 (valPE2 & 0x00100000)) {
628 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
629 err = -1;
630 }
631
632 /* SDR0_PExRCSSET shutdown */
633 if ((valPE0 & 0x00000100) ||
634 (valPE1 & 0x00000100) ||
635 (valPE2 & 0x00000100)) {
636 printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
637 err = -1;
638 }
639
640 return err;
641}
642
643/* Global PCIe core initializations for 440SPe core */
644static int __init ppc440spe_pciex_core_init(struct device_node *np)
645{
646 int time_out = 20;
647
648 /* Set PLL clock receiver to LVPECL */
6e42b21b 649 dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
a2d2e1ec
BH		 650
651 /* Shouldn't we do all the calibration stuff etc... here ? */
652 if (ppc440spe_pciex_check_reset(np))
653 return -ENXIO;
654
655 if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) {
656 printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration "
657 "failed (0x%08x)\n",
658 mfdcri(SDR0, PESDR0_PLLLCT2));
659 return -1;
660 }
661
662 /* De-assert reset of PCIe PLL, wait for lock */
6e42b21b 663 dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
a2d2e1ec
BH		 664 udelay(3);
665
666 while (time_out) {
667 if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) {
668 time_out--;
669 udelay(1);
670 } else
671 break;
672 }
673 if (!time_out) {
674 printk(KERN_INFO "PCIE: VCO output not locked\n");
675 return -1;
676 }
677
678 pr_debug("PCIE initialization OK\n");
679
680 return 3;
681}
682
683static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
684{
685 u32 val = 1 << 24;
686
687 if (port->endpoint)
688 val = PTYPE_LEGACY_ENDPOINT << 20;
689 else
690 val = PTYPE_ROOT_PORT << 20;
691
692 if (port->index == 0)
693 val |= LNKW_X8 << 12;
694 else
695 val |= LNKW_X4 << 12;
696
697 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
698 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);
accf5ef2 699 if (ppc440spe_revA())
a2d2e1ec
BH		 700 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);
701 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);
702 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);
703 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);
704 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);
705 if (port->index == 0) {
706 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,
707 0x35000000);
708 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,
709 0x35000000);
710 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,
711 0x35000000);
712 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
713 0x35000000);
714 }
6e42b21b
VB		 715 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
716 (1 << 24) | (1 << 16), 1 << 12);
a2d2e1ec
BH		 717
718 return 0;
719}
720
035ee428
BH		 721static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
722{
723 return ppc440spe_pciex_init_port_hw(port);
724}
725
726static int ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
a2d2e1ec 727{
035ee428
BH		 728 int rc = ppc440spe_pciex_init_port_hw(port);
729
730 port->has_ibpre = 1;
731
732 return rc;
733}
a2d2e1ec 734
035ee428
BH		 735static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port)
736{
a2d2e1ec
BH		 737 /* XXX Check what that value means... I hate magic */
738 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800);
739
a2d2e1ec
BH		 740 /*
741 * Set buffer allocations and then assert VRB and TXE.
742 */
035ee428
BH		 743 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
744 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
745 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000);
746 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000);
747 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000);
748 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000);
749 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
750 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
a2d2e1ec 751
035ee428
BH		 752 return 0;
753}
754
755static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port)
756{
757 /* Report CRS to the operating system */
758 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
a2d2e1ec
BH		 759
760 return 0;
761}
762
763static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
764{
765 .core_init = ppc440spe_pciex_core_init,
035ee428 766 .port_init_hw = ppc440speA_pciex_init_port_hw,
a2d2e1ec
BH		 767 .setup_utl = ppc440speA_pciex_init_utl,
768};
769
770static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
771{
772 .core_init = ppc440spe_pciex_core_init,
035ee428
BH		 773 .port_init_hw = ppc440speB_pciex_init_port_hw,
774 .setup_utl = ppc440speB_pciex_init_utl,
a2d2e1ec
BH		 775};
776
66b7e504
SR		 777static int __init ppc460ex_pciex_core_init(struct device_node *np)
778{
779 /* Nothing to do, return 2 ports */
780 return 2;
781}
782
783static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
784{
785 u32 val;
786 u32 utlset1;
787
5f91925c 788 if (port->endpoint)
66b7e504 789 val = PTYPE_LEGACY_ENDPOINT << 20;
5f91925c 790 else
66b7e504 791 val = PTYPE_ROOT_PORT << 20;
66b7e504
SR		 792
793 if (port->index == 0) {
794 val |= LNKW_X1 << 12;
5f91925c 795 utlset1 = 0x20000000;
66b7e504
SR		 796 } else {
797 val |= LNKW_X4 << 12;
5f91925c 798 utlset1 = 0x20101101;
66b7e504
SR		 799 }
800
801 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
802 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
803 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
804
805 switch (port->index) {
806 case 0:
807 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
808 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000136);
809 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
810
811 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);
812 break;
813
814 case 1:
815 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);
816 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
817 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
818 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
819 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000136);
820 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000136);
821 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000136);
822 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000136);
823 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
824 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
825 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);
826 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);
827
828 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000);
829 break;
830 }
831
832 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
833 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
834 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
835
836 /* Poll for PHY reset */
837 /* XXX FIXME add timeout */
838 switch (port->index) {
839 case 0:
840 while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1))
841 udelay(10);
842 break;
843 case 1:
844 while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1))
845 udelay(10);
846 break;
847 }
848
849 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
850 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
851 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
852 PESDRx_RCSSET_RSTPYN);
853
854 port->has_ibpre = 1;
855
856 return 0;
857}
858
859static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
860{
861 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
862
863 /*
864 * Set buffer allocations and then assert VRB and TXE.
865 */
866 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c);
867 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
868 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
869 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
870 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000);
871 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
872 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
873 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000);
874 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
875
876 return 0;
877}
878
879static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
880{
881 .core_init = ppc460ex_pciex_core_init,
882 .port_init_hw = ppc460ex_pciex_init_port_hw,
883 .setup_utl = ppc460ex_pciex_init_utl,
884};
885
a2d2e1ec
BH		 886#endif /* CONFIG_44x */
887
888#ifdef CONFIG_40x
889
890static int __init ppc405ex_pciex_core_init(struct device_node *np)
891{
892 /* Nothing to do, return 2 ports */
893 return 2;
894}
895
896static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port)
897{
898 /* Assert the PE0_PHY reset */
899 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);
900 msleep(1);
901
902 /* deassert the PE0_hotreset */
903 if (port->endpoint)
904 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);
905 else
906 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);
907
908 /* poll for phy !reset */
909 /* XXX FIXME add timeout */
910 while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000))
911 ;
912
913 /* deassert the PE0_gpl_utl_reset */
914 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);
915}
916
917static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
918{
919 u32 val;
920
921 if (port->endpoint)
922 val = PTYPE_LEGACY_ENDPOINT;
923 else
924 val = PTYPE_ROOT_PORT;
925
926 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,
927 1 << 24 | val << 20 | LNKW_X1 << 12);
928
929 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
930 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
931 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);
932 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);
933
934 /*
935 * Only reset the PHY when no link is currently established.
936 * This is for the Atheros PCIe board which has problems to establish
937 * the link (again) after this PHY reset. All other currently tested
938 * PCIe boards don't show this problem.
939 * This has to be re-tested and fixed in a later release!
940 */
a2d2e1ec
BH		 941 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
942 if (!(val & 0x00001000))
943 ppc405ex_pcie_phy_reset(port);
a2d2e1ec
BH		 944
945 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */
946
55aaf6ec
SR		 947 port->has_ibpre = 1;
948
a2d2e1ec
BH		 949 return 0;
950}
951
952static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
953{
a2d2e1ec
BH		 954 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
955
a2d2e1ec
BH		 956 /*
957 * Set buffer allocations and then assert VRB and TXE.
958 */
035ee428
BH		 959 out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000);
960 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
961 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
962 out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000);
963 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
964 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
965 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
966 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
a2d2e1ec 967
035ee428 968 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
a2d2e1ec
BH		 969
970 return 0;
971}
972
973static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
974{
975 .core_init = ppc405ex_pciex_core_init,
976 .port_init_hw = ppc405ex_pciex_init_port_hw,
977 .setup_utl = ppc405ex_pciex_init_utl,
978};
979
980#endif /* CONFIG_40x */
981
982
983/* Check that the core has been initied and if not, do it */
984static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
985{
986 static int core_init;
987 int count = -ENODEV;
988
989 if (core_init++)
990 return 0;
991
992#ifdef CONFIG_44x
accf5ef2
SR		 993 if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) {
994 if (ppc440spe_revA())
995 ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops;
996 else
997 ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
998 }
66b7e504
SR		 999 if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
1000 ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
a2d2e1ec
BH		 1001#endif /* CONFIG_44x */
1002#ifdef CONFIG_40x
1003 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
1004 ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops;
1005#endif
1006 if (ppc4xx_pciex_hwops == NULL) {
1007 printk(KERN_WARNING "PCIE: unknown host type %s\n",
1008 np->full_name);
1009 return -ENODEV;
1010 }
1011
1012 count = ppc4xx_pciex_hwops->core_init(np);
1013 if (count > 0) {
1014 ppc4xx_pciex_ports =
1015 kzalloc(count * sizeof(struct ppc4xx_pciex_port),
1016 GFP_KERNEL);
1017 if (ppc4xx_pciex_ports) {
1018 ppc4xx_pciex_port_count = count;
1019 return 0;
1020 }
1021 printk(KERN_WARNING "PCIE: failed to allocate ports array\n");
1022 return -ENOMEM;
1023 }
1024 return -ENODEV;
1025}
1026
1027static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port)
1028{
1029 /* We map PCI Express configuration based on the reg property */
1030 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH,
1031 RES_TO_U32_HIGH(port->cfg_space.start));
1032 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL,
1033 RES_TO_U32_LOW(port->cfg_space.start));
1034
1035 /* XXX FIXME: Use size from reg property. For now, map 512M */
1036 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001);
1037
1038 /* We map UTL registers based on the reg property */
1039 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH,
1040 RES_TO_U32_HIGH(port->utl_regs.start));
1041 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL,
1042 RES_TO_U32_LOW(port->utl_regs.start));
1043
1044 /* XXX FIXME: Use size from reg property */
1045 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001);
1046
1047 /* Disable all other outbound windows */
1048 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0);
1049 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0);
1050 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0);
1051 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
1052}
1053
035ee428
BH		 1054static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
1055 unsigned int sdr_offset,
1056 unsigned int mask,
1057 unsigned int value,
1058 int timeout_ms)
a2d2e1ec 1059{
a2d2e1ec
BH		 1060 u32 val;
1061
035ee428
BH		 1062 while(timeout_ms--) {
1063 val = mfdcri(SDR0, port->sdr_base + sdr_offset);
1064 if ((val & mask) == value) {
1065 pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
1066 port->index, sdr_offset, timeout_ms, val);
1067 return 0;
1068 }
1069 msleep(1);
1070 }
1071 return -1;
1072}
1073
1074static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1075{
1076 int rc = 0;
a2d2e1ec
BH		 1077
1078 /* Init HW */
1079 if (ppc4xx_pciex_hwops->port_init_hw)
1080 rc = ppc4xx_pciex_hwops->port_init_hw(port);
1081 if (rc != 0)
1082 return rc;
1083
035ee428 1084 printk(KERN_INFO "PCIE%d: Checking link...\n",
a2d2e1ec 1085 port->index);
a2d2e1ec 1086
035ee428
BH		 1087 /* Wait for reset to complete */
1088 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
1089 printk(KERN_WARNING "PCIE%d: PGRST failed\n",
1090 port->index);
a2d2e1ec
BH		 1091 return -1;
1092 }
1093
035ee428
BH		 1094 /* Check for card presence detect if supported, if not, just wait for
1095 * link unconditionally.
1096 *
1097 * note that we don't fail if there is no link, we just filter out
1098 * config space accesses. That way, it will be easier to implement
1099 * hotplug later on.
a2d2e1ec 1100 */
035ee428
BH		 1101 if (!port->has_ibpre ||
1102 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1103 1 << 28, 1 << 28, 100)) {
1104 printk(KERN_INFO
1105 "PCIE%d: Device detected, waiting for link...\n",
a2d2e1ec 1106 port->index);
035ee428
BH		 1107 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1108 0x1000, 0x1000, 2000))
1109 printk(KERN_WARNING
1110 "PCIE%d: Link up failed\n", port->index);
1111 else {
1112 printk(KERN_INFO
1113 "PCIE%d: link is up !\n", port->index);
1114 port->link = 1;
1115 }
1116 } else
1117 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
a2d2e1ec
BH		 1118
1119 /*
1120 * Initialize mapping: disable all regions and configure
1121 * CFG and REG regions based on resources in the device tree
1122 */
1123 ppc4xx_pciex_port_init_mapping(port);
1124
1125 /*
035ee428
BH		 1126 * Map UTL
1127 */
1128 port->utl_base = ioremap(port->utl_regs.start, 0x100);
1129 BUG_ON(port->utl_base == NULL);
1130
1131 /*
1132 * Setup UTL registers --BenH.
a2d2e1ec
BH		 1133 */
1134 if (ppc4xx_pciex_hwops->setup_utl)
1135 ppc4xx_pciex_hwops->setup_utl(port);
1136
1137 /*
1138 * Check for VC0 active and assert RDY.
1139 */
035ee428
BH		 1140 if (port->link &&
1141 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
1142 1 << 16, 1 << 16, 5000)) {
1143 printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index);
1144 port->link = 0;
a2d2e1ec 1145 }
035ee428 1146
6e42b21b 1147 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
a2d2e1ec
BH		 1148 msleep(100);
1149
1150 return 0;
1151}
1152
1153static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port,
1154 struct pci_bus *bus,
1155 unsigned int devfn)
1156{
1157 static int message;
1158
1159 /* Endpoint can not generate upstream(remote) config cycles */
1160 if (port->endpoint && bus->number != port->hose->first_busno)
1161 return PCIBIOS_DEVICE_NOT_FOUND;
1162
1163 /* Check we are within the mapped range */
1164 if (bus->number > port->hose->last_busno) {
1165 if (!message) {
1166 printk(KERN_WARNING "Warning! Probing bus %u"
1167 " out of range !\n", bus->number);
1168 message++;
1169 }
1170 return PCIBIOS_DEVICE_NOT_FOUND;
1171 }
1172
1173 /* The root complex has only one device / function */
1174 if (bus->number == port->hose->first_busno && devfn != 0)
1175 return PCIBIOS_DEVICE_NOT_FOUND;
1176
1177 /* The other side of the RC has only one device as well */
1178 if (bus->number == (port->hose->first_busno + 1) &&
1179 PCI_SLOT(devfn) != 0)
1180 return PCIBIOS_DEVICE_NOT_FOUND;
1181
035ee428
BH		 1182 /* Check if we have a link */
1183 if ((bus->number != port->hose->first_busno) && !port->link)
1184 return PCIBIOS_DEVICE_NOT_FOUND;
1185
a2d2e1ec
BH		 1186 return 0;
1187}
1188
1189static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port,
1190 struct pci_bus *bus,
1191 unsigned int devfn)
1192{
1193 int relbus;
1194
1195 /* Remove the casts when we finally remove the stupid volatile
1196 * in struct pci_controller
1197 */
1198 if (bus->number == port->hose->first_busno)
1199 return (void __iomem *)port->hose->cfg_addr;
1200
1201 relbus = bus->number - (port->hose->first_busno + 1);
1202 return (void __iomem *)port->hose->cfg_data +
1203 ((relbus << 20) | (devfn << 12));
1204}
1205
1206static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
1207 int offset, int len, u32 *val)
1208{
1209 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1210 struct ppc4xx_pciex_port *port =
1211 &ppc4xx_pciex_ports[hose->indirect_type];
1212 void __iomem *addr;
1213 u32 gpl_cfg;
1214
1215 BUG_ON(hose != port->hose);
1216
1217 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1218 return PCIBIOS_DEVICE_NOT_FOUND;
1219
1220 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1221
1222 /*
1223 * Reading from configuration space of non-existing device can
1224 * generate transaction errors. For the read duration we suppress
1225 * assertion of machine check exceptions to avoid those.
1226 */
1227 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1228 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1229
035ee428
BH		 1230 /* Make sure no CRS is recorded */
1231 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000);
1232
a2d2e1ec
BH		 1233 switch (len) {
1234 case 1:
1235 *val = in_8((u8 *)(addr + offset));
1236 break;
1237 case 2:
1238 *val = in_le16((u16 *)(addr + offset));
1239 break;
1240 default:
1241 *val = in_le32((u32 *)(addr + offset));
1242 break;
1243 }
1244
1245 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x"
1246 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1247 bus->number, hose->first_busno, hose->last_busno,
1248 devfn, offset, len, addr + offset, *val);
1249
035ee428
BH		 1250 /* Check for CRS (440SPe rev B does that for us but heh ..) */
1251 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) {
1252 pr_debug("Got CRS !\n");
1253 if (len != 4 || offset != 0)
1254 return PCIBIOS_DEVICE_NOT_FOUND;
1255 *val = 0xffff0001;
1256 }
1257
a2d2e1ec
BH		 1258 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1259
1260 return PCIBIOS_SUCCESSFUL;
1261}
1262
1263static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
1264 int offset, int len, u32 val)
1265{
1266 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1267 struct ppc4xx_pciex_port *port =
1268 &ppc4xx_pciex_ports[hose->indirect_type];
1269 void __iomem *addr;
1270 u32 gpl_cfg;
1271
1272 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1273 return PCIBIOS_DEVICE_NOT_FOUND;
1274
1275 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1276
1277 /*
1278 * Reading from configuration space of non-existing device can
1279 * generate transaction errors. For the read duration we suppress
1280 * assertion of machine check exceptions to avoid those.
1281 */
1282 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1283 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1284
1285 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x"
1286 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1287 bus->number, hose->first_busno, hose->last_busno,
1288 devfn, offset, len, addr + offset, val);
1289
1290 switch (len) {
1291 case 1:
1292 out_8((u8 *)(addr + offset), val);
1293 break;
1294 case 2:
1295 out_le16((u16 *)(addr + offset), val);
1296 break;
1297 default:
1298 out_le32((u32 *)(addr + offset), val);
1299 break;
1300 }
1301
1302 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1303
1304 return PCIBIOS_SUCCESSFUL;
1305}
1306
1307static struct pci_ops ppc4xx_pciex_pci_ops =
1308{
1309 .read = ppc4xx_pciex_read_config,
1310 .write = ppc4xx_pciex_write_config,
1311};
1312
1313static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
1314 struct pci_controller *hose,
1315 void __iomem *mbase)
1316{
1317 u32 lah, lal, pciah, pcial, sa;
1318 int i, j;
1319
1320 /* Setup outbound memory windows */
1321 for (i = j = 0; i < 3; i++) {
1322 struct resource *res = &hose->mem_resources[i];
1323
1324 /* we only care about memory windows */
1325 if (!(res->flags & IORESOURCE_MEM))
1326 continue;
1327 if (j > 1) {
1328 printk(KERN_WARNING "%s: Too many ranges\n",
1329 port->node->full_name);
1330 break;
1331 }
1332
1333 /* Calculate register values */
1334 lah = RES_TO_U32_HIGH(res->start);
1335 lal = RES_TO_U32_LOW(res->start);
1336 pciah = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
1337 pcial = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
1338 sa = res->end + 1 - res->start;
1339 if (!is_power_of_2(sa) || sa < 0x100000 ||
1340 sa > 0xffffffffu) {
1341 printk(KERN_WARNING "%s: Resource out of range\n",
1342 port->node->full_name);
1343 continue;
1344 }
1345 sa = (0xffffffffu << ilog2(sa)) | 0x1;
1346
1347 /* Program register values */
1348 switch (j) {
1349 case 0:
1350 out_le32(mbase + PECFG_POM0LAH, pciah);
1351 out_le32(mbase + PECFG_POM0LAL, pcial);
1352 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);
1353 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);
1354 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);
1355 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, sa | 3);
1356 break;
1357 case 1:
1358 out_le32(mbase + PECFG_POM1LAH, pciah);
1359 out_le32(mbase + PECFG_POM1LAL, pcial);
1360 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);
1361 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);
1362 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);
1363 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, sa | 3);
1364 break;
1365 }
1366 j++;
1367 }
1368
1369 /* Configure IO, always 64K starting at 0 */
1370 if (hose->io_resource.flags & IORESOURCE_IO) {
1371 lah = RES_TO_U32_HIGH(hose->io_base_phys);
1372 lal = RES_TO_U32_LOW(hose->io_base_phys);
1373 out_le32(mbase + PECFG_POM2LAH, 0);
1374 out_le32(mbase + PECFG_POM2LAL, 0);
1375 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah);
1376 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);
1377 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);
1378 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0xffff0000 | 3);
1379 }
1380}
1381
1382static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
1383 struct pci_controller *hose,
1384 void __iomem *mbase,
1385 struct resource *res)
1386{
1387 resource_size_t size = res->end - res->start + 1;
1388 u64 sa;
1389
80daac3f
SR		 1390 if (port->endpoint) {
1391 resource_size_t ep_addr = 0;
1392 resource_size_t ep_size = 32 << 20;
1393
1394 /* Currently we map a fixed 64MByte window to PLB address
1395 * 0 (SDRAM). This should probably be configurable via a dts
1396 * property.
1397 */
1398
1399 /* Calculate window size */
1400 sa = (0xffffffffffffffffull << ilog2(ep_size));;
1401
1402 /* Setup BAR0 */
1403 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1404 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) |
1405 PCI_BASE_ADDRESS_MEM_TYPE_64);
a2d2e1ec 1406
80daac3f
SR		 1407 /* Disable BAR1 & BAR2 */
1408 out_le32(mbase + PECFG_BAR1MPA, 0);
1409 out_le32(mbase + PECFG_BAR2HMPA, 0);
1410 out_le32(mbase + PECFG_BAR2LMPA, 0);
a2d2e1ec 1411
80daac3f
SR		 1412 out_le32(mbase + PECFG_PIM01SAH, RES_TO_U32_HIGH(sa));
1413 out_le32(mbase + PECFG_PIM01SAL, RES_TO_U32_LOW(sa));
1414
1415 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr));
1416 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(ep_addr));
1417 } else {
1418 /* Calculate window size */
1419 sa = (0xffffffffffffffffull << ilog2(size));;
1420 if (res->flags & IORESOURCE_PREFETCH)
1421 sa |= 0x8;
1422
1423 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1424 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa));
1425
1426 /* The setup of the split looks weird to me ... let's see
1427 * if it works
1428 */
1429 out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
1430 out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
1431 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
1432 out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
1433 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
1434 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
1435
1436 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start));
1437 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start));
1438 }
a2d2e1ec
BH		 1439
1440 /* Enable inbound mapping */
1441 out_le32(mbase + PECFG_PIMEN, 0x1);
1442
a2d2e1ec
BH		 1443 /* Enable I/O, Mem, and Busmaster cycles */
1444 out_le16(mbase + PCI_COMMAND,
1445 in_le16(mbase + PCI_COMMAND) |
1446 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1447}
1448
1449static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port)
1450{
1451 struct resource dma_window;
1452 struct pci_controller *hose = NULL;
1453 const int *bus_range;
1454 int primary = 0, busses;
1455 void __iomem *mbase = NULL, *cfg_data = NULL;
80daac3f
SR		 1456 const u32 *pval;
1457 u32 val;
a2d2e1ec
BH		 1458
1459 /* Check if primary bridge */
1460 if (of_get_property(port->node, "primary", NULL))
1461 primary = 1;
1462
1463 /* Get bus range if any */
1464 bus_range = of_get_property(port->node, "bus-range", NULL);
1465
1466 /* Allocate the host controller data structure */
1467 hose = pcibios_alloc_controller(port->node);
1468 if (!hose)
1469 goto fail;
1470
1471 /* We stick the port number in "indirect_type" so the config space
1472 * ops can retrieve the port data structure easily
1473 */
1474 hose->indirect_type = port->index;
1475
1476 /* Get bus range */
1477 hose->first_busno = bus_range ? bus_range[0] : 0x0;
1478 hose->last_busno = bus_range ? bus_range[1] : 0xff;
1479
1480 /* Because of how big mapping the config space is (1M per bus), we
1481 * limit how many busses we support. In the long run, we could replace
1482 * that with something akin to kmap_atomic instead. We set aside 1 bus
1483 * for the host itself too.
1484 */
1485 busses = hose->last_busno - hose->first_busno; /* This is off by 1 */
1486 if (busses > MAX_PCIE_BUS_MAPPED) {
1487 busses = MAX_PCIE_BUS_MAPPED;
1488 hose->last_busno = hose->first_busno + busses;
1489 }
1490
80daac3f
SR		 1491 if (!port->endpoint) {
1492 /* Only map the external config space in cfg_data for
1493 * PCIe root-complexes. External space is 1M per bus
1494 */
1495 cfg_data = ioremap(port->cfg_space.start +
1496 (hose->first_busno + 1) * 0x100000,
1497 busses * 0x100000);
1498 if (cfg_data == NULL) {
1499 printk(KERN_ERR "%s: Can't map external config space !",
1500 port->node->full_name);
1501 goto fail;
1502 }
1503 hose->cfg_data = cfg_data;
1504 }
1505
1506 /* Always map the host config space in cfg_addr.
1507 * Internal space is 4K
a2d2e1ec 1508 */
a2d2e1ec 1509 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
80daac3f
SR		 1510 if (mbase == NULL) {
1511 printk(KERN_ERR "%s: Can't map internal config space !",
a2d2e1ec
BH		 1512 port->node->full_name);
1513 goto fail;
1514 }
a2d2e1ec
BH		 1515 hose->cfg_addr = mbase;
1516
1517 pr_debug("PCIE %s, bus %d..%d\n", port->node->full_name,
1518 hose->first_busno, hose->last_busno);
1519 pr_debug(" config space mapped at: root @0x%p, other @0x%p\n",
1520 hose->cfg_addr, hose->cfg_data);
1521
1522 /* Setup config space */
1523 hose->ops = &ppc4xx_pciex_pci_ops;
1524 port->hose = hose;
1525 mbase = (void __iomem *)hose->cfg_addr;
1526
80daac3f
SR		 1527 if (!port->endpoint) {
1528 /*
1529 * Set bus numbers on our root port
1530 */
1531 out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno);
1532 out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1);
1533 out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno);
1534 }
a2d2e1ec
BH		 1535
1536 /*
1537 * OMRs are already reset, also disable PIMs
1538 */
1539 out_le32(mbase + PECFG_PIMEN, 0);
1540
1541 /* Parse outbound mapping resources */
1542 pci_process_bridge_OF_ranges(hose, port->node, primary);
1543
1544 /* Parse inbound mapping resources */
1545 if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0)
1546 goto fail;
1547
1548 /* Configure outbound ranges POMs */
1549 ppc4xx_configure_pciex_POMs(port, hose, mbase);
1550
1551 /* Configure inbound ranges PIMs */
1552 ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window);
1553
1554 /* The root complex doesn't show up if we don't set some vendor
80daac3f
SR		 1555 * and device IDs into it. The defaults below are the same bogus
1556 * one that the initial code in arch/ppc had. This can be
1557 * overwritten by setting the "vendor-id/device-id" properties
1558 * in the pciex node.
a2d2e1ec 1559 */
a2d2e1ec 1560
80daac3f
SR		 1561 /* Get the (optional) vendor-/device-id from the device-tree */
1562 pval = of_get_property(port->node, "vendor-id", NULL);
1563 if (pval) {
1564 val = *pval;
1565 } else {
1566 if (!port->endpoint)
1567 val = 0xaaa0 + port->index;
1568 else
1569 val = 0xeee0 + port->index;
1570 }
1571 out_le16(mbase + 0x200, val);
1572
1573 pval = of_get_property(port->node, "device-id", NULL);
1574 if (pval) {
1575 val = *pval;
1576 } else {
1577 if (!port->endpoint)
1578 val = 0xbed0 + port->index;
1579 else
1580 val = 0xfed0 + port->index;
1581 }
1582 out_le16(mbase + 0x202, val);
1583
1584 if (!port->endpoint) {
1585 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
1586 out_le32(mbase + 0x208, 0x06040001);
1587
1588 printk(KERN_INFO "PCIE%d: successfully set as root-complex\n",
1589 port->index);
1590 } else {
1591 /* Set Class Code to Processor/PPC */
1592 out_le32(mbase + 0x208, 0x0b200001);
1593
1594 printk(KERN_INFO "PCIE%d: successfully set as endpoint\n",
1595 port->index);
1596 }
a2d2e1ec 1597
a2d2e1ec
BH		 1598 return;
1599 fail:
1600 if (hose)
1601 pcibios_free_controller(hose);
1602 if (cfg_data)
1603 iounmap(cfg_data);
1604 if (mbase)
1605 iounmap(mbase);
1606}
1607
5738ec6d
BH		 1608static void __init ppc4xx_probe_pciex_bridge(struct device_node *np)
1609{
a2d2e1ec
BH		 1610 struct ppc4xx_pciex_port *port;
1611 const u32 *pval;
1612 int portno;
1613 unsigned int dcrs;
80daac3f 1614 const char *val;
a2d2e1ec
BH		 1615
1616 /* First, proceed to core initialization as we assume there's
1617 * only one PCIe core in the system
1618 */
1619 if (ppc4xx_pciex_check_core_init(np))
1620 return;
1621
1622 /* Get the port number from the device-tree */
1623 pval = of_get_property(np, "port", NULL);
1624 if (pval == NULL) {
1625 printk(KERN_ERR "PCIE: Can't find port number for %s\n",
1626 np->full_name);
1627 return;
1628 }
1629 portno = *pval;
1630 if (portno >= ppc4xx_pciex_port_count) {
1631 printk(KERN_ERR "PCIE: port number out of range for %s\n",
1632 np->full_name);
1633 return;
1634 }
1635 port = &ppc4xx_pciex_ports[portno];
1636 port->index = portno;
1637 port->node = of_node_get(np);
1638 pval = of_get_property(np, "sdr-base", NULL);
1639 if (pval == NULL) {
1640 printk(KERN_ERR "PCIE: missing sdr-base for %s\n",
1641 np->full_name);
1642 return;
1643 }
1644 port->sdr_base = *pval;
1645
80daac3f
SR		 1646 /* Check if device_type property is set to "pci" or "pci-endpoint".
1647 * Resulting from this setup this PCIe port will be configured
1648 * as root-complex or as endpoint.
1649 */
1650 val = of_get_property(port->node, "device_type", NULL);
1651 if (!strcmp(val, "pci-endpoint")) {
1652 port->endpoint = 1;
1653 } else if (!strcmp(val, "pci")) {
1654 port->endpoint = 0;
1655 } else {
1656 printk(KERN_ERR "PCIE: missing or incorrect device_type for %s\n",
1657 np->full_name);
1658 return;
1659 }
035ee428 1660
a2d2e1ec
BH		 1661 /* Fetch config space registers address */
1662 if (of_address_to_resource(np, 0, &port->cfg_space)) {
1663 printk(KERN_ERR "%s: Can't get PCI-E config space !",
1664 np->full_name);
1665 return;
1666 }
1667 /* Fetch host bridge internal registers address */
1668 if (of_address_to_resource(np, 1, &port->utl_regs)) {
1669 printk(KERN_ERR "%s: Can't get UTL register base !",
1670 np->full_name);
1671 return;
1672 }
1673
1674 /* Map DCRs */
1675 dcrs = dcr_resource_start(np, 0);
1676 if (dcrs == 0) {
1677 printk(KERN_ERR "%s: Can't get DCR register base !",
1678 np->full_name);
1679 return;
1680 }
1681 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
1682
1683 /* Initialize the port specific registers */
035ee428
BH		 1684 if (ppc4xx_pciex_port_init(port)) {
1685 printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index);
a2d2e1ec 1686 return;
035ee428 1687 }
a2d2e1ec
BH		 1688
1689 /* Setup the linux hose data structure */
1690 ppc4xx_pciex_port_setup_hose(port);
5738ec6d
BH		 1691}
1692
a2d2e1ec
BH		 1693#endif /* CONFIG_PPC4xx_PCI_EXPRESS */
1694
5738ec6d
BH		 1695static int __init ppc4xx_pci_find_bridges(void)
1696{
1697 struct device_node *np;
1698
a2d2e1ec 1699#ifdef CONFIG_PPC4xx_PCI_EXPRESS
5738ec6d
BH		 1700 for_each_compatible_node(np, NULL, "ibm,plb-pciex")
1701 ppc4xx_probe_pciex_bridge(np);
a2d2e1ec 1702#endif
5738ec6d
BH		 1703 for_each_compatible_node(np, NULL, "ibm,plb-pcix")
1704 ppc4xx_probe_pcix_bridge(np);
1705 for_each_compatible_node(np, NULL, "ibm,plb-pci")
1706 ppc4xx_probe_pci_bridge(np);
1707
1708 return 0;
1709}
1710arch_initcall(ppc4xx_pci_find_bridges);
1711
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