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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[net-next-2.6.git] / arch / powerpc / sysdev / fsl_pci.c
CommitLineData
b809b3e8 1/*
5b70a097 2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
b809b3e8 3 *
598804cd
AV		 4 * Copyright 2007-2009 Freescale Semiconductor, Inc.
5 * Copyright 2008-2009 MontaVista Software, Inc.
b809b3e8 6 *
9ac4dd30
ZR		 7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
8 * Recode: ZHANG WEI <wei.zhang@freescale.com>
9 * Rewrite the routing for Frescale PCI and PCI Express
10 * Roy Zang <tie-fei.zang@freescale.com>
598804cd
AV		 11 * MPC83xx PCI-Express support:
12 * Tony Li <tony.li@freescale.com>
13 * Anton Vorontsov <avorontsov@ru.mvista.com>
b809b3e8
JL		 14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
9ac4dd30 20#include <linux/kernel.h>
b809b3e8 21#include <linux/pci.h>
9ac4dd30
ZR		 22#include <linux/delay.h>
23#include <linux/string.h>
24#include <linux/init.h>
25#include <linux/bootmem.h>
95f72d1e 26#include <linux/memblock.h>
54c18193 27#include <linux/log2.h>
5a0e3ad6 28#include <linux/slab.h>
b809b3e8 29
b809b3e8
JL		 30#include <asm/io.h>
31#include <asm/prom.h>
b809b3e8 32#include <asm/pci-bridge.h>
9ac4dd30 33#include <asm/machdep.h>
b809b3e8 34#include <sysdev/fsl_soc.h>
55c44991 35#include <sysdev/fsl_pci.h>
b809b3e8 36
598804cd
AV		 37static int fsl_pcie_bus_fixup;
38
39static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
40{
41 /* if we aren't a PCIe don't bother */
42 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
43 return;
44
45 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
46 fsl_pcie_bus_fixup = 1;
47 return;
48}
49
50static int __init fsl_pcie_check_link(struct pci_controller *hose)
51{
52 u32 val;
53
54 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
55 if (val < PCIE_LTSSM_L0)
56 return 1;
57 return 0;
58}
59
5753c082 60#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
a097a78c
TP		 61static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
62 unsigned int index, const struct resource *res,
63 resource_size_t offset)
64{
65 resource_size_t pci_addr = res->start - offset;
66 resource_size_t phys_addr = res->start;
67 resource_size_t size = res->end - res->start + 1;
68 u32 flags = 0x80044000; /* enable & mem R/W */
69 unsigned int i;
70
71 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
72 (u64)res->start, (u64)size);
73
565f3764
TP		 74 if (res->flags & IORESOURCE_PREFETCH)
75 flags |= 0x10000000; /* enable relaxed ordering */
76
a097a78c
TP		 77 for (i = 0; size > 0; i++) {
78 unsigned int bits = min(__ilog2(size),
79 __ffs(pci_addr | phys_addr));
80
81 if (index + i >= 5)
82 return -1;
83
84 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
85 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
86 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
87 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
88
89 pci_addr += (resource_size_t)1U << bits;
90 phys_addr += (resource_size_t)1U << bits;
91 size -= (resource_size_t)1U << bits;
92 }
93
94 return i;
95}
96
9ac4dd30 97/* atmu setup for fsl pci/pcie controller */
c9dadffb
AV		 98static void __init setup_pci_atmu(struct pci_controller *hose,
99 struct resource *rsrc)
b809b3e8 100{
9ac4dd30 101 struct ccsr_pci __iomem *pci;
54c18193
KG		 102 int i, j, n, mem_log, win_idx = 2;
103 u64 mem, sz, paddr_hi = 0;
104 u64 paddr_lo = ULLONG_MAX;
105 u32 pcicsrbar = 0, pcicsrbar_sz;
106 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
107 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
108 char *name = hose->dn->full_name;
b809b3e8 109
72b122cc
KG		 110 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
111 (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1);
9ac4dd30 112 pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
a097a78c
TP		 113 if (!pci) {
114 dev_err(hose->parent, "Unable to map ATMU registers\n");
115 return;
116 }
9ac4dd30 117
a097a78c 118 /* Disable all windows (except powar0 since it's ignored) */
9ac4dd30
ZR		 119 for(i = 1; i < 5; i++)
120 out_be32(&pci->pow[i].powar, 0);
121 for(i = 0; i < 3; i++)
122 out_be32(&pci->piw[i].piwar, 0);
123
124 /* Setup outbound MEM window */
a097a78c
TP		 125 for(i = 0, j = 1; i < 3; i++) {
126 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
127 continue;
128
54c18193
KG		 129 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
130 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
131
a097a78c
TP		 132 n = setup_one_atmu(pci, j, &hose->mem_resources[i],
133 hose->pci_mem_offset);
134
135 if (n < 0 || j >= 5) {
136 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
137 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
138 } else
139 j += n;
140 }
9ac4dd30
ZR		 141
142 /* Setup outbound IO window */
a097a78c
TP		 143 if (hose->io_resource.flags & IORESOURCE_IO) {
144 if (j >= 5) {
145 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
146 } else {
147 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
148 "phy base 0x%016llx.\n",
149 (u64)hose->io_resource.start,
150 (u64)hose->io_resource.end - (u64)hose->io_resource.start + 1,
151 (u64)hose->io_base_phys);
152 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
153 out_be32(&pci->pow[j].potear, 0);
154 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
155 /* Enable, IO R/W */
156 out_be32(&pci->pow[j].powar, 0x80088000
157 | (__ilog2(hose->io_resource.end
158 - hose->io_resource.start + 1) - 1));
159 }
9ac4dd30
ZR		 160 }
161
54c18193
KG		 162 /* convert to pci address space */
163 paddr_hi -= hose->pci_mem_offset;
164 paddr_lo -= hose->pci_mem_offset;
165
166 if (paddr_hi == paddr_lo) {
167 pr_err("%s: No outbound window space\n", name);
168 return ;
169 }
170
171 if (paddr_lo == 0) {
172 pr_err("%s: No space for inbound window\n", name);
173 return ;
174 }
175
176 /* setup PCSRBAR/PEXCSRBAR */
177 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
178 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
179 pcicsrbar_sz = ~pcicsrbar_sz + 1;
180
181 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
182 (paddr_lo > 0x100000000ull))
183 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
184 else
185 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
186 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
187
188 paddr_lo = min(paddr_lo, (u64)pcicsrbar);
189
190 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
191
192 /* Setup inbound mem window */
95f72d1e 193 mem = memblock_end_of_DRAM();
54c18193
KG		 194 sz = min(mem, paddr_lo);
195 mem_log = __ilog2_u64(sz);
196
197 /* PCIe can overmap inbound & outbound since RX & TX are separated */
198 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
199 /* Size window to exact size if power-of-two or one size up */
200 if ((1ull << mem_log) != mem) {
201 if ((1ull << mem_log) > mem)
202 pr_info("%s: Setting PCI inbound window "
203 "greater than memory size\n", name);
204 mem_log++;
205 }
206
207 piwar |= (mem_log - 1);
208
209 /* Setup inbound memory window */
210 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
211 out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
212 out_be32(&pci->piw[win_idx].piwar, piwar);
213 win_idx--;
214
215 hose->dma_window_base_cur = 0x00000000;
216 hose->dma_window_size = (resource_size_t)sz;
217 } else {
218 u64 paddr = 0;
219
220 /* Setup inbound memory window */
221 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
222 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
223 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
224 win_idx--;
225
226 paddr += 1ull << mem_log;
227 sz -= 1ull << mem_log;
228
229 if (sz) {
230 mem_log = __ilog2_u64(sz);
231 piwar |= (mem_log - 1);
232
233 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
234 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
235 out_be32(&pci->piw[win_idx].piwar, piwar);
236 win_idx--;
237
238 paddr += 1ull << mem_log;
239 }
240
241 hose->dma_window_base_cur = 0x00000000;
242 hose->dma_window_size = (resource_size_t)paddr;
243 }
a097a78c 244
54c18193
KG		 245 if (hose->dma_window_size < mem) {
246#ifndef CONFIG_SWIOTLB
247 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
248 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
249 name);
250#endif
251 /* adjusting outbound windows could reclaim space in mem map */
252 if (paddr_hi < 0xffffffffull)
253 pr_warning("%s: WARNING: Outbound window cfg leaves "
254 "gaps in memory map. Adjusting the memory map "
255 "could reduce unnecessary bounce buffering.\n",
256 name);
257
258 pr_info("%s: DMA window size is 0x%llx\n", name,
259 (u64)hose->dma_window_size);
260 }
89d93347 261
a097a78c 262 iounmap(pci);
b809b3e8
JL		 263}
264
c9dadffb 265static void __init setup_pci_cmd(struct pci_controller *hose)
b809b3e8 266{
b809b3e8 267 u16 cmd;
eb12af43
KG		 268 int cap_x;
269
b809b3e8
JL		 270 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
271 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
9ac4dd30 272 | PCI_COMMAND_IO;
b809b3e8 273 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
eb12af43
KG		 274
275 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
276 if (cap_x) {
277 int pci_x_cmd = cap_x + PCI_X_CMD;
278 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
279 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
280 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
281 } else {
282 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
283 }
9ad494f6
KG		 284}
285
6c0a11c1
KG		 286void fsl_pcibios_fixup_bus(struct pci_bus *bus)
287{
8206a110 288 struct pci_controller *hose = pci_bus_to_host(bus);
6c0a11c1
KG		 289 int i;
290
72b122cc
KG		 291 if ((bus->parent == hose->bus) &&
292 ((fsl_pcie_bus_fixup &&
293 early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) ||
294 (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)))
295 {
296 for (i = 0; i < 4; ++i) {
297 struct resource *res = bus->resource[i];
298 struct resource *par = bus->parent->resource[i];
299 if (res) {
300 res->start = 0;
301 res->end = 0;
302 res->flags = 0;
303 }
304 if (res && par) {
305 res->start = par->start;
306 res->end = par->end;
307 res->flags = par->flags;
308 }
6c0a11c1
KG		 309 }
310 }
311}
312
9ac4dd30 313int __init fsl_add_bridge(struct device_node *dev, int is_primary)
b809b3e8
JL		 314{
315 int len;
316 struct pci_controller *hose;
317 struct resource rsrc;
8efca493 318 const int *bus_range;
b809b3e8 319
9ac4dd30 320 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
b809b3e8
JL		 321
322 /* Fetch host bridge registers address */
9ac4dd30
ZR		 323 if (of_address_to_resource(dev, 0, &rsrc)) {
324 printk(KERN_WARNING "Can't get pci register base!");
325 return -ENOMEM;
326 }
b809b3e8
JL		 327
328 /* Get bus range if any */
e2eb6392 329 bus_range = of_get_property(dev, "bus-range", &len);
b809b3e8
JL		 330 if (bus_range == NULL || len < 2 * sizeof(int))
331 printk(KERN_WARNING "Can't get bus-range for %s, assume"
9ac4dd30 332 " bus 0\n", dev->full_name);
b809b3e8 333
7fe519c2 334 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
dbf8471f 335 hose = pcibios_alloc_controller(dev);
b809b3e8
JL		 336 if (!hose)
337 return -ENOMEM;
dbf8471f 338
b809b3e8 339 hose->first_busno = bus_range ? bus_range[0] : 0x0;
bf7c036f 340 hose->last_busno = bus_range ? bus_range[1] : 0xff;
b809b3e8 341
2e56ff20
KG		 342 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
343 PPC_INDIRECT_TYPE_BIG_ENDIAN);
9ac4dd30 344 setup_pci_cmd(hose);
b809b3e8 345
9ac4dd30 346 /* check PCI express link status */
957ecffc 347 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
7659c038 348 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
957ecffc 349 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
9ac4dd30 350 if (fsl_pcie_check_link(hose))
957ecffc
KG		 351 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
352 }
b809b3e8 353
df3c9019 354 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
9ac4dd30
ZR		 355 "Firmware bus number: %d->%d\n",
356 (unsigned long long)rsrc.start, hose->first_busno,
357 hose->last_busno);
b809b3e8 358
9ac4dd30 359 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
b809b3e8
JL		 360 hose, hose->cfg_addr, hose->cfg_data);
361
362 /* Interpret the "ranges" property */
363 /* This also maps the I/O region and sets isa_io/mem_base */
9ac4dd30 364 pci_process_bridge_OF_ranges(hose, dev, is_primary);
b809b3e8
JL		 365
366 /* Setup PEX window registers */
9ac4dd30 367 setup_pci_atmu(hose, &rsrc);
b809b3e8
JL		 368
369 return 0;
370}
9ac4dd30 371
72b122cc
KG		 372DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header);
373DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header);
374DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header);
375DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header);
376DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header);
377DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header);
378DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header);
bfa568d1
AV		 379DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569E, quirk_fsl_pcie_header);
380DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569, quirk_fsl_pcie_header);
72b122cc
KG		 381DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header);
382DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header);
383DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header);
384DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header);
385DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header);
386DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header);
387DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header);
388DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header);
389DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header);
390DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header);
2f3804ed
KG		 391DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536E, quirk_fsl_pcie_header);
392DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header);
72b122cc
KG		 393DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header);
394DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header);
395DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
a3f62bd2
KG		 396DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011E, quirk_fsl_pcie_header);
397DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011, quirk_fsl_pcie_header);
398DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013E, quirk_fsl_pcie_header);
399DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013, quirk_fsl_pcie_header);
400DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020E, quirk_fsl_pcie_header);
401DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020, quirk_fsl_pcie_header);
a28dec2f
AV		 402DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021E, quirk_fsl_pcie_header);
403DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021, quirk_fsl_pcie_header);
a3f62bd2
KG		 404DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022E, quirk_fsl_pcie_header);
405DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022, quirk_fsl_pcie_header);
406DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010E, quirk_fsl_pcie_header);
407DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010, quirk_fsl_pcie_header);
01af9507
KG		 408DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020E, quirk_fsl_pcie_header);
409DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020, quirk_fsl_pcie_header);
a3f62bd2
KG		 410DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040E, quirk_fsl_pcie_header);
411DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040, quirk_fsl_pcie_header);
412DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080E, quirk_fsl_pcie_header);
413DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080, quirk_fsl_pcie_header);
5753c082 414#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
76fe1ffc 415
35225802 416#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
e3b5e0d5 417DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8308, quirk_fsl_pcie_header);
598804cd
AV		 418DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314E, quirk_fsl_pcie_header);
419DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314, quirk_fsl_pcie_header);
420DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315E, quirk_fsl_pcie_header);
421DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315, quirk_fsl_pcie_header);
422DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377E, quirk_fsl_pcie_header);
423DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377, quirk_fsl_pcie_header);
424DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378E, quirk_fsl_pcie_header);
425DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378, quirk_fsl_pcie_header);
426
427struct mpc83xx_pcie_priv {
428 void __iomem *cfg_type0;
429 void __iomem *cfg_type1;
430 u32 dev_base;
431};
432
433/*
434 * With the convention of u-boot, the PCIE outbound window 0 serves
435 * as configuration transactions outbound.
436 */
437#define PEX_OUTWIN0_BAR 0xCA4
438#define PEX_OUTWIN0_TAL 0xCA8
439#define PEX_OUTWIN0_TAH 0xCAC
440
441static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
442{
8206a110 443 struct pci_controller *hose = pci_bus_to_host(bus);
598804cd
AV		 444
445 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
446 return PCIBIOS_DEVICE_NOT_FOUND;
447 /*
448 * Workaround for the HW bug: for Type 0 configure transactions the
449 * PCI-E controller does not check the device number bits and just
450 * assumes that the device number bits are 0.
451 */
452 if (bus->number == hose->first_busno ||
453 bus->primary == hose->first_busno) {
454 if (devfn & 0xf8)
455 return PCIBIOS_DEVICE_NOT_FOUND;
456 }
457
458 if (ppc_md.pci_exclude_device) {
459 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
460 return PCIBIOS_DEVICE_NOT_FOUND;
461 }
462
463 return PCIBIOS_SUCCESSFUL;
464}
465
466static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
467 unsigned int devfn, int offset)
468{
8206a110 469 struct pci_controller *hose = pci_bus_to_host(bus);
598804cd 470 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
f93611fa 471 u32 dev_base = bus->number << 24 | devfn << 16;
598804cd
AV		 472 int ret;
473
474 ret = mpc83xx_pcie_exclude_device(bus, devfn);
475 if (ret)
476 return NULL;
477
478 offset &= 0xfff;
479
480 /* Type 0 */
481 if (bus->number == hose->first_busno)
482 return pcie->cfg_type0 + offset;
483
484 if (pcie->dev_base == dev_base)
485 goto mapped;
486
487 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
488
489 pcie->dev_base = dev_base;
490mapped:
491 return pcie->cfg_type1 + offset;
492}
493
494static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
495 int offset, int len, u32 *val)
496{
497 void __iomem *cfg_addr;
498
499 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
500 if (!cfg_addr)
501 return PCIBIOS_DEVICE_NOT_FOUND;
502
503 switch (len) {
504 case 1:
505 *val = in_8(cfg_addr);
506 break;
507 case 2:
508 *val = in_le16(cfg_addr);
509 break;
510 default:
511 *val = in_le32(cfg_addr);
512 break;
513 }
514
515 return PCIBIOS_SUCCESSFUL;
516}
517
518static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
519 int offset, int len, u32 val)
520{
f93611fa 521 struct pci_controller *hose = pci_bus_to_host(bus);
598804cd
AV		 522 void __iomem *cfg_addr;
523
524 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
525 if (!cfg_addr)
526 return PCIBIOS_DEVICE_NOT_FOUND;
527
f93611fa
AV		 528 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
529 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
530 val &= 0xffffff00;
531
598804cd
AV		 532 switch (len) {
533 case 1:
534 out_8(cfg_addr, val);
535 break;
536 case 2:
537 out_le16(cfg_addr, val);
538 break;
539 default:
540 out_le32(cfg_addr, val);
541 break;
542 }
543
544 return PCIBIOS_SUCCESSFUL;
545}
546
547static struct pci_ops mpc83xx_pcie_ops = {
548 .read = mpc83xx_pcie_read_config,
549 .write = mpc83xx_pcie_write_config,
550};
551
552static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
553 struct resource *reg)
554{
555 struct mpc83xx_pcie_priv *pcie;
556 u32 cfg_bar;
557 int ret = -ENOMEM;
558
559 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
560 if (!pcie)
561 return ret;
562
563 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
564 if (!pcie->cfg_type0)
565 goto err0;
566
567 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
568 if (!cfg_bar) {
569 /* PCI-E isn't configured. */
570 ret = -ENODEV;
571 goto err1;
572 }
573
574 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
575 if (!pcie->cfg_type1)
576 goto err1;
577
578 WARN_ON(hose->dn->data);
579 hose->dn->data = pcie;
580 hose->ops = &mpc83xx_pcie_ops;
581
582 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
583 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
584
585 if (fsl_pcie_check_link(hose))
586 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
587
588 return 0;
589err1:
590 iounmap(pcie->cfg_type0);
591err0:
592 kfree(pcie);
593 return ret;
594
595}
596
76fe1ffc
JR		 597int __init mpc83xx_add_bridge(struct device_node *dev)
598{
598804cd 599 int ret;
76fe1ffc
JR		 600 int len;
601 struct pci_controller *hose;
5b70a097
JR		 602 struct resource rsrc_reg;
603 struct resource rsrc_cfg;
76fe1ffc 604 const int *bus_range;
5b70a097 605 int primary;
76fe1ffc 606
598804cd
AV		 607 if (!of_device_is_available(dev)) {
608 pr_warning("%s: disabled by the firmware.\n",
609 dev->full_name);
610 return -ENODEV;
611 }
76fe1ffc
JR		 612 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
613
614 /* Fetch host bridge registers address */
5b70a097
JR		 615 if (of_address_to_resource(dev, 0, &rsrc_reg)) {
616 printk(KERN_WARNING "Can't get pci register base!\n");
617 return -ENOMEM;
618 }
619
620 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
621
622 if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
623 printk(KERN_WARNING
624 "No pci config register base in dev tree, "
625 "using default\n");
626 /*
627 * MPC83xx supports up to two host controllers
628 * one at 0x8500 has config space registers at 0x8300
629 * one at 0x8600 has config space registers at 0x8380
630 */
631 if ((rsrc_reg.start & 0xfffff) == 0x8500)
632 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
633 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
634 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
635 }
636 /*
637 * Controller at offset 0x8500 is primary
638 */
639 if ((rsrc_reg.start & 0xfffff) == 0x8500)
640 primary = 1;
641 else
642 primary = 0;
76fe1ffc
JR		 643
644 /* Get bus range if any */
645 bus_range = of_get_property(dev, "bus-range", &len);
646 if (bus_range == NULL || len < 2 * sizeof(int)) {
647 printk(KERN_WARNING "Can't get bus-range for %s, assume"
648 " bus 0\n", dev->full_name);
649 }
650
7fe519c2 651 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
76fe1ffc
JR		 652 hose = pcibios_alloc_controller(dev);
653 if (!hose)
654 return -ENOMEM;
655
656 hose->first_busno = bus_range ? bus_range[0] : 0;
657 hose->last_busno = bus_range ? bus_range[1] : 0xff;
658
598804cd
AV		 659 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
660 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
661 if (ret)
662 goto err0;
663 } else {
664 setup_indirect_pci(hose, rsrc_cfg.start,
665 rsrc_cfg.start + 4, 0);
666 }
76fe1ffc 667
35225802 668 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
76fe1ffc 669 "Firmware bus number: %d->%d\n",
5b70a097 670 (unsigned long long)rsrc_reg.start, hose->first_busno,
76fe1ffc
JR		 671 hose->last_busno);
672
673 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
674 hose, hose->cfg_addr, hose->cfg_data);
675
676 /* Interpret the "ranges" property */
677 /* This also maps the I/O region and sets isa_io/mem_base */
678 pci_process_bridge_OF_ranges(hose, dev, primary);
679
680 return 0;
598804cd
AV		 681err0:
682 pcibios_free_controller(hose);
683 return ret;
76fe1ffc
JR		 684}
685#endif /* CONFIG_PPC_83xx */
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