[net-next-2.6.git] / arch / powerpc / sysdev / fsl_lbc.c

/*
 * Freescale LBC and UPM routines.
 *
 * Copyright © 2007-2008  MontaVista Software, Inc.
 * Copyright © 2010 Freescale Semiconductor
 *
 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
 * Author: Jack Lan <Jack.Lan@freescale.com>
 * Author: Roy Zang <tie-fei.zang@freescale.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/compiler.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/mod_devicetable.h>
#include <asm/prom.h>
#include <asm/fsl_lbc.h>

static spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
EXPORT_SYMBOL(fsl_lbc_ctrl_dev);

/**
 * fsl_lbc_addr - convert the base address
 * @addr_base:	base address of the memory bank
 *
 * This function converts a base address of lbc into the right format for the
 * BR register. If the SOC has eLBC then it returns 32bit physical address
 * else it convers a 34bit local bus physical address to correct format of
 * 32bit address for BR register (Example: MPC8641).
 */
u32 fsl_lbc_addr(phys_addr_t addr_base)
{
	struct device_node *np = fsl_lbc_ctrl_dev->dev->of_node;
	u32 addr = addr_base & 0xffff8000;

	if (of_device_is_compatible(np, "fsl,elbc"))
		return addr;

	return addr | ((addr_base & 0x300000000ull) >> 19);
}
EXPORT_SYMBOL(fsl_lbc_addr);

/**
 * fsl_lbc_find - find Localbus bank
 * @addr_base:	base address of the memory bank
 *
 * This function walks LBC banks comparing "Base address" field of the BR
 * registers with the supplied addr_base argument. When bases match this
 * function returns bank number (starting with 0), otherwise it returns
 * appropriate errno value.
 */
int fsl_lbc_find(phys_addr_t addr_base)
{
	int i;
	struct fsl_lbc_regs __iomem *lbc;

	if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
		return -ENODEV;

	lbc = fsl_lbc_ctrl_dev->regs;
	for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) {
		__be32 br = in_be32(&lbc->bank[i].br);
		__be32 or = in_be32(&lbc->bank[i].or);

		if (br & BR_V && (br & or & BR_BA) == fsl_lbc_addr(addr_base))
			return i;
	}

	return -ENOENT;
}
EXPORT_SYMBOL(fsl_lbc_find);

/**
 * fsl_upm_find - find pre-programmed UPM via base address
 * @addr_base:	base address of the memory bank controlled by the UPM
 * @upm:	pointer to the allocated fsl_upm structure
 *
 * This function fills fsl_upm structure so you can use it with the rest of
 * UPM API. On success this function returns 0, otherwise it returns
 * appropriate errno value.
 */
int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
{
	int bank;
	__be32 br;
	struct fsl_lbc_regs __iomem *lbc;

	bank = fsl_lbc_find(addr_base);
	if (bank < 0)
		return bank;

	if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
		return -ENODEV;

	lbc = fsl_lbc_ctrl_dev->regs;
	br = in_be32(&lbc->bank[bank].br);

	switch (br & BR_MSEL) {
	case BR_MS_UPMA:
		upm->mxmr = &lbc->mamr;
		break;
	case BR_MS_UPMB:
		upm->mxmr = &lbc->mbmr;
		break;
	case BR_MS_UPMC:
		upm->mxmr = &lbc->mcmr;
		break;
	default:
		return -EINVAL;
	}

	switch (br & BR_PS) {
	case BR_PS_8:
		upm->width = 8;
		break;
	case BR_PS_16:
		upm->width = 16;
		break;
	case BR_PS_32:
		upm->width = 32;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}
EXPORT_SYMBOL(fsl_upm_find);

/**
 * fsl_upm_run_pattern - actually run an UPM pattern
 * @upm:	pointer to the fsl_upm structure obtained via fsl_upm_find
 * @io_base:	remapped pointer to where memory access should happen
 * @mar:	MAR register content during pattern execution
 *
 * This function triggers dummy write to the memory specified by the io_base,
 * thus UPM pattern actually executed. Note that mar usage depends on the
 * pre-programmed AMX bits in the UPM RAM.
 */
int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
{
	int ret = 0;
	unsigned long flags;

	if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
		return -ENODEV;

	spin_lock_irqsave(&fsl_lbc_lock, flags);

	out_be32(&fsl_lbc_ctrl_dev->regs->mar, mar);

	switch (upm->width) {
	case 8:
		out_8(io_base, 0x0);
		break;
	case 16:
		out_be16(io_base, 0x0);
		break;
	case 32:
		out_be32(io_base, 0x0);
		break;
	default:
		ret = -EINVAL;
		break;
	}

	spin_unlock_irqrestore(&fsl_lbc_lock, flags);

	return ret;
}
EXPORT_SYMBOL(fsl_upm_run_pattern);

static int __devinit fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl)
{
	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;

	/* clear event registers */
	setbits32(&lbc->ltesr, LTESR_CLEAR);
	out_be32(&lbc->lteatr, 0);
	out_be32(&lbc->ltear, 0);
	out_be32(&lbc->lteccr, LTECCR_CLEAR);
	out_be32(&lbc->ltedr, LTEDR_ENABLE);

	/* Enable interrupts for any detected events */
	out_be32(&lbc->lteir, LTEIR_ENABLE);

	return 0;
}

/*
 * NOTE: This interrupt is used to report localbus events of various kinds,
 * such as transaction errors on the chipselects.
 */

static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data)
{
	struct fsl_lbc_ctrl *ctrl = data;
	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
	u32 status;

	status = in_be32(&lbc->ltesr);
	if (!status)
		return IRQ_NONE;

	out_be32(&lbc->ltesr, LTESR_CLEAR);
	out_be32(&lbc->lteatr, 0);
	out_be32(&lbc->ltear, 0);
	ctrl->irq_status = status;

	if (status & LTESR_BM)
		dev_err(ctrl->dev, "Local bus monitor time-out: "
			"LTESR 0x%08X\n", status);
	if (status & LTESR_WP)
		dev_err(ctrl->dev, "Write protect error: "
			"LTESR 0x%08X\n", status);
	if (status & LTESR_ATMW)
		dev_err(ctrl->dev, "Atomic write error: "
			"LTESR 0x%08X\n", status);
	if (status & LTESR_ATMR)
		dev_err(ctrl->dev, "Atomic read error: "
			"LTESR 0x%08X\n", status);
	if (status & LTESR_CS)
		dev_err(ctrl->dev, "Chip select error: "
			"LTESR 0x%08X\n", status);
	if (status & LTESR_UPM)
		;
	if (status & LTESR_FCT) {
		dev_err(ctrl->dev, "FCM command time-out: "
			"LTESR 0x%08X\n", status);
		smp_wmb();
		wake_up(&ctrl->irq_wait);
	}
	if (status & LTESR_PAR) {
		dev_err(ctrl->dev, "Parity or Uncorrectable ECC error: "
			"LTESR 0x%08X\n", status);
		smp_wmb();
		wake_up(&ctrl->irq_wait);
	}
	if (status & LTESR_CC) {
		smp_wmb();
		wake_up(&ctrl->irq_wait);
	}
	if (status & ~LTESR_MASK)
		dev_err(ctrl->dev, "Unknown error: "
			"LTESR 0x%08X\n", status);
	return IRQ_HANDLED;
}

/*
 * fsl_lbc_ctrl_probe
 *
 * called by device layer when it finds a device matching
 * one our driver can handled. This code allocates all of
 * the resources needed for the controller only.  The
 * resources for the NAND banks themselves are allocated
 * in the chip probe function.
*/

static int __devinit fsl_lbc_ctrl_probe(struct platform_device *dev)
{
	int ret;

	if (!dev->dev.of_node) {
		dev_err(&dev->dev, "Device OF-Node is NULL");
		return -EFAULT;
	}

	fsl_lbc_ctrl_dev = kzalloc(sizeof(*fsl_lbc_ctrl_dev), GFP_KERNEL);
	if (!fsl_lbc_ctrl_dev)
		return -ENOMEM;

	dev_set_drvdata(&dev->dev, fsl_lbc_ctrl_dev);

	spin_lock_init(&fsl_lbc_ctrl_dev->lock);
	init_waitqueue_head(&fsl_lbc_ctrl_dev->irq_wait);

	fsl_lbc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
	if (!fsl_lbc_ctrl_dev->regs) {
		dev_err(&dev->dev, "failed to get memory region\n");
		ret = -ENODEV;
		goto err;
	}

	fsl_lbc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
	if (fsl_lbc_ctrl_dev->irq == NO_IRQ) {
		dev_err(&dev->dev, "failed to get irq resource\n");
		ret = -ENODEV;
		goto err;
	}

	fsl_lbc_ctrl_dev->dev = &dev->dev;

	ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev);
	if (ret < 0)
		goto err;

	ret = request_irq(fsl_lbc_ctrl_dev->irq, fsl_lbc_ctrl_irq, 0,
				"fsl-lbc", fsl_lbc_ctrl_dev);
	if (ret != 0) {
		dev_err(&dev->dev, "failed to install irq (%d)\n",
			fsl_lbc_ctrl_dev->irq);
		ret = fsl_lbc_ctrl_dev->irq;
		goto err;
	}

	return 0;

err:
	iounmap(fsl_lbc_ctrl_dev->regs);
	kfree(fsl_lbc_ctrl_dev);
	return ret;
}

static const struct of_device_id fsl_lbc_match[] = {
	{ .compatible = "fsl,elbc", },
	{ .compatible = "fsl,pq3-localbus", },
	{ .compatible = "fsl,pq2-localbus", },
	{ .compatible = "fsl,pq2pro-localbus", },
	{},
};

static struct platform_driver fsl_lbc_ctrl_driver = {
	.driver = {
		.name = "fsl-lbc",
		.of_match_table = fsl_lbc_match,
	},
	.probe = fsl_lbc_ctrl_probe,
};

static int __init fsl_lbc_init(void)
{
	return platform_driver_register(&fsl_lbc_ctrl_driver);
}
module_init(fsl_lbc_init);
Commit	Line	Data
acaa7aa3 AV	1	/*
	2	* Freescale LBC and UPM routines.
	3	*
3ab8f2a2 RZ	4	* Copyright © 2007-2008 MontaVista Software, Inc.
3ab8f2a2 RZ	5	* Copyright © 2010 Freescale Semiconductor
acaa7aa3 AV	6	*
acaa7aa3 AV	7	* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
3ab8f2a2 RZ	8	* Author: Jack Lan <Jack.Lan@freescale.com>
3ab8f2a2 RZ	9	* Author: Roy Zang <tie-fei.zang@freescale.com>
acaa7aa3 AV	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*/
	16
c0da99d5 AV	17	#include <linux/init.h>
c0da99d5 AV	18	#include <linux/module.h>
acaa7aa3	19	#include <linux/kernel.h>
c0da99d5 AV	20	#include <linux/compiler.h>
	21	#include <linux/spinlock.h>
	22	#include <linux/types.h>
	23	#include <linux/io.h>
acaa7aa3	24	#include <linux/of.h>
3ab8f2a2 RZ	25	#include <linux/slab.h>
	26	#include <linux/platform_device.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/mod_devicetable.h>
c0da99d5	29	#include <asm/prom.h>
acaa7aa3 AV	30	#include <asm/fsl_lbc.h>
acaa7aa3 AV	31
c0da99d5	32	static spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
3ab8f2a2 RZ	33	struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
3ab8f2a2 RZ	34	EXPORT_SYMBOL(fsl_lbc_ctrl_dev);
acaa7aa3	35
0b824d2b LCB	36	/**
	37	* fsl_lbc_addr - convert the base address
	38	* @addr_base: base address of the memory bank
	39	*
	40	* This function converts a base address of lbc into the right format for the
	41	* BR register. If the SOC has eLBC then it returns 32bit physical address
	42	* else it convers a 34bit local bus physical address to correct format of
	43	* 32bit address for BR register (Example: MPC8641).
	44	*/
	45	u32 fsl_lbc_addr(phys_addr_t addr_base)
	46	{
	47	struct device_node *np = fsl_lbc_ctrl_dev->dev->of_node;
	48	u32 addr = addr_base & 0xffff8000;
	49
	50	if (of_device_is_compatible(np, "fsl,elbc"))
	51	return addr;
	52
	53	return addr \| ((addr_base & 0x300000000ull) >> 19);
	54	}
	55	EXPORT_SYMBOL(fsl_lbc_addr);
	56
acaa7aa3 AV	57	/**
	58	* fsl_lbc_find - find Localbus bank
	59	* @addr_base: base address of the memory bank
	60	*
	61	* This function walks LBC banks comparing "Base address" field of the BR
	62	* registers with the supplied addr_base argument. When bases match this
	63	* function returns bank number (starting with 0), otherwise it returns
	64	* appropriate errno value.
	65	*/
	66	int fsl_lbc_find(phys_addr_t addr_base)
	67	{
	68	int i;
3ab8f2a2	69	struct fsl_lbc_regs __iomem *lbc;
acaa7aa3	70
3ab8f2a2	71	if (!fsl_lbc_ctrl_dev \|\| !fsl_lbc_ctrl_dev->regs)
acaa7aa3 AV	72	return -ENODEV;
acaa7aa3 AV	73
3ab8f2a2 RZ	74	lbc = fsl_lbc_ctrl_dev->regs;
	75	for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) {
	76	__be32 br = in_be32(&lbc->bank[i].br);
	77	__be32 or = in_be32(&lbc->bank[i].or);
acaa7aa3	78
0b824d2b	79	if (br & BR_V && (br & or & BR_BA) == fsl_lbc_addr(addr_base))
acaa7aa3 AV	80	return i;
	81	}
	82
	83	return -ENOENT;
	84	}
	85	EXPORT_SYMBOL(fsl_lbc_find);
	86
	87	/**
	88	* fsl_upm_find - find pre-programmed UPM via base address
	89	* @addr_base: base address of the memory bank controlled by the UPM
	90	* @upm: pointer to the allocated fsl_upm structure
	91	*
	92	* This function fills fsl_upm structure so you can use it with the rest of
	93	* UPM API. On success this function returns 0, otherwise it returns
	94	* appropriate errno value.
	95	*/
	96	int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
	97	{
	98	int bank;
	99	__be32 br;
3ab8f2a2	100	struct fsl_lbc_regs __iomem *lbc;
acaa7aa3 AV	101
	102	bank = fsl_lbc_find(addr_base);
	103	if (bank < 0)
	104	return bank;
	105
3ab8f2a2 RZ	106	if (!fsl_lbc_ctrl_dev \|\| !fsl_lbc_ctrl_dev->regs)
	107	return -ENODEV;
	108
	109	lbc = fsl_lbc_ctrl_dev->regs;
	110	br = in_be32(&lbc->bank[bank].br);
acaa7aa3 AV	111
	112	switch (br & BR_MSEL) {
	113	case BR_MS_UPMA:
3ab8f2a2	114	upm->mxmr = &lbc->mamr;
acaa7aa3 AV	115	break;
acaa7aa3 AV	116	case BR_MS_UPMB:
3ab8f2a2	117	upm->mxmr = &lbc->mbmr;
acaa7aa3 AV	118	break;
acaa7aa3 AV	119	case BR_MS_UPMC:
3ab8f2a2	120	upm->mxmr = &lbc->mcmr;
acaa7aa3 AV	121	break;
	122	default:
	123	return -EINVAL;
	124	}
	125
	126	switch (br & BR_PS) {
	127	case BR_PS_8:
	128	upm->width = 8;
	129	break;
	130	case BR_PS_16:
	131	upm->width = 16;
	132	break;
	133	case BR_PS_32:
	134	upm->width = 32;
	135	break;
	136	default:
	137	return -EINVAL;
	138	}
	139
	140	return 0;
	141	}
	142	EXPORT_SYMBOL(fsl_upm_find);
c0da99d5 AV	143
	144	/**
	145	* fsl_upm_run_pattern - actually run an UPM pattern
	146	* @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
	147	* @io_base: remapped pointer to where memory access should happen
	148	* @mar: MAR register content during pattern execution
	149	*
	150	* This function triggers dummy write to the memory specified by the io_base,
	151	* thus UPM pattern actually executed. Note that mar usage depends on the
	152	* pre-programmed AMX bits in the UPM RAM.
	153	*/
	154	int fsl_upm_run_pattern(struct fsl_upm upm, void __iomem io_base, u32 mar)
	155	{
	156	int ret = 0;
	157	unsigned long flags;
	158
3ab8f2a2 RZ	159	if (!fsl_lbc_ctrl_dev \|\| !fsl_lbc_ctrl_dev->regs)
	160	return -ENODEV;
	161
c0da99d5 AV	162	spin_lock_irqsave(&fsl_lbc_lock, flags);
c0da99d5 AV	163
3ab8f2a2	164	out_be32(&fsl_lbc_ctrl_dev->regs->mar, mar);
c0da99d5 AV	165
	166	switch (upm->width) {
	167	case 8:
	168	out_8(io_base, 0x0);
	169	break;
	170	case 16:
	171	out_be16(io_base, 0x0);
	172	break;
	173	case 32:
	174	out_be32(io_base, 0x0);
	175	break;
	176	default:
	177	ret = -EINVAL;
	178	break;
	179	}
	180
	181	spin_unlock_irqrestore(&fsl_lbc_lock, flags);
	182
	183	return ret;
	184	}
	185	EXPORT_SYMBOL(fsl_upm_run_pattern);
3ab8f2a2 RZ	186
	187	static int __devinit fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl)
	188	{
	189	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
	190
	191	/* clear event registers */
	192	setbits32(&lbc->ltesr, LTESR_CLEAR);
	193	out_be32(&lbc->lteatr, 0);
	194	out_be32(&lbc->ltear, 0);
	195	out_be32(&lbc->lteccr, LTECCR_CLEAR);
	196	out_be32(&lbc->ltedr, LTEDR_ENABLE);
	197
	198	/* Enable interrupts for any detected events */
	199	out_be32(&lbc->lteir, LTEIR_ENABLE);
	200
	201	return 0;
	202	}
	203
	204	/*
	205	* NOTE: This interrupt is used to report localbus events of various kinds,
	206	* such as transaction errors on the chipselects.
	207	*/
	208
	209	static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data)
	210	{
	211	struct fsl_lbc_ctrl *ctrl = data;
	212	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
	213	u32 status;
	214
	215	status = in_be32(&lbc->ltesr);
	216	if (!status)
	217	return IRQ_NONE;
	218
	219	out_be32(&lbc->ltesr, LTESR_CLEAR);
	220	out_be32(&lbc->lteatr, 0);
	221	out_be32(&lbc->ltear, 0);
	222	ctrl->irq_status = status;
	223
	224	if (status & LTESR_BM)
	225	dev_err(ctrl->dev, "Local bus monitor time-out: "
	226	"LTESR 0x%08X\n", status);
	227	if (status & LTESR_WP)
	228	dev_err(ctrl->dev, "Write protect error: "
	229	"LTESR 0x%08X\n", status);
	230	if (status & LTESR_ATMW)
	231	dev_err(ctrl->dev, "Atomic write error: "
	232	"LTESR 0x%08X\n", status);
	233	if (status & LTESR_ATMR)
	234	dev_err(ctrl->dev, "Atomic read error: "
	235	"LTESR 0x%08X\n", status);
	236	if (status & LTESR_CS)
	237	dev_err(ctrl->dev, "Chip select error: "
	238	"LTESR 0x%08X\n", status);
	239	if (status & LTESR_UPM)
	240	;
	241	if (status & LTESR_FCT) {
	242	dev_err(ctrl->dev, "FCM command time-out: "
	243	"LTESR 0x%08X\n", status);
	244	smp_wmb();
	245	wake_up(&ctrl->irq_wait);
	246	}
	247	if (status & LTESR_PAR) {
	248	dev_err(ctrl->dev, "Parity or Uncorrectable ECC error: "
	249	"LTESR 0x%08X\n", status);
250	smp_wmb();
251	wake_up(&ctrl->irq_wait);
252	}
253	if (status & LTESR_CC) {
254	smp_wmb();
255	wake_up(&ctrl->irq_wait);
256	}
257	if (status & ~LTESR_MASK)
258	dev_err(ctrl->dev, "Unknown error: "
259	"LTESR 0x%08X\n", status);
260	return IRQ_HANDLED;
261	}
262
263	/*
264	* fsl_lbc_ctrl_probe
265	*
266	* called by device layer when it finds a device matching
267	* one our driver can handled. This code allocates all of
268	* the resources needed for the controller only. The
269	* resources for the NAND banks themselves are allocated
270	* in the chip probe function.
271	*/
272
273	static int __devinit fsl_lbc_ctrl_probe(struct platform_device *dev)
274	{
275	int ret;
276
277	if (!dev->dev.of_node) {
278	dev_err(&dev->dev, "Device OF-Node is NULL");
279	return -EFAULT;
280	}
281
282	fsl_lbc_ctrl_dev = kzalloc(sizeof(*fsl_lbc_ctrl_dev), GFP_KERNEL);
283	if (!fsl_lbc_ctrl_dev)
284	return -ENOMEM;
285
286	dev_set_drvdata(&dev->dev, fsl_lbc_ctrl_dev);
287
288	spin_lock_init(&fsl_lbc_ctrl_dev->lock);
289	init_waitqueue_head(&fsl_lbc_ctrl_dev->irq_wait);
290
291	fsl_lbc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
292	if (!fsl_lbc_ctrl_dev->regs) {
293	dev_err(&dev->dev, "failed to get memory region\n");
294	ret = -ENODEV;
295	goto err;
296	}
297
298	fsl_lbc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
299	if (fsl_lbc_ctrl_dev->irq == NO_IRQ) {
300	dev_err(&dev->dev, "failed to get irq resource\n");
301	ret = -ENODEV;
302	goto err;
303	}
304
305	fsl_lbc_ctrl_dev->dev = &dev->dev;
306
307	ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev);
308	if (ret < 0)
309	goto err;
310
311	ret = request_irq(fsl_lbc_ctrl_dev->irq, fsl_lbc_ctrl_irq, 0,
312	"fsl-lbc", fsl_lbc_ctrl_dev);
313	if (ret != 0) {
314	dev_err(&dev->dev, "failed to install irq (%d)\n",
315	fsl_lbc_ctrl_dev->irq);
316	ret = fsl_lbc_ctrl_dev->irq;
317	goto err;
318	}
319
320	return 0;
321
322	err:
323	iounmap(fsl_lbc_ctrl_dev->regs);
324	kfree(fsl_lbc_ctrl_dev);
325	return ret;
326	}
327
328	static const struct of_device_id fsl_lbc_match[] = {
329	{ .compatible = "fsl,elbc", },
330	{ .compatible = "fsl,pq3-localbus", },
331	{ .compatible = "fsl,pq2-localbus", },
332	{ .compatible = "fsl,pq2pro-localbus", },
333	{},
334	};
335
336	static struct platform_driver fsl_lbc_ctrl_driver = {
337	.driver = {
338	.name = "fsl-lbc",
339	.of_match_table = fsl_lbc_match,
340	},
341	.probe = fsl_lbc_ctrl_probe,
342	};
343
344	static int __init fsl_lbc_init(void)
345	{
346	return platform_driver_register(&fsl_lbc_ctrl_driver);
347	}
348	module_init(fsl_lbc_init);