[net-next-2.6.git] / arch / powerpc / sysdev / commproc.c

/*
 * General Purpose functions for the global management of the
 * Communication Processor Module.
 * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
 *
 * In addition to the individual control of the communication
 * channels, there are a few functions that globally affect the
 * communication processor.
 *
 * Buffer descriptors must be allocated from the dual ported memory
 * space.  The allocator for that is here.  When the communication
 * process is reset, we reclaim the memory available.  There is
 * currently no deallocator for this memory.
 * The amount of space available is platform dependent.  On the
 * MBX, the EPPC software loads additional microcode into the
 * communication processor, and uses some of the DP ram for this
 * purpose.  Current, the first 512 bytes and the last 256 bytes of
 * memory are used.  Right now I am conservative and only use the
 * memory that can never be used for microcode.  If there are
 * applications that require more DP ram, we can expand the boundaries
 * but then we have to be careful of any downloaded microcode.
 */
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/dma-mapping.h>
#include <linux/param.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <asm/mpc8xx.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/8xx_immap.h>
#include <asm/commproc.h>
#include <asm/io.h>
#include <asm/tlbflush.h>
#include <asm/rheap.h>
#include <asm/prom.h>

#include <asm/fs_pd.h>

#define CPM_MAP_SIZE    (0x4000)

static void m8xx_cpm_dpinit(void);
static	uint	host_buffer;	/* One page of host buffer */
static	uint	host_end;	/* end + 1 */
cpm8xx_t	*cpmp;		/* Pointer to comm processor space */
cpic8xx_t	*cpic_reg;

static struct device_node *cpm_pic_node;
static struct irq_host *cpm_pic_host;

static void cpm_mask_irq(unsigned int irq)
{
	unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;

	clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
}

static void cpm_unmask_irq(unsigned int irq)
{
	unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;

	setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
}

static void cpm_end_irq(unsigned int irq)
{
	unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;

	out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec));
}

static struct irq_chip cpm_pic = {
	.typename = " CPM PIC ",
	.mask = cpm_mask_irq,
	.unmask = cpm_unmask_irq,
	.eoi = cpm_end_irq,
};

int cpm_get_irq(void)
{
	int cpm_vec;

	/* Get the vector by setting the ACK bit and then reading
	 * the register.
	 */
	out_be16(&cpic_reg->cpic_civr, 1);
	cpm_vec = in_be16(&cpic_reg->cpic_civr);
	cpm_vec >>= 11;

	return irq_linear_revmap(cpm_pic_host, cpm_vec);
}

static int cpm_pic_host_match(struct irq_host *h, struct device_node *node)
{
	return cpm_pic_node == node;
}

static int cpm_pic_host_map(struct irq_host *h, unsigned int virq,
			  irq_hw_number_t hw)
{
	pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);

	get_irq_desc(virq)->status |= IRQ_LEVEL;
	set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
	return 0;
}

/* The CPM can generate the error interrupt when there is a race condition
 * between generating and masking interrupts.  All we have to do is ACK it
 * and return.  This is a no-op function so we don't need any special
 * tests in the interrupt handler.
 */
static	irqreturn_t cpm_error_interrupt(int irq, void *dev)
{
	return IRQ_HANDLED;
}

static struct irqaction cpm_error_irqaction = {
	.handler = cpm_error_interrupt,
	.mask = CPU_MASK_NONE,
	.name = "error",
};

static struct irq_host_ops cpm_pic_host_ops = {
	.match = cpm_pic_host_match,
	.map = cpm_pic_host_map,
};

unsigned int cpm_pic_init(void)
{
	struct device_node *np = NULL;
	struct resource res;
	unsigned int sirq = NO_IRQ, hwirq, eirq;
	int ret;

	pr_debug("cpm_pic_init\n");

	np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
	if (np == NULL) {
		printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");
		return sirq;
	}
	ret = of_address_to_resource(np, 0, &res);
	if (ret)
		goto end;

	cpic_reg = (void *)ioremap(res.start, res.end - res.start + 1);
	if (cpic_reg == NULL)
		goto end;

	sirq = irq_of_parse_and_map(np, 0);
	if (sirq == NO_IRQ)
		goto end;

	/* Initialize the CPM interrupt controller. */
	hwirq = (unsigned int)irq_map[sirq].hwirq;
	out_be32(&cpic_reg->cpic_cicr,
	    (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
		((hwirq/2) << 13) | CICR_HP_MASK);

	out_be32(&cpic_reg->cpic_cimr, 0);

	cpm_pic_node = of_node_get(np);

	cpm_pic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, 64, &cpm_pic_host_ops, 64);
	if (cpm_pic_host == NULL) {
		printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
		sirq = NO_IRQ;
		goto end;
	}
	of_node_put(np);

	/* Install our own error handler. */
	np = of_find_node_by_type(NULL, "cpm");
	if (np == NULL) {
		printk(KERN_ERR "CPM PIC init: can not find cpm node\n");
		goto end;
	}
	eirq= irq_of_parse_and_map(np, 0);
	if (eirq == NO_IRQ)
		goto end;

	if (setup_irq(eirq, &cpm_error_irqaction))
		printk(KERN_ERR "Could not allocate CPM error IRQ!");

	setbits32(&cpic_reg->cpic_cicr, CICR_IEN);

end:
	of_node_put(np);
	return sirq;
}

void cpm_reset(void)
{
	cpm8xx_t	*commproc;
	sysconf8xx_t    *siu_conf;

	commproc = (cpm8xx_t *)ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);

#ifdef CONFIG_UCODE_PATCH
	/* Perform a reset.
	*/
	out_be16(&commproc->cp_cpcr,  CPM_CR_RST | CPM_CR_FLG);

	/* Wait for it.
	*/
	while (in_be16(&commproc->cp_cpcr) & CPM_CR_FLG);

	cpm_load_patch(commproc);
#endif

	/* Set SDMA Bus Request priority 5.
	 * On 860T, this also enables FEC priority 6.  I am not sure
	 * this is what we realy want for some applications, but the
	 * manual recommends it.
	 * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
	 */
	siu_conf = (sysconf8xx_t*)immr_map(im_siu_conf);
	out_be32(&siu_conf->sc_sdcr, 1);
	immr_unmap(siu_conf);

	/* Reclaim the DP memory for our use. */
	m8xx_cpm_dpinit();

	/* Tell everyone where the comm processor resides.
	*/
	cpmp = commproc;
}

/* We used to do this earlier, but have to postpone as long as possible
 * to ensure the kernel VM is now running.
 */
static void
alloc_host_memory(void)
{
	dma_addr_t	physaddr;

	/* Set the host page for allocation.
	*/
	host_buffer = (uint)dma_alloc_coherent(NULL, PAGE_SIZE, &physaddr,
			GFP_KERNEL);
	host_end = host_buffer + PAGE_SIZE;
}

/* We also own one page of host buffer space for the allocation of
 * UART "fifos" and the like.
 */
uint
m8xx_cpm_hostalloc(uint size)
{
	uint	retloc;

	if (host_buffer == 0)
		alloc_host_memory();

	if ((host_buffer + size) >= host_end)
		return(0);

	retloc = host_buffer;
	host_buffer += size;

	return(retloc);
}

/* Set a baud rate generator.  This needs lots of work.  There are
 * four BRGs, any of which can be wired to any channel.
 * The internal baud rate clock is the system clock divided by 16.
 * This assumes the baudrate is 16x oversampled by the uart.
 */
#define BRG_INT_CLK		(get_brgfreq())
#define BRG_UART_CLK		(BRG_INT_CLK/16)
#define BRG_UART_CLK_DIV16	(BRG_UART_CLK/16)

void
cpm_setbrg(uint brg, uint rate)
{
	volatile uint	*bp;

	/* This is good enough to get SMCs running.....
	*/
	bp = (uint *)&cpmp->cp_brgc1;
	bp += brg;
	/* The BRG has a 12-bit counter.  For really slow baud rates (or
	 * really fast processors), we may have to further divide by 16.
	 */
	if (((BRG_UART_CLK / rate) - 1) < 4096)
		*bp = (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN;
	else
		*bp = (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
						CPM_BRG_EN | CPM_BRG_DIV16;
}

/*
 * dpalloc / dpfree bits.
 */
static spinlock_t cpm_dpmem_lock;
/*
 * 16 blocks should be enough to satisfy all requests
 * until the memory subsystem goes up...
 */
static rh_block_t cpm_boot_dpmem_rh_block[16];
static rh_info_t cpm_dpmem_info;

#define CPM_DPMEM_ALIGNMENT	8
static u8* dpram_vbase;
static uint dpram_pbase;

void m8xx_cpm_dpinit(void)
{
	spin_lock_init(&cpm_dpmem_lock);

	dpram_vbase = immr_map_size(im_cpm.cp_dpmem, CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE);
	dpram_pbase = (uint)&((immap_t *)IMAP_ADDR)->im_cpm.cp_dpmem;

	/* Initialize the info header */
	rh_init(&cpm_dpmem_info, CPM_DPMEM_ALIGNMENT,
			sizeof(cpm_boot_dpmem_rh_block) /
			sizeof(cpm_boot_dpmem_rh_block[0]),
			cpm_boot_dpmem_rh_block);

	/*
	 * Attach the usable dpmem area.
	 * XXX: This is actually crap.  CPM_DATAONLY_BASE and
	 * CPM_DATAONLY_SIZE are a subset of the available dparm.  It varies
	 * with the processor and the microcode patches applied / activated.
	 * But the following should be at least safe.
	 */
	rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
}

/*
 * Allocate the requested size worth of DP memory.
 * This function returns an offset into the DPRAM area.
 * Use cpm_dpram_addr() to get the virtual address of the area.
 */
unsigned long cpm_dpalloc(uint size, uint align)
{
	unsigned long start;
	unsigned long flags;

	spin_lock_irqsave(&cpm_dpmem_lock, flags);
	cpm_dpmem_info.alignment = align;
	start = rh_alloc(&cpm_dpmem_info, size, "commproc");
	spin_unlock_irqrestore(&cpm_dpmem_lock, flags);

	return (uint)start;
}
EXPORT_SYMBOL(cpm_dpalloc);

int cpm_dpfree(unsigned long offset)
{
	int ret;
	unsigned long flags;

	spin_lock_irqsave(&cpm_dpmem_lock, flags);
	ret = rh_free(&cpm_dpmem_info, offset);
	spin_unlock_irqrestore(&cpm_dpmem_lock, flags);

	return ret;
}
EXPORT_SYMBOL(cpm_dpfree);

unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
{
	unsigned long start;
	unsigned long flags;

	spin_lock_irqsave(&cpm_dpmem_lock, flags);
	cpm_dpmem_info.alignment = align;
	start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
	spin_unlock_irqrestore(&cpm_dpmem_lock, flags);

	return start;
}
EXPORT_SYMBOL(cpm_dpalloc_fixed);

void cpm_dpdump(void)
{
	rh_dump(&cpm_dpmem_info);
}
EXPORT_SYMBOL(cpm_dpdump);

void *cpm_dpram_addr(unsigned long offset)
{
	return (void *)(dpram_vbase + offset);
}
EXPORT_SYMBOL(cpm_dpram_addr);

uint cpm_dpram_phys(u8* addr)
{
	return (dpram_pbase + (uint)(addr - dpram_vbase));
}
EXPORT_SYMBOL(cpm_dpram_addr);
Commit	Line	Data
f2a0bd37 VB	1	/*
	2	* General Purpose functions for the global management of the
	3	* Communication Processor Module.
	4	* Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
	5	*
	6	* In addition to the individual control of the communication
	7	* channels, there are a few functions that globally affect the
	8	* communication processor.
	9	*
	10	* Buffer descriptors must be allocated from the dual ported memory
	11	* space. The allocator for that is here. When the communication
	12	* process is reset, we reclaim the memory available. There is
	13	* currently no deallocator for this memory.
	14	* The amount of space available is platform dependent. On the
	15	* MBX, the EPPC software loads additional microcode into the
	16	* communication processor, and uses some of the DP ram for this
	17	* purpose. Current, the first 512 bytes and the last 256 bytes of
	18	* memory are used. Right now I am conservative and only use the
	19	* memory that can never be used for microcode. If there are
	20	* applications that require more DP ram, we can expand the boundaries
	21	* but then we have to be careful of any downloaded microcode.
	22	*/
	23	#include <linux/errno.h>
	24	#include <linux/sched.h>
	25	#include <linux/kernel.h>
	26	#include <linux/dma-mapping.h>
	27	#include <linux/param.h>
	28	#include <linux/string.h>
	29	#include <linux/mm.h>
	30	#include <linux/interrupt.h>
	31	#include <linux/irq.h>
	32	#include <linux/module.h>
	33	#include <asm/mpc8xx.h>
	34	#include <asm/page.h>
	35	#include <asm/pgtable.h>
	36	#include <asm/8xx_immap.h>
	37	#include <asm/commproc.h>
	38	#include <asm/io.h>
	39	#include <asm/tlbflush.h>
	40	#include <asm/rheap.h>
	41	#include <asm/prom.h>
	42
	43	#include <asm/fs_pd.h>
	44
	45	#define CPM_MAP_SIZE (0x4000)
	46
	47	static void m8xx_cpm_dpinit(void);
	48	static uint host_buffer; /* One page of host buffer */
	49	static uint host_end; /* end + 1 */
	50	cpm8xx_t cpmp; / Pointer to comm processor space */
	51	cpic8xx_t *cpic_reg;
	52
	53	static struct device_node *cpm_pic_node;
	54	static struct irq_host *cpm_pic_host;
	55
	56	static void cpm_mask_irq(unsigned int irq)
	57	{
	58	unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
	59
	60	clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
	61	}
	62
	63	static void cpm_unmask_irq(unsigned int irq)
	64	{
65	unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
66
67	setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
68	}
69
70	static void cpm_end_irq(unsigned int irq)
71	{
72	unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
73
74	out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec));
75	}
76
77	static struct irq_chip cpm_pic = {
78	.typename = " CPM PIC ",
79	.mask = cpm_mask_irq,
80	.unmask = cpm_unmask_irq,
81	.eoi = cpm_end_irq,
82	};
83
84	int cpm_get_irq(void)
85	{
86	int cpm_vec;
87
88	/* Get the vector by setting the ACK bit and then reading
89	* the register.
90	*/
91	out_be16(&cpic_reg->cpic_civr, 1);
92	cpm_vec = in_be16(&cpic_reg->cpic_civr);
93	cpm_vec >>= 11;
94
95	return irq_linear_revmap(cpm_pic_host, cpm_vec);
96	}
97
98	static int cpm_pic_host_match(struct irq_host h, struct device_node node)
99	{
100	return cpm_pic_node == node;
101	}
102
103	static int cpm_pic_host_map(struct irq_host *h, unsigned int virq,
104	irq_hw_number_t hw)
105	{
106	pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
107
108	get_irq_desc(virq)->status \|= IRQ_LEVEL;
109	set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
110	return 0;
111	}
112
113	/* The CPM can generate the error interrupt when there is a race condition
114	* between generating and masking interrupts. All we have to do is ACK it
115	* and return. This is a no-op function so we don't need any special
116	* tests in the interrupt handler.
117	*/
118	static irqreturn_t cpm_error_interrupt(int irq, void *dev)
119	{
120	return IRQ_HANDLED;
121	}
122
123	static struct irqaction cpm_error_irqaction = {
124	.handler = cpm_error_interrupt,
125	.mask = CPU_MASK_NONE,
126	.name = "error",
127	};
128
129	static struct irq_host_ops cpm_pic_host_ops = {
130	.match = cpm_pic_host_match,
131	.map = cpm_pic_host_map,
132	};
133
134	unsigned int cpm_pic_init(void)
135	{
136	struct device_node *np = NULL;
137	struct resource res;
138	unsigned int sirq = NO_IRQ, hwirq, eirq;
139	int ret;
140
141	pr_debug("cpm_pic_init\n");
142
143	np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
144	if (np == NULL) {
145	printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");
146	return sirq;
147	}
148	ret = of_address_to_resource(np, 0, &res);
149	if (ret)
150	goto end;
151
152	cpic_reg = (void *)ioremap(res.start, res.end - res.start + 1);
153	if (cpic_reg == NULL)
154	goto end;
155
156	sirq = irq_of_parse_and_map(np, 0);
157	if (sirq == NO_IRQ)
158	goto end;
159
160	/* Initialize the CPM interrupt controller. */
161	hwirq = (unsigned int)irq_map[sirq].hwirq;
162	out_be32(&cpic_reg->cpic_cicr,
163	(CICR_SCD_SCC4 \| CICR_SCC_SCC3 \| CICR_SCB_SCC2 \| CICR_SCA_SCC1) \|
164	((hwirq/2) << 13) \| CICR_HP_MASK);
165
166	out_be32(&cpic_reg->cpic_cimr, 0);
167
168	cpm_pic_node = of_node_get(np);
169
170	cpm_pic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, 64, &cpm_pic_host_ops, 64);
171	if (cpm_pic_host == NULL) {
172	printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
173	sirq = NO_IRQ;
174	goto end;
175	}
176	of_node_put(np);
177
178	/* Install our own error handler. */
179	np = of_find_node_by_type(NULL, "cpm");
180	if (np == NULL) {
181	printk(KERN_ERR "CPM PIC init: can not find cpm node\n");
182	goto end;
183	}
184	eirq= irq_of_parse_and_map(np, 0);
185	if (eirq == NO_IRQ)
186	goto end;
187
188	if (setup_irq(eirq, &cpm_error_irqaction))
189	printk(KERN_ERR "Could not allocate CPM error IRQ!");
190
191	setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
192
193	end:
194	of_node_put(np);
195	return sirq;
196	}
197
198	void cpm_reset(void)
199	{
200	cpm8xx_t *commproc;
201	sysconf8xx_t *siu_conf;
202
203	commproc = (cpm8xx_t *)ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
204
205	#ifdef CONFIG_UCODE_PATCH
206	/* Perform a reset.
207	*/
208	out_be16(&commproc->cp_cpcr, CPM_CR_RST \| CPM_CR_FLG);
209
210	/* Wait for it.
211	*/
212	while (in_be16(&commproc->cp_cpcr) & CPM_CR_FLG);
213
214	cpm_load_patch(commproc);
215	#endif
216
217	/* Set SDMA Bus Request priority 5.
218	* On 860T, this also enables FEC priority 6. I am not sure
219	* this is what we realy want for some applications, but the
220	* manual recommends it.
221	* Bit 25, FAM can also be set to use FEC aggressive mode (860T).
222	*/
223	siu_conf = (sysconf8xx_t*)immr_map(im_siu_conf);
224	out_be32(&siu_conf->sc_sdcr, 1);
225	immr_unmap(siu_conf);
226
227	/* Reclaim the DP memory for our use. */
228	m8xx_cpm_dpinit();
229
230	/* Tell everyone where the comm processor resides.
231	*/
232	cpmp = commproc;
233	}
234
235	/* We used to do this earlier, but have to postpone as long as possible
236	* to ensure the kernel VM is now running.
237	*/
238	static void
239	alloc_host_memory(void)
240	{
241	dma_addr_t physaddr;
242
243	/* Set the host page for allocation.
244	*/
245	host_buffer = (uint)dma_alloc_coherent(NULL, PAGE_SIZE, &physaddr,
246	GFP_KERNEL);
247	host_end = host_buffer + PAGE_SIZE;
248	}
249
250	/* We also own one page of host buffer space for the allocation of
251	* UART "fifos" and the like.
252	*/
253	uint
254	m8xx_cpm_hostalloc(uint size)
255	{
256	uint retloc;
257
258	if (host_buffer == 0)
259	alloc_host_memory();
260
261	if ((host_buffer + size) >= host_end)
262	return(0);
263
264	retloc = host_buffer;
265	host_buffer += size;
266
267	return(retloc);
268	}
269
270	/* Set a baud rate generator. This needs lots of work. There are
271	* four BRGs, any of which can be wired to any channel.
272	* The internal baud rate clock is the system clock divided by 16.
273	* This assumes the baudrate is 16x oversampled by the uart.
274	*/
275	#define BRG_INT_CLK (get_brgfreq())
276	#define BRG_UART_CLK (BRG_INT_CLK/16)
277	#define BRG_UART_CLK_DIV16 (BRG_UART_CLK/16)
278
279	void
280	cpm_setbrg(uint brg, uint rate)
281	{
282	volatile uint *bp;
283
284	/* This is good enough to get SMCs running.....
285	*/
286	bp = (uint *)&cpmp->cp_brgc1;
287	bp += brg;
288	/* The BRG has a 12-bit counter. For really slow baud rates (or
289	* really fast processors), we may have to further divide by 16.
290	*/
291	if (((BRG_UART_CLK / rate) - 1) < 4096)
292	*bp = (((BRG_UART_CLK / rate) - 1) << 1) \| CPM_BRG_EN;
293	else
294	*bp = (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) \|
295	CPM_BRG_EN \| CPM_BRG_DIV16;
296	}
297
298	/*
299	* dpalloc / dpfree bits.
300	*/
301	static spinlock_t cpm_dpmem_lock;
302	/*
303	* 16 blocks should be enough to satisfy all requests
304	* until the memory subsystem goes up...
305	*/
306	static rh_block_t cpm_boot_dpmem_rh_block[16];
307	static rh_info_t cpm_dpmem_info;
308
309	#define CPM_DPMEM_ALIGNMENT 8
310	static u8* dpram_vbase;
311	static uint dpram_pbase;
312
313	void m8xx_cpm_dpinit(void)
314	{
315	spin_lock_init(&cpm_dpmem_lock);
316
317	dpram_vbase = immr_map_size(im_cpm.cp_dpmem, CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE);
318	dpram_pbase = (uint)&((immap_t *)IMAP_ADDR)->im_cpm.cp_dpmem;
319
320	/* Initialize the info header */
321	rh_init(&cpm_dpmem_info, CPM_DPMEM_ALIGNMENT,
322	sizeof(cpm_boot_dpmem_rh_block) /
323	sizeof(cpm_boot_dpmem_rh_block[0]),
324	cpm_boot_dpmem_rh_block);
325
326	/*
327	* Attach the usable dpmem area.
328	* XXX: This is actually crap. CPM_DATAONLY_BASE and
329	* CPM_DATAONLY_SIZE are a subset of the available dparm. It varies
330	* with the processor and the microcode patches applied / activated.
331	* But the following should be at least safe.
332	*/
4c35630c	333	rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
f2a0bd37 VB	334	}
	335
	336	/*
	337	* Allocate the requested size worth of DP memory.
	338	* This function returns an offset into the DPRAM area.
	339	* Use cpm_dpram_addr() to get the virtual address of the area.
	340	*/
4c35630c	341	unsigned long cpm_dpalloc(uint size, uint align)
f2a0bd37	342	{
4c35630c	343	unsigned long start;
f2a0bd37 VB	344	unsigned long flags;
	345
	346	spin_lock_irqsave(&cpm_dpmem_lock, flags);
	347	cpm_dpmem_info.alignment = align;
	348	start = rh_alloc(&cpm_dpmem_info, size, "commproc");
	349	spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
	350
	351	return (uint)start;
	352	}
	353	EXPORT_SYMBOL(cpm_dpalloc);
	354
4c35630c	355	int cpm_dpfree(unsigned long offset)
f2a0bd37 VB	356	{
	357	int ret;
	358	unsigned long flags;
	359
	360	spin_lock_irqsave(&cpm_dpmem_lock, flags);
4c35630c	361	ret = rh_free(&cpm_dpmem_info, offset);
f2a0bd37 VB	362	spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
	363
	364	return ret;
	365	}
	366	EXPORT_SYMBOL(cpm_dpfree);
	367
4c35630c	368	unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
f2a0bd37	369	{
4c35630c	370	unsigned long start;
f2a0bd37 VB	371	unsigned long flags;
	372
	373	spin_lock_irqsave(&cpm_dpmem_lock, flags);
	374	cpm_dpmem_info.alignment = align;
4c35630c	375	start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
f2a0bd37 VB	376	spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
f2a0bd37 VB	377
4c35630c	378	return start;
f2a0bd37 VB	379	}
	380	EXPORT_SYMBOL(cpm_dpalloc_fixed);
	381
	382	void cpm_dpdump(void)
	383	{
	384	rh_dump(&cpm_dpmem_info);
	385	}
	386	EXPORT_SYMBOL(cpm_dpdump);
	387
4c35630c	388	void *cpm_dpram_addr(unsigned long offset)
f2a0bd37 VB	389	{
	390	return (void *)(dpram_vbase + offset);
	391	}
	392	EXPORT_SYMBOL(cpm_dpram_addr);
	393
	394	uint cpm_dpram_phys(u8* addr)
	395	{
	396	return (dpram_pbase + (uint)(addr - dpram_vbase));
	397	}
	398	EXPORT_SYMBOL(cpm_dpram_addr);