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Commit | Line | Data |
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007e8f51 DG |
1 | /* |
2 | * arch/powerpc/platforms/pseries/xics.c | |
1da177e4 LT |
3 | * |
4 | * Copyright 2000 IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/types.h> |
12 | #include <linux/threads.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/irq.h> | |
15 | #include <linux/smp.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/signal.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/gfp.h> | |
20 | #include <linux/radix-tree.h> | |
21 | #include <linux/cpu.h> | |
57cfb814 | 22 | #include <asm/firmware.h> |
1da177e4 LT |
23 | #include <asm/prom.h> |
24 | #include <asm/io.h> | |
25 | #include <asm/pgtable.h> | |
26 | #include <asm/smp.h> | |
27 | #include <asm/rtas.h> | |
1da177e4 LT |
28 | #include <asm/hvcall.h> |
29 | #include <asm/machdep.h> | |
2227718c | 30 | #include <asm/i8259.h> |
1da177e4 | 31 | |
007e8f51 DG |
32 | #include "xics.h" |
33 | ||
1da177e4 LT |
34 | static unsigned int xics_startup(unsigned int irq); |
35 | static void xics_enable_irq(unsigned int irq); | |
36 | static void xics_disable_irq(unsigned int irq); | |
37 | static void xics_mask_and_ack_irq(unsigned int irq); | |
38 | static void xics_end_irq(unsigned int irq); | |
39 | static void xics_set_affinity(unsigned int irq_nr, cpumask_t cpumask); | |
40 | ||
26370322 | 41 | static struct hw_interrupt_type xics_pic = { |
1da177e4 LT |
42 | .typename = " XICS ", |
43 | .startup = xics_startup, | |
44 | .enable = xics_enable_irq, | |
45 | .disable = xics_disable_irq, | |
46 | .ack = xics_mask_and_ack_irq, | |
47 | .end = xics_end_irq, | |
48 | .set_affinity = xics_set_affinity | |
49 | }; | |
50 | ||
1da177e4 LT |
51 | /* This is used to map real irq numbers to virtual */ |
52 | static struct radix_tree_root irq_map = RADIX_TREE_INIT(GFP_ATOMIC); | |
53 | ||
54 | #define XICS_IPI 2 | |
55 | #define XICS_IRQ_SPURIOUS 0 | |
56 | ||
57 | /* Want a priority other than 0. Various HW issues require this. */ | |
58 | #define DEFAULT_PRIORITY 5 | |
59 | ||
007e8f51 | 60 | /* |
1da177e4 LT |
61 | * Mark IPIs as higher priority so we can take them inside interrupts that |
62 | * arent marked SA_INTERRUPT | |
63 | */ | |
64 | #define IPI_PRIORITY 4 | |
65 | ||
66 | struct xics_ipl { | |
67 | union { | |
68 | u32 word; | |
69 | u8 bytes[4]; | |
70 | } xirr_poll; | |
71 | union { | |
72 | u32 word; | |
73 | u8 bytes[4]; | |
74 | } xirr; | |
75 | u32 dummy; | |
76 | union { | |
77 | u32 word; | |
78 | u8 bytes[4]; | |
79 | } qirr; | |
80 | }; | |
81 | ||
82 | static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS]; | |
83 | ||
84 | static int xics_irq_8259_cascade = 0; | |
85 | static int xics_irq_8259_cascade_real = 0; | |
86 | static unsigned int default_server = 0xFF; | |
26370322 AB |
87 | static unsigned int default_distrib_server = 0; |
88 | static unsigned int interrupt_server_size = 8; | |
1da177e4 LT |
89 | |
90 | /* | |
91 | * XICS only has a single IPI, so encode the messages per CPU | |
92 | */ | |
93 | struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned; | |
94 | ||
95 | /* RTAS service tokens */ | |
26370322 AB |
96 | static int ibm_get_xive; |
97 | static int ibm_set_xive; | |
98 | static int ibm_int_on; | |
99 | static int ibm_int_off; | |
1da177e4 LT |
100 | |
101 | typedef struct { | |
102 | int (*xirr_info_get)(int cpu); | |
103 | void (*xirr_info_set)(int cpu, int val); | |
104 | void (*cppr_info)(int cpu, u8 val); | |
105 | void (*qirr_info)(int cpu, u8 val); | |
106 | } xics_ops; | |
107 | ||
108 | ||
109 | /* SMP */ | |
110 | ||
111 | static int pSeries_xirr_info_get(int n_cpu) | |
112 | { | |
113 | return in_be32(&xics_per_cpu[n_cpu]->xirr.word); | |
114 | } | |
115 | ||
116 | static void pSeries_xirr_info_set(int n_cpu, int value) | |
117 | { | |
118 | out_be32(&xics_per_cpu[n_cpu]->xirr.word, value); | |
119 | } | |
120 | ||
121 | static void pSeries_cppr_info(int n_cpu, u8 value) | |
122 | { | |
123 | out_8(&xics_per_cpu[n_cpu]->xirr.bytes[0], value); | |
124 | } | |
125 | ||
126 | static void pSeries_qirr_info(int n_cpu, u8 value) | |
127 | { | |
128 | out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value); | |
129 | } | |
130 | ||
131 | static xics_ops pSeries_ops = { | |
132 | pSeries_xirr_info_get, | |
133 | pSeries_xirr_info_set, | |
134 | pSeries_cppr_info, | |
135 | pSeries_qirr_info | |
136 | }; | |
137 | ||
138 | static xics_ops *ops = &pSeries_ops; | |
139 | ||
140 | ||
141 | /* LPAR */ | |
142 | ||
143 | static inline long plpar_eoi(unsigned long xirr) | |
144 | { | |
145 | return plpar_hcall_norets(H_EOI, xirr); | |
146 | } | |
147 | ||
148 | static inline long plpar_cppr(unsigned long cppr) | |
149 | { | |
150 | return plpar_hcall_norets(H_CPPR, cppr); | |
151 | } | |
152 | ||
153 | static inline long plpar_ipi(unsigned long servernum, unsigned long mfrr) | |
154 | { | |
155 | return plpar_hcall_norets(H_IPI, servernum, mfrr); | |
156 | } | |
157 | ||
158 | static inline long plpar_xirr(unsigned long *xirr_ret) | |
159 | { | |
160 | unsigned long dummy; | |
161 | return plpar_hcall(H_XIRR, 0, 0, 0, 0, xirr_ret, &dummy, &dummy); | |
162 | } | |
163 | ||
164 | static int pSeriesLP_xirr_info_get(int n_cpu) | |
165 | { | |
166 | unsigned long lpar_rc; | |
007e8f51 | 167 | unsigned long return_value; |
1da177e4 LT |
168 | |
169 | lpar_rc = plpar_xirr(&return_value); | |
706c8c93 | 170 | if (lpar_rc != H_SUCCESS) |
007e8f51 | 171 | panic(" bad return code xirr - rc = %lx \n", lpar_rc); |
1da177e4 LT |
172 | return (int)return_value; |
173 | } | |
174 | ||
175 | static void pSeriesLP_xirr_info_set(int n_cpu, int value) | |
176 | { | |
177 | unsigned long lpar_rc; | |
178 | unsigned long val64 = value & 0xffffffff; | |
179 | ||
180 | lpar_rc = plpar_eoi(val64); | |
706c8c93 | 181 | if (lpar_rc != H_SUCCESS) |
1da177e4 | 182 | panic("bad return code EOI - rc = %ld, value=%lx\n", lpar_rc, |
007e8f51 | 183 | val64); |
1da177e4 LT |
184 | } |
185 | ||
186 | void pSeriesLP_cppr_info(int n_cpu, u8 value) | |
187 | { | |
188 | unsigned long lpar_rc; | |
189 | ||
190 | lpar_rc = plpar_cppr(value); | |
706c8c93 | 191 | if (lpar_rc != H_SUCCESS) |
007e8f51 | 192 | panic("bad return code cppr - rc = %lx\n", lpar_rc); |
1da177e4 LT |
193 | } |
194 | ||
195 | static void pSeriesLP_qirr_info(int n_cpu , u8 value) | |
196 | { | |
197 | unsigned long lpar_rc; | |
198 | ||
199 | lpar_rc = plpar_ipi(get_hard_smp_processor_id(n_cpu), value); | |
706c8c93 | 200 | if (lpar_rc != H_SUCCESS) |
007e8f51 | 201 | panic("bad return code qirr - rc = %lx\n", lpar_rc); |
1da177e4 LT |
202 | } |
203 | ||
204 | xics_ops pSeriesLP_ops = { | |
205 | pSeriesLP_xirr_info_get, | |
206 | pSeriesLP_xirr_info_set, | |
207 | pSeriesLP_cppr_info, | |
208 | pSeriesLP_qirr_info | |
209 | }; | |
210 | ||
211 | static unsigned int xics_startup(unsigned int virq) | |
212 | { | |
213 | unsigned int irq; | |
214 | ||
215 | irq = irq_offset_down(virq); | |
216 | if (radix_tree_insert(&irq_map, virt_irq_to_real(irq), | |
217 | &virt_irq_to_real_map[irq]) == -ENOMEM) | |
218 | printk(KERN_CRIT "Out of memory creating real -> virtual" | |
219 | " IRQ mapping for irq %u (real 0x%x)\n", | |
220 | virq, virt_irq_to_real(irq)); | |
221 | xics_enable_irq(virq); | |
222 | return 0; /* return value is ignored */ | |
223 | } | |
224 | ||
225 | static unsigned int real_irq_to_virt(unsigned int real_irq) | |
226 | { | |
227 | unsigned int *ptr; | |
228 | ||
229 | ptr = radix_tree_lookup(&irq_map, real_irq); | |
230 | if (ptr == NULL) | |
231 | return NO_IRQ; | |
232 | return ptr - virt_irq_to_real_map; | |
233 | } | |
234 | ||
235 | #ifdef CONFIG_SMP | |
236 | static int get_irq_server(unsigned int irq) | |
237 | { | |
238 | unsigned int server; | |
239 | /* For the moment only implement delivery to all cpus or one cpu */ | |
a53da52f | 240 | cpumask_t cpumask = irq_desc[irq].affinity; |
1da177e4 LT |
241 | cpumask_t tmp = CPU_MASK_NONE; |
242 | ||
243 | if (!distribute_irqs) | |
244 | return default_server; | |
245 | ||
246 | if (cpus_equal(cpumask, CPU_MASK_ALL)) { | |
247 | server = default_distrib_server; | |
248 | } else { | |
249 | cpus_and(tmp, cpu_online_map, cpumask); | |
250 | ||
251 | if (cpus_empty(tmp)) | |
252 | server = default_distrib_server; | |
253 | else | |
254 | server = get_hard_smp_processor_id(first_cpu(tmp)); | |
255 | } | |
256 | ||
257 | return server; | |
258 | ||
259 | } | |
260 | #else | |
261 | static int get_irq_server(unsigned int irq) | |
262 | { | |
263 | return default_server; | |
264 | } | |
265 | #endif | |
266 | ||
267 | static void xics_enable_irq(unsigned int virq) | |
268 | { | |
269 | unsigned int irq; | |
270 | int call_status; | |
271 | unsigned int server; | |
272 | ||
273 | irq = virt_irq_to_real(irq_offset_down(virq)); | |
274 | if (irq == XICS_IPI) | |
275 | return; | |
276 | ||
277 | server = get_irq_server(virq); | |
278 | call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server, | |
279 | DEFAULT_PRIORITY); | |
280 | if (call_status != 0) { | |
26370322 AB |
281 | printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_set_xive " |
282 | "returned %d\n", irq, call_status); | |
283 | printk("set_xive %x, server %x\n", ibm_set_xive, server); | |
1da177e4 LT |
284 | return; |
285 | } | |
286 | ||
287 | /* Now unmask the interrupt (often a no-op) */ | |
288 | call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq); | |
289 | if (call_status != 0) { | |
26370322 AB |
290 | printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_int_on " |
291 | "returned %d\n", irq, call_status); | |
1da177e4 LT |
292 | return; |
293 | } | |
294 | } | |
295 | ||
296 | static void xics_disable_real_irq(unsigned int irq) | |
297 | { | |
298 | int call_status; | |
299 | unsigned int server; | |
300 | ||
301 | if (irq == XICS_IPI) | |
302 | return; | |
303 | ||
304 | call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq); | |
305 | if (call_status != 0) { | |
26370322 AB |
306 | printk(KERN_ERR "xics_disable_real_irq: irq=%u: " |
307 | "ibm_int_off returned %d\n", irq, call_status); | |
1da177e4 LT |
308 | return; |
309 | } | |
310 | ||
311 | server = get_irq_server(irq); | |
312 | /* Have to set XIVE to 0xff to be able to remove a slot */ | |
313 | call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server, 0xff); | |
314 | if (call_status != 0) { | |
26370322 AB |
315 | printk(KERN_ERR "xics_disable_irq: irq=%u: ibm_set_xive(0xff)" |
316 | " returned %d\n", irq, call_status); | |
1da177e4 LT |
317 | return; |
318 | } | |
319 | } | |
320 | ||
321 | static void xics_disable_irq(unsigned int virq) | |
322 | { | |
323 | unsigned int irq; | |
324 | ||
325 | irq = virt_irq_to_real(irq_offset_down(virq)); | |
326 | xics_disable_real_irq(irq); | |
327 | } | |
328 | ||
329 | static void xics_end_irq(unsigned int irq) | |
330 | { | |
331 | int cpu = smp_processor_id(); | |
332 | ||
333 | iosync(); | |
334 | ops->xirr_info_set(cpu, ((0xff << 24) | | |
335 | (virt_irq_to_real(irq_offset_down(irq))))); | |
336 | ||
337 | } | |
338 | ||
339 | static void xics_mask_and_ack_irq(unsigned int irq) | |
340 | { | |
341 | int cpu = smp_processor_id(); | |
342 | ||
343 | if (irq < irq_offset_value()) { | |
344 | i8259_pic.ack(irq); | |
345 | iosync(); | |
346 | ops->xirr_info_set(cpu, ((0xff<<24) | | |
347 | xics_irq_8259_cascade_real)); | |
348 | iosync(); | |
349 | } | |
350 | } | |
351 | ||
352 | int xics_get_irq(struct pt_regs *regs) | |
353 | { | |
354 | unsigned int cpu = smp_processor_id(); | |
355 | unsigned int vec; | |
356 | int irq; | |
357 | ||
358 | vec = ops->xirr_info_get(cpu); | |
359 | /* (vec >> 24) == old priority */ | |
360 | vec &= 0x00ffffff; | |
361 | ||
362 | /* for sanity, this had better be < NR_IRQS - 16 */ | |
363 | if (vec == xics_irq_8259_cascade_real) { | |
2227718c | 364 | irq = i8259_irq(regs); |
8b1af56b | 365 | xics_end_irq(irq_offset_up(xics_irq_8259_cascade)); |
1da177e4 LT |
366 | } else if (vec == XICS_IRQ_SPURIOUS) { |
367 | irq = -1; | |
368 | } else { | |
369 | irq = real_irq_to_virt(vec); | |
370 | if (irq == NO_IRQ) | |
371 | irq = real_irq_to_virt_slowpath(vec); | |
372 | if (irq == NO_IRQ) { | |
26370322 | 373 | printk(KERN_ERR "Interrupt %u (real) is invalid," |
1da177e4 LT |
374 | " disabling it.\n", vec); |
375 | xics_disable_real_irq(vec); | |
376 | } else | |
377 | irq = irq_offset_up(irq); | |
378 | } | |
379 | return irq; | |
380 | } | |
381 | ||
382 | #ifdef CONFIG_SMP | |
383 | ||
8446196a | 384 | static irqreturn_t xics_ipi_action(int irq, void *dev_id, struct pt_regs *regs) |
1da177e4 LT |
385 | { |
386 | int cpu = smp_processor_id(); | |
387 | ||
388 | ops->qirr_info(cpu, 0xff); | |
389 | ||
390 | WARN_ON(cpu_is_offline(cpu)); | |
391 | ||
392 | while (xics_ipi_message[cpu].value) { | |
393 | if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION, | |
394 | &xics_ipi_message[cpu].value)) { | |
395 | mb(); | |
396 | smp_message_recv(PPC_MSG_CALL_FUNCTION, regs); | |
397 | } | |
398 | if (test_and_clear_bit(PPC_MSG_RESCHEDULE, | |
399 | &xics_ipi_message[cpu].value)) { | |
400 | mb(); | |
401 | smp_message_recv(PPC_MSG_RESCHEDULE, regs); | |
402 | } | |
403 | #if 0 | |
404 | if (test_and_clear_bit(PPC_MSG_MIGRATE_TASK, | |
405 | &xics_ipi_message[cpu].value)) { | |
406 | mb(); | |
407 | smp_message_recv(PPC_MSG_MIGRATE_TASK, regs); | |
408 | } | |
409 | #endif | |
cc532915 | 410 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) |
1da177e4 LT |
411 | if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK, |
412 | &xics_ipi_message[cpu].value)) { | |
413 | mb(); | |
414 | smp_message_recv(PPC_MSG_DEBUGGER_BREAK, regs); | |
415 | } | |
416 | #endif | |
417 | } | |
418 | return IRQ_HANDLED; | |
419 | } | |
420 | ||
421 | void xics_cause_IPI(int cpu) | |
422 | { | |
423 | ops->qirr_info(cpu, IPI_PRIORITY); | |
424 | } | |
6c80a21c | 425 | #endif /* CONFIG_SMP */ |
1da177e4 LT |
426 | |
427 | void xics_setup_cpu(void) | |
428 | { | |
429 | int cpu = smp_processor_id(); | |
430 | ||
431 | ops->cppr_info(cpu, 0xff); | |
432 | iosync(); | |
1da177e4 | 433 | |
6c80a21c PM |
434 | /* |
435 | * Put the calling processor into the GIQ. This is really only | |
436 | * necessary from a secondary thread as the OF start-cpu interface | |
437 | * performs this function for us on primary threads. | |
438 | * | |
439 | * XXX: undo of teardown on kexec needs this too, as may hotplug | |
440 | */ | |
441 | rtas_set_indicator(GLOBAL_INTERRUPT_QUEUE, | |
442 | (1UL << interrupt_server_size) - 1 - default_distrib_server, 1); | |
443 | } | |
1da177e4 LT |
444 | |
445 | void xics_init_IRQ(void) | |
446 | { | |
447 | int i; | |
448 | unsigned long intr_size = 0; | |
449 | struct device_node *np; | |
450 | uint *ireg, ilen, indx = 0; | |
451 | unsigned long intr_base = 0; | |
452 | struct xics_interrupt_node { | |
453 | unsigned long addr; | |
454 | unsigned long size; | |
007e8f51 | 455 | } intnodes[NR_CPUS]; |
1da177e4 LT |
456 | |
457 | ppc64_boot_msg(0x20, "XICS Init"); | |
458 | ||
459 | ibm_get_xive = rtas_token("ibm,get-xive"); | |
460 | ibm_set_xive = rtas_token("ibm,set-xive"); | |
461 | ibm_int_on = rtas_token("ibm,int-on"); | |
462 | ibm_int_off = rtas_token("ibm,int-off"); | |
463 | ||
464 | np = of_find_node_by_type(NULL, "PowerPC-External-Interrupt-Presentation"); | |
465 | if (!np) | |
466 | panic("xics_init_IRQ: can't find interrupt presentation"); | |
467 | ||
468 | nextnode: | |
469 | ireg = (uint *)get_property(np, "ibm,interrupt-server-ranges", NULL); | |
470 | if (ireg) { | |
471 | /* | |
472 | * set node starting index for this node | |
473 | */ | |
474 | indx = *ireg; | |
475 | } | |
476 | ||
477 | ireg = (uint *)get_property(np, "reg", &ilen); | |
478 | if (!ireg) | |
479 | panic("xics_init_IRQ: can't find interrupt reg property"); | |
007e8f51 | 480 | |
1da177e4 LT |
481 | while (ilen) { |
482 | intnodes[indx].addr = (unsigned long)*ireg++ << 32; | |
483 | ilen -= sizeof(uint); | |
484 | intnodes[indx].addr |= *ireg++; | |
485 | ilen -= sizeof(uint); | |
486 | intnodes[indx].size = (unsigned long)*ireg++ << 32; | |
487 | ilen -= sizeof(uint); | |
488 | intnodes[indx].size |= *ireg++; | |
489 | ilen -= sizeof(uint); | |
490 | indx++; | |
491 | if (indx >= NR_CPUS) break; | |
492 | } | |
493 | ||
494 | np = of_find_node_by_type(np, "PowerPC-External-Interrupt-Presentation"); | |
495 | if ((indx < NR_CPUS) && np) goto nextnode; | |
496 | ||
497 | /* Find the server numbers for the boot cpu. */ | |
498 | for (np = of_find_node_by_type(NULL, "cpu"); | |
499 | np; | |
500 | np = of_find_node_by_type(np, "cpu")) { | |
501 | ireg = (uint *)get_property(np, "reg", &ilen); | |
4df20460 | 502 | if (ireg && ireg[0] == get_hard_smp_processor_id(boot_cpuid)) { |
1da177e4 LT |
503 | ireg = (uint *)get_property(np, "ibm,ppc-interrupt-gserver#s", |
504 | &ilen); | |
505 | i = ilen / sizeof(int); | |
506 | if (ireg && i > 0) { | |
507 | default_server = ireg[0]; | |
508 | default_distrib_server = ireg[i-1]; /* take last element */ | |
509 | } | |
510 | ireg = (uint *)get_property(np, | |
511 | "ibm,interrupt-server#-size", NULL); | |
512 | if (ireg) | |
513 | interrupt_server_size = *ireg; | |
514 | break; | |
515 | } | |
516 | } | |
517 | of_node_put(np); | |
518 | ||
519 | intr_base = intnodes[0].addr; | |
520 | intr_size = intnodes[0].size; | |
521 | ||
522 | np = of_find_node_by_type(NULL, "interrupt-controller"); | |
523 | if (!np) { | |
cc98f705 | 524 | printk(KERN_DEBUG "xics: no ISA interrupt controller\n"); |
1da177e4 LT |
525 | xics_irq_8259_cascade_real = -1; |
526 | xics_irq_8259_cascade = -1; | |
527 | } else { | |
528 | ireg = (uint *) get_property(np, "interrupts", NULL); | |
529 | if (!ireg) | |
530 | panic("xics_init_IRQ: can't find ISA interrupts property"); | |
531 | ||
532 | xics_irq_8259_cascade_real = *ireg; | |
533 | xics_irq_8259_cascade | |
534 | = virt_irq_create_mapping(xics_irq_8259_cascade_real); | |
8b1af56b | 535 | i8259_init(0, 0); |
1da177e4 LT |
536 | of_node_put(np); |
537 | } | |
538 | ||
57cfb814 | 539 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
799d6046 PM |
540 | ops = &pSeriesLP_ops; |
541 | else { | |
1da177e4 | 542 | #ifdef CONFIG_SMP |
0e551954 | 543 | for_each_possible_cpu(i) { |
1da177e4 LT |
544 | int hard_id; |
545 | ||
546 | /* FIXME: Do this dynamically! --RR */ | |
547 | if (!cpu_present(i)) | |
548 | continue; | |
549 | ||
550 | hard_id = get_hard_smp_processor_id(i); | |
007e8f51 | 551 | xics_per_cpu[i] = ioremap(intnodes[hard_id].addr, |
1da177e4 LT |
552 | intnodes[hard_id].size); |
553 | } | |
554 | #else | |
555 | xics_per_cpu[0] = ioremap(intr_base, intr_size); | |
556 | #endif /* CONFIG_SMP */ | |
1da177e4 LT |
557 | } |
558 | ||
8b1af56b | 559 | for (i = irq_offset_value(); i < NR_IRQS; ++i) |
d1bef4ed | 560 | get_irq_desc(i)->chip = &xics_pic; |
1da177e4 | 561 | |
6c80a21c | 562 | xics_setup_cpu(); |
1da177e4 LT |
563 | |
564 | ppc64_boot_msg(0x21, "XICS Done"); | |
565 | } | |
566 | ||
567 | /* | |
568 | * We cant do this in init_IRQ because we need the memory subsystem up for | |
569 | * request_irq() | |
570 | */ | |
571 | static int __init xics_setup_i8259(void) | |
572 | { | |
573 | if (ppc64_interrupt_controller == IC_PPC_XIC && | |
574 | xics_irq_8259_cascade != -1) { | |
575 | if (request_irq(irq_offset_up(xics_irq_8259_cascade), | |
576 | no_action, 0, "8259 cascade", NULL)) | |
577 | printk(KERN_ERR "xics_setup_i8259: couldn't get 8259 " | |
578 | "cascade\n"); | |
1da177e4 LT |
579 | } |
580 | return 0; | |
581 | } | |
582 | arch_initcall(xics_setup_i8259); | |
583 | ||
584 | #ifdef CONFIG_SMP | |
585 | void xics_request_IPIs(void) | |
586 | { | |
587 | virt_irq_to_real_map[XICS_IPI] = XICS_IPI; | |
588 | ||
589 | /* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */ | |
590 | request_irq(irq_offset_up(XICS_IPI), xics_ipi_action, SA_INTERRUPT, | |
591 | "IPI", NULL); | |
592 | get_irq_desc(irq_offset_up(XICS_IPI))->status |= IRQ_PER_CPU; | |
593 | } | |
594 | #endif | |
595 | ||
596 | static void xics_set_affinity(unsigned int virq, cpumask_t cpumask) | |
597 | { | |
598 | unsigned int irq; | |
599 | int status; | |
600 | int xics_status[2]; | |
601 | unsigned long newmask; | |
602 | cpumask_t tmp = CPU_MASK_NONE; | |
603 | ||
604 | irq = virt_irq_to_real(irq_offset_down(virq)); | |
605 | if (irq == XICS_IPI || irq == NO_IRQ) | |
606 | return; | |
607 | ||
608 | status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq); | |
609 | ||
610 | if (status) { | |
26370322 | 611 | printk(KERN_ERR "xics_set_affinity: irq=%u ibm,get-xive " |
1da177e4 LT |
612 | "returns %d\n", irq, status); |
613 | return; | |
614 | } | |
615 | ||
616 | /* For the moment only implement delivery to all cpus or one cpu */ | |
617 | if (cpus_equal(cpumask, CPU_MASK_ALL)) { | |
618 | newmask = default_distrib_server; | |
619 | } else { | |
620 | cpus_and(tmp, cpu_online_map, cpumask); | |
621 | if (cpus_empty(tmp)) | |
622 | return; | |
623 | newmask = get_hard_smp_processor_id(first_cpu(tmp)); | |
624 | } | |
625 | ||
626 | status = rtas_call(ibm_set_xive, 3, 1, NULL, | |
627 | irq, newmask, xics_status[1]); | |
628 | ||
629 | if (status) { | |
26370322 | 630 | printk(KERN_ERR "xics_set_affinity: irq=%u ibm,set-xive " |
1da177e4 LT |
631 | "returns %d\n", irq, status); |
632 | return; | |
633 | } | |
634 | } | |
635 | ||
6d22d85a | 636 | void xics_teardown_cpu(int secondary) |
fce0d574 S |
637 | { |
638 | int cpu = smp_processor_id(); | |
fce0d574 S |
639 | |
640 | ops->cppr_info(cpu, 0x00); | |
641 | iosync(); | |
642 | ||
81bbbe92 HM |
643 | /* Clear IPI */ |
644 | ops->qirr_info(cpu, 0xff); | |
645 | ||
646 | /* | |
647 | * we need to EOI the IPI if we got here from kexec down IPI | |
648 | * | |
649 | * probably need to check all the other interrupts too | |
650 | * should we be flagging idle loop instead? | |
651 | * or creating some task to be scheduled? | |
652 | */ | |
653 | ops->xirr_info_set(cpu, XICS_IPI); | |
654 | ||
fce0d574 | 655 | /* |
6d22d85a PM |
656 | * Some machines need to have at least one cpu in the GIQ, |
657 | * so leave the master cpu in the group. | |
fce0d574 | 658 | */ |
81bbbe92 | 659 | if (secondary) |
6d22d85a PM |
660 | rtas_set_indicator(GLOBAL_INTERRUPT_QUEUE, |
661 | (1UL << interrupt_server_size) - 1 - | |
662 | default_distrib_server, 0); | |
fce0d574 S |
663 | } |
664 | ||
1da177e4 LT |
665 | #ifdef CONFIG_HOTPLUG_CPU |
666 | ||
667 | /* Interrupts are disabled. */ | |
668 | void xics_migrate_irqs_away(void) | |
669 | { | |
670 | int status; | |
671 | unsigned int irq, virq, cpu = smp_processor_id(); | |
672 | ||
673 | /* Reject any interrupt that was queued to us... */ | |
674 | ops->cppr_info(cpu, 0); | |
675 | iosync(); | |
676 | ||
677 | /* remove ourselves from the global interrupt queue */ | |
678 | status = rtas_set_indicator(GLOBAL_INTERRUPT_QUEUE, | |
679 | (1UL << interrupt_server_size) - 1 - default_distrib_server, 0); | |
680 | WARN_ON(status < 0); | |
681 | ||
682 | /* Allow IPIs again... */ | |
683 | ops->cppr_info(cpu, DEFAULT_PRIORITY); | |
684 | iosync(); | |
685 | ||
686 | for_each_irq(virq) { | |
687 | irq_desc_t *desc; | |
688 | int xics_status[2]; | |
689 | unsigned long flags; | |
690 | ||
691 | /* We cant set affinity on ISA interrupts */ | |
692 | if (virq < irq_offset_value()) | |
693 | continue; | |
694 | ||
695 | desc = get_irq_desc(virq); | |
696 | irq = virt_irq_to_real(irq_offset_down(virq)); | |
697 | ||
698 | /* We need to get IPIs still. */ | |
699 | if (irq == XICS_IPI || irq == NO_IRQ) | |
700 | continue; | |
701 | ||
702 | /* We only need to migrate enabled IRQS */ | |
d1bef4ed | 703 | if (desc == NULL || desc->chip == NULL |
1da177e4 | 704 | || desc->action == NULL |
d1bef4ed | 705 | || desc->chip->set_affinity == NULL) |
1da177e4 LT |
706 | continue; |
707 | ||
708 | spin_lock_irqsave(&desc->lock, flags); | |
709 | ||
710 | status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq); | |
711 | if (status) { | |
26370322 | 712 | printk(KERN_ERR "migrate_irqs_away: irq=%u " |
1da177e4 LT |
713 | "ibm,get-xive returns %d\n", |
714 | virq, status); | |
715 | goto unlock; | |
716 | } | |
717 | ||
718 | /* | |
719 | * We only support delivery to all cpus or to one cpu. | |
720 | * The irq has to be migrated only in the single cpu | |
721 | * case. | |
722 | */ | |
723 | if (xics_status[0] != get_hard_smp_processor_id(cpu)) | |
724 | goto unlock; | |
725 | ||
26370322 | 726 | printk(KERN_WARNING "IRQ %u affinity broken off cpu %u\n", |
1da177e4 LT |
727 | virq, cpu); |
728 | ||
729 | /* Reset affinity to all cpus */ | |
d1bef4ed | 730 | desc->chip->set_affinity(virq, CPU_MASK_ALL); |
a53da52f | 731 | irq_desc[irq].affinity = CPU_MASK_ALL; |
1da177e4 LT |
732 | unlock: |
733 | spin_unlock_irqrestore(&desc->lock, flags); | |
734 | } | |
735 | } | |
736 | #endif |