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Commit | Line | Data |
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007e8f51 DG |
1 | /* |
2 | * arch/powerpc/platforms/pseries/xics.c | |
1da177e4 LT |
3 | * |
4 | * Copyright 2000 IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
0ebfff14 | 11 | |
1da177e4 LT |
12 | #include <linux/types.h> |
13 | #include <linux/threads.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/irq.h> | |
16 | #include <linux/smp.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/signal.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/gfp.h> | |
21 | #include <linux/radix-tree.h> | |
22 | #include <linux/cpu.h> | |
0ebfff14 | 23 | |
57cfb814 | 24 | #include <asm/firmware.h> |
1da177e4 LT |
25 | #include <asm/prom.h> |
26 | #include <asm/io.h> | |
27 | #include <asm/pgtable.h> | |
28 | #include <asm/smp.h> | |
29 | #include <asm/rtas.h> | |
1da177e4 LT |
30 | #include <asm/hvcall.h> |
31 | #include <asm/machdep.h> | |
2227718c | 32 | #include <asm/i8259.h> |
1da177e4 | 33 | |
007e8f51 | 34 | #include "xics.h" |
b9377ffc | 35 | #include "plpar_wrappers.h" |
007e8f51 | 36 | |
0641cc91 MM |
37 | static struct irq_host *xics_host; |
38 | ||
1da177e4 LT |
39 | #define XICS_IPI 2 |
40 | #define XICS_IRQ_SPURIOUS 0 | |
41 | ||
42 | /* Want a priority other than 0. Various HW issues require this. */ | |
43 | #define DEFAULT_PRIORITY 5 | |
44 | ||
007e8f51 | 45 | /* |
1da177e4 | 46 | * Mark IPIs as higher priority so we can take them inside interrupts that |
6714465e | 47 | * arent marked IRQF_DISABLED |
1da177e4 LT |
48 | */ |
49 | #define IPI_PRIORITY 4 | |
50 | ||
0641cc91 MM |
51 | static unsigned int default_server = 0xFF; |
52 | static unsigned int default_distrib_server = 0; | |
53 | static unsigned int interrupt_server_size = 8; | |
54 | ||
55 | /* RTAS service tokens */ | |
56 | static int ibm_get_xive; | |
57 | static int ibm_set_xive; | |
58 | static int ibm_int_on; | |
59 | static int ibm_int_off; | |
60 | ||
61 | ||
62 | /* Direct hardware low level accessors */ | |
63 | ||
64 | /* The part of the interrupt presentation layer that we care about */ | |
1da177e4 LT |
65 | struct xics_ipl { |
66 | union { | |
67 | u32 word; | |
68 | u8 bytes[4]; | |
69 | } xirr_poll; | |
70 | union { | |
71 | u32 word; | |
72 | u8 bytes[4]; | |
73 | } xirr; | |
74 | u32 dummy; | |
75 | union { | |
76 | u32 word; | |
77 | u8 bytes[4]; | |
78 | } qirr; | |
79 | }; | |
80 | ||
81 | static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS]; | |
82 | ||
d7cf0edb | 83 | static inline unsigned int direct_xirr_info_get(void) |
1da177e4 | 84 | { |
d7cf0edb MM |
85 | int cpu = smp_processor_id(); |
86 | ||
87 | return in_be32(&xics_per_cpu[cpu]->xirr.word); | |
1da177e4 LT |
88 | } |
89 | ||
d7cf0edb | 90 | static inline void direct_xirr_info_set(int value) |
1da177e4 | 91 | { |
d7cf0edb MM |
92 | int cpu = smp_processor_id(); |
93 | ||
94 | out_be32(&xics_per_cpu[cpu]->xirr.word, value); | |
1da177e4 LT |
95 | } |
96 | ||
d7cf0edb | 97 | static inline void direct_cppr_info(u8 value) |
1da177e4 | 98 | { |
d7cf0edb MM |
99 | int cpu = smp_processor_id(); |
100 | ||
101 | out_8(&xics_per_cpu[cpu]->xirr.bytes[0], value); | |
1da177e4 LT |
102 | } |
103 | ||
b9e5b4e6 | 104 | static inline void direct_qirr_info(int n_cpu, u8 value) |
1da177e4 LT |
105 | { |
106 | out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value); | |
107 | } | |
108 | ||
1da177e4 | 109 | |
b9e5b4e6 | 110 | /* LPAR low level accessors */ |
1da177e4 | 111 | |
d7cf0edb | 112 | static inline unsigned int lpar_xirr_info_get(void) |
1da177e4 LT |
113 | { |
114 | unsigned long lpar_rc; | |
007e8f51 | 115 | unsigned long return_value; |
1da177e4 LT |
116 | |
117 | lpar_rc = plpar_xirr(&return_value); | |
706c8c93 | 118 | if (lpar_rc != H_SUCCESS) |
007e8f51 | 119 | panic(" bad return code xirr - rc = %lx \n", lpar_rc); |
0ebfff14 | 120 | return (unsigned int)return_value; |
1da177e4 LT |
121 | } |
122 | ||
d7cf0edb | 123 | static inline void lpar_xirr_info_set(int value) |
1da177e4 LT |
124 | { |
125 | unsigned long lpar_rc; | |
126 | unsigned long val64 = value & 0xffffffff; | |
127 | ||
128 | lpar_rc = plpar_eoi(val64); | |
706c8c93 | 129 | if (lpar_rc != H_SUCCESS) |
1da177e4 | 130 | panic("bad return code EOI - rc = %ld, value=%lx\n", lpar_rc, |
007e8f51 | 131 | val64); |
1da177e4 LT |
132 | } |
133 | ||
d7cf0edb | 134 | static inline void lpar_cppr_info(u8 value) |
1da177e4 LT |
135 | { |
136 | unsigned long lpar_rc; | |
137 | ||
138 | lpar_rc = plpar_cppr(value); | |
706c8c93 | 139 | if (lpar_rc != H_SUCCESS) |
007e8f51 | 140 | panic("bad return code cppr - rc = %lx\n", lpar_rc); |
1da177e4 LT |
141 | } |
142 | ||
b9e5b4e6 | 143 | static inline void lpar_qirr_info(int n_cpu , u8 value) |
1da177e4 LT |
144 | { |
145 | unsigned long lpar_rc; | |
146 | ||
147 | lpar_rc = plpar_ipi(get_hard_smp_processor_id(n_cpu), value); | |
706c8c93 | 148 | if (lpar_rc != H_SUCCESS) |
007e8f51 | 149 | panic("bad return code qirr - rc = %lx\n", lpar_rc); |
1da177e4 LT |
150 | } |
151 | ||
1da177e4 | 152 | |
0641cc91 | 153 | /* Interface to generic irq subsystem */ |
1da177e4 LT |
154 | |
155 | #ifdef CONFIG_SMP | |
7ccb4a66 | 156 | static int get_irq_server(unsigned int virq, unsigned int strict_check) |
1da177e4 | 157 | { |
7ccb4a66 | 158 | int server; |
1da177e4 | 159 | /* For the moment only implement delivery to all cpus or one cpu */ |
0ebfff14 | 160 | cpumask_t cpumask = irq_desc[virq].affinity; |
1da177e4 LT |
161 | cpumask_t tmp = CPU_MASK_NONE; |
162 | ||
163 | if (!distribute_irqs) | |
164 | return default_server; | |
165 | ||
7ccb4a66 | 166 | if (!cpus_equal(cpumask, CPU_MASK_ALL)) { |
1da177e4 LT |
167 | cpus_and(tmp, cpu_online_map, cpumask); |
168 | ||
7ccb4a66 MK |
169 | server = first_cpu(tmp); |
170 | ||
171 | if (server < NR_CPUS) | |
172 | return get_hard_smp_processor_id(server); | |
173 | ||
174 | if (strict_check) | |
175 | return -1; | |
1da177e4 LT |
176 | } |
177 | ||
7ccb4a66 MK |
178 | if (cpus_equal(cpu_online_map, cpu_present_map)) |
179 | return default_distrib_server; | |
1da177e4 | 180 | |
7ccb4a66 | 181 | return default_server; |
1da177e4 LT |
182 | } |
183 | #else | |
7ccb4a66 | 184 | static int get_irq_server(unsigned int virq, unsigned int strict_check) |
1da177e4 LT |
185 | { |
186 | return default_server; | |
187 | } | |
188 | #endif | |
189 | ||
b9e5b4e6 | 190 | static void xics_unmask_irq(unsigned int virq) |
1da177e4 LT |
191 | { |
192 | unsigned int irq; | |
193 | int call_status; | |
7ccb4a66 | 194 | int server; |
1da177e4 | 195 | |
0ebfff14 BH |
196 | pr_debug("xics: unmask virq %d\n", virq); |
197 | ||
198 | irq = (unsigned int)irq_map[virq].hwirq; | |
199 | pr_debug(" -> map to hwirq 0x%x\n", irq); | |
200 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | |
1da177e4 LT |
201 | return; |
202 | ||
7ccb4a66 | 203 | server = get_irq_server(virq, 0); |
b9e5b4e6 | 204 | |
1da177e4 LT |
205 | call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server, |
206 | DEFAULT_PRIORITY); | |
207 | if (call_status != 0) { | |
26370322 AB |
208 | printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_set_xive " |
209 | "returned %d\n", irq, call_status); | |
210 | printk("set_xive %x, server %x\n", ibm_set_xive, server); | |
1da177e4 LT |
211 | return; |
212 | } | |
213 | ||
214 | /* Now unmask the interrupt (often a no-op) */ | |
215 | call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq); | |
216 | if (call_status != 0) { | |
26370322 AB |
217 | printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_int_on " |
218 | "returned %d\n", irq, call_status); | |
1da177e4 LT |
219 | return; |
220 | } | |
221 | } | |
222 | ||
0641cc91 MM |
223 | static unsigned int xics_startup(unsigned int virq) |
224 | { | |
225 | /* unmask it */ | |
226 | xics_unmask_irq(virq); | |
227 | return 0; | |
228 | } | |
229 | ||
b9e5b4e6 | 230 | static void xics_mask_real_irq(unsigned int irq) |
1da177e4 LT |
231 | { |
232 | int call_status; | |
1da177e4 LT |
233 | |
234 | if (irq == XICS_IPI) | |
235 | return; | |
236 | ||
237 | call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq); | |
238 | if (call_status != 0) { | |
26370322 AB |
239 | printk(KERN_ERR "xics_disable_real_irq: irq=%u: " |
240 | "ibm_int_off returned %d\n", irq, call_status); | |
1da177e4 LT |
241 | return; |
242 | } | |
243 | ||
1da177e4 | 244 | /* Have to set XIVE to 0xff to be able to remove a slot */ |
673aeb76 MO |
245 | call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, |
246 | default_server, 0xff); | |
1da177e4 | 247 | if (call_status != 0) { |
26370322 AB |
248 | printk(KERN_ERR "xics_disable_irq: irq=%u: ibm_set_xive(0xff)" |
249 | " returned %d\n", irq, call_status); | |
1da177e4 LT |
250 | return; |
251 | } | |
252 | } | |
253 | ||
b9e5b4e6 | 254 | static void xics_mask_irq(unsigned int virq) |
1da177e4 LT |
255 | { |
256 | unsigned int irq; | |
257 | ||
0ebfff14 BH |
258 | pr_debug("xics: mask virq %d\n", virq); |
259 | ||
260 | irq = (unsigned int)irq_map[virq].hwirq; | |
261 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | |
262 | return; | |
263 | xics_mask_real_irq(irq); | |
b9e5b4e6 BH |
264 | } |
265 | ||
0641cc91 | 266 | static void xics_mask_unknown_vec(unsigned int vec) |
1da177e4 | 267 | { |
0641cc91 MM |
268 | printk(KERN_ERR "Interrupt %u (real) is invalid, disabling it.\n", vec); |
269 | xics_mask_real_irq(vec); | |
1da177e4 LT |
270 | } |
271 | ||
8767e9ba | 272 | static inline unsigned int xics_xirr_vector(unsigned int xirr) |
1da177e4 | 273 | { |
8767e9ba MM |
274 | /* |
275 | * The top byte is the old cppr, to be restored on EOI. | |
276 | * The remaining 24 bits are the vector. | |
277 | */ | |
278 | return xirr & 0x00ffffff; | |
279 | } | |
280 | ||
8767e9ba MM |
281 | static unsigned int xics_get_irq_direct(void) |
282 | { | |
283 | unsigned int xirr = direct_xirr_info_get(); | |
284 | unsigned int vec = xics_xirr_vector(xirr); | |
285 | unsigned int irq; | |
1da177e4 | 286 | |
b9e5b4e6 BH |
287 | if (vec == XICS_IRQ_SPURIOUS) |
288 | return NO_IRQ; | |
8767e9ba | 289 | |
967e012e | 290 | irq = irq_radix_revmap_lookup(xics_host, vec); |
b9e5b4e6 | 291 | if (likely(irq != NO_IRQ)) |
0ebfff14 | 292 | return irq; |
b9e5b4e6 | 293 | |
8767e9ba MM |
294 | /* We don't have a linux mapping, so have rtas mask it. */ |
295 | xics_mask_unknown_vec(vec); | |
1da177e4 | 296 | |
8767e9ba MM |
297 | /* We might learn about it later, so EOI it */ |
298 | direct_xirr_info_set(xirr); | |
299 | return NO_IRQ; | |
b9e5b4e6 BH |
300 | } |
301 | ||
35a84c2f | 302 | static unsigned int xics_get_irq_lpar(void) |
1da177e4 | 303 | { |
8767e9ba MM |
304 | unsigned int xirr = lpar_xirr_info_get(); |
305 | unsigned int vec = xics_xirr_vector(xirr); | |
306 | unsigned int irq; | |
307 | ||
308 | if (vec == XICS_IRQ_SPURIOUS) | |
309 | return NO_IRQ; | |
310 | ||
311 | irq = irq_radix_revmap_lookup(xics_host, vec); | |
312 | if (likely(irq != NO_IRQ)) | |
313 | return irq; | |
314 | ||
315 | /* We don't have a linux mapping, so have RTAS mask it. */ | |
316 | xics_mask_unknown_vec(vec); | |
317 | ||
318 | /* We might learn about it later, so EOI it */ | |
319 | lpar_xirr_info_set(xirr); | |
320 | return NO_IRQ; | |
b9e5b4e6 BH |
321 | } |
322 | ||
0641cc91 | 323 | static void xics_eoi_direct(unsigned int virq) |
b9e5b4e6 | 324 | { |
0641cc91 | 325 | unsigned int irq = (unsigned int)irq_map[virq].hwirq; |
b9e5b4e6 | 326 | |
0641cc91 MM |
327 | iosync(); |
328 | direct_xirr_info_set((0xff << 24) | irq); | |
b9e5b4e6 BH |
329 | } |
330 | ||
0641cc91 | 331 | static void xics_eoi_lpar(unsigned int virq) |
b9e5b4e6 | 332 | { |
0641cc91 | 333 | unsigned int irq = (unsigned int)irq_map[virq].hwirq; |
1da177e4 | 334 | |
b9e5b4e6 | 335 | iosync(); |
0641cc91 | 336 | lpar_xirr_info_set((0xff << 24) | irq); |
b9e5b4e6 BH |
337 | } |
338 | ||
339 | static void xics_set_affinity(unsigned int virq, cpumask_t cpumask) | |
340 | { | |
341 | unsigned int irq; | |
342 | int status; | |
343 | int xics_status[2]; | |
7ccb4a66 | 344 | int irq_server; |
b9e5b4e6 | 345 | |
0ebfff14 BH |
346 | irq = (unsigned int)irq_map[virq].hwirq; |
347 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | |
b9e5b4e6 BH |
348 | return; |
349 | ||
350 | status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq); | |
351 | ||
352 | if (status) { | |
353 | printk(KERN_ERR "xics_set_affinity: irq=%u ibm,get-xive " | |
354 | "returns %d\n", irq, status); | |
355 | return; | |
356 | } | |
357 | ||
7ccb4a66 MK |
358 | /* |
359 | * For the moment only implement delivery to all cpus or one cpu. | |
360 | * Get current irq_server for the given irq | |
361 | */ | |
e48395f1 | 362 | irq_server = get_irq_server(virq, 1); |
7ccb4a66 MK |
363 | if (irq_server == -1) { |
364 | char cpulist[128]; | |
365 | cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask); | |
366 | printk(KERN_WARNING "xics_set_affinity: No online cpus in " | |
367 | "the mask %s for irq %d\n", cpulist, virq); | |
368 | return; | |
b9e5b4e6 BH |
369 | } |
370 | ||
371 | status = rtas_call(ibm_set_xive, 3, 1, NULL, | |
7ccb4a66 | 372 | irq, irq_server, xics_status[1]); |
b9e5b4e6 BH |
373 | |
374 | if (status) { | |
375 | printk(KERN_ERR "xics_set_affinity: irq=%u ibm,set-xive " | |
376 | "returns %d\n", irq, status); | |
377 | return; | |
378 | } | |
379 | } | |
380 | ||
381 | static struct irq_chip xics_pic_direct = { | |
382 | .typename = " XICS ", | |
383 | .startup = xics_startup, | |
384 | .mask = xics_mask_irq, | |
385 | .unmask = xics_unmask_irq, | |
386 | .eoi = xics_eoi_direct, | |
387 | .set_affinity = xics_set_affinity | |
388 | }; | |
389 | ||
b9e5b4e6 BH |
390 | static struct irq_chip xics_pic_lpar = { |
391 | .typename = " XICS ", | |
392 | .startup = xics_startup, | |
393 | .mask = xics_mask_irq, | |
394 | .unmask = xics_unmask_irq, | |
395 | .eoi = xics_eoi_lpar, | |
396 | .set_affinity = xics_set_affinity | |
397 | }; | |
398 | ||
0641cc91 MM |
399 | |
400 | /* Interface to arch irq controller subsystem layer */ | |
401 | ||
1af9fa89 ME |
402 | /* Points to the irq_chip we're actually using */ |
403 | static struct irq_chip *xics_irq_chip; | |
b9e5b4e6 | 404 | |
0ebfff14 | 405 | static int xics_host_match(struct irq_host *h, struct device_node *node) |
1da177e4 | 406 | { |
0ebfff14 BH |
407 | /* IBM machines have interrupt parents of various funky types for things |
408 | * like vdevices, events, etc... The trick we use here is to match | |
409 | * everything here except the legacy 8259 which is compatible "chrp,iic" | |
410 | */ | |
55b61fec | 411 | return !of_device_is_compatible(node, "chrp,iic"); |
0ebfff14 | 412 | } |
1da177e4 | 413 | |
1af9fa89 ME |
414 | static int xics_host_map(struct irq_host *h, unsigned int virq, |
415 | irq_hw_number_t hw) | |
0ebfff14 | 416 | { |
1af9fa89 | 417 | pr_debug("xics: map virq %d, hwirq 0x%lx\n", virq, hw); |
0ebfff14 | 418 | |
967e012e SD |
419 | /* Insert the interrupt mapping into the radix tree for fast lookup */ |
420 | irq_radix_revmap_insert(xics_host, virq, hw); | |
421 | ||
0ebfff14 | 422 | get_irq_desc(virq)->status |= IRQ_LEVEL; |
1af9fa89 | 423 | set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq); |
0ebfff14 BH |
424 | return 0; |
425 | } | |
426 | ||
427 | static int xics_host_xlate(struct irq_host *h, struct device_node *ct, | |
428 | u32 *intspec, unsigned int intsize, | |
429 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) | |
430 | ||
431 | { | |
432 | /* Current xics implementation translates everything | |
433 | * to level. It is not technically right for MSIs but this | |
434 | * is irrelevant at this point. We might get smarter in the future | |
6c80a21c | 435 | */ |
0ebfff14 BH |
436 | *out_hwirq = intspec[0]; |
437 | *out_flags = IRQ_TYPE_LEVEL_LOW; | |
438 | ||
439 | return 0; | |
440 | } | |
441 | ||
1af9fa89 | 442 | static struct irq_host_ops xics_host_ops = { |
0ebfff14 | 443 | .match = xics_host_match, |
1af9fa89 | 444 | .map = xics_host_map, |
0ebfff14 BH |
445 | .xlate = xics_host_xlate, |
446 | }; | |
447 | ||
448 | static void __init xics_init_host(void) | |
449 | { | |
0ebfff14 | 450 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
1af9fa89 | 451 | xics_irq_chip = &xics_pic_lpar; |
0ebfff14 | 452 | else |
1af9fa89 ME |
453 | xics_irq_chip = &xics_pic_direct; |
454 | ||
455 | xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, &xics_host_ops, | |
0ebfff14 BH |
456 | XICS_IRQ_SPURIOUS); |
457 | BUG_ON(xics_host == NULL); | |
458 | irq_set_default_host(xics_host); | |
6c80a21c | 459 | } |
1da177e4 | 460 | |
0641cc91 MM |
461 | |
462 | /* Inter-processor interrupt support */ | |
463 | ||
464 | #ifdef CONFIG_SMP | |
465 | /* | |
466 | * XICS only has a single IPI, so encode the messages per CPU | |
467 | */ | |
468 | struct xics_ipi_struct { | |
469 | unsigned long value; | |
470 | } ____cacheline_aligned; | |
471 | ||
472 | static struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned; | |
473 | ||
474 | static inline void smp_xics_do_message(int cpu, int msg) | |
475 | { | |
476 | set_bit(msg, &xics_ipi_message[cpu].value); | |
477 | mb(); | |
478 | if (firmware_has_feature(FW_FEATURE_LPAR)) | |
479 | lpar_qirr_info(cpu, IPI_PRIORITY); | |
480 | else | |
481 | direct_qirr_info(cpu, IPI_PRIORITY); | |
482 | } | |
483 | ||
484 | void smp_xics_message_pass(int target, int msg) | |
485 | { | |
486 | unsigned int i; | |
487 | ||
488 | if (target < NR_CPUS) { | |
489 | smp_xics_do_message(target, msg); | |
490 | } else { | |
491 | for_each_online_cpu(i) { | |
492 | if (target == MSG_ALL_BUT_SELF | |
493 | && i == smp_processor_id()) | |
494 | continue; | |
495 | smp_xics_do_message(i, msg); | |
496 | } | |
497 | } | |
498 | } | |
499 | ||
500 | static irqreturn_t xics_ipi_dispatch(int cpu) | |
501 | { | |
502 | WARN_ON(cpu_is_offline(cpu)); | |
503 | ||
504 | while (xics_ipi_message[cpu].value) { | |
505 | if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION, | |
506 | &xics_ipi_message[cpu].value)) { | |
507 | mb(); | |
508 | smp_message_recv(PPC_MSG_CALL_FUNCTION); | |
509 | } | |
510 | if (test_and_clear_bit(PPC_MSG_RESCHEDULE, | |
511 | &xics_ipi_message[cpu].value)) { | |
512 | mb(); | |
513 | smp_message_recv(PPC_MSG_RESCHEDULE); | |
514 | } | |
515 | if (test_and_clear_bit(PPC_MSG_CALL_FUNC_SINGLE, | |
516 | &xics_ipi_message[cpu].value)) { | |
517 | mb(); | |
518 | smp_message_recv(PPC_MSG_CALL_FUNC_SINGLE); | |
519 | } | |
520 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) | |
521 | if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK, | |
522 | &xics_ipi_message[cpu].value)) { | |
523 | mb(); | |
524 | smp_message_recv(PPC_MSG_DEBUGGER_BREAK); | |
525 | } | |
526 | #endif | |
527 | } | |
528 | return IRQ_HANDLED; | |
529 | } | |
530 | ||
531 | static irqreturn_t xics_ipi_action_direct(int irq, void *dev_id) | |
532 | { | |
533 | int cpu = smp_processor_id(); | |
534 | ||
535 | direct_qirr_info(cpu, 0xff); | |
536 | ||
537 | return xics_ipi_dispatch(cpu); | |
538 | } | |
539 | ||
540 | static irqreturn_t xics_ipi_action_lpar(int irq, void *dev_id) | |
541 | { | |
542 | int cpu = smp_processor_id(); | |
543 | ||
544 | lpar_qirr_info(cpu, 0xff); | |
545 | ||
546 | return xics_ipi_dispatch(cpu); | |
547 | } | |
548 | ||
549 | static void xics_request_ipi(void) | |
550 | { | |
551 | unsigned int ipi; | |
552 | int rc; | |
553 | ||
554 | ipi = irq_create_mapping(xics_host, XICS_IPI); | |
555 | BUG_ON(ipi == NO_IRQ); | |
556 | ||
557 | /* | |
558 | * IPIs are marked IRQF_DISABLED as they must run with irqs | |
559 | * disabled | |
560 | */ | |
561 | set_irq_handler(ipi, handle_percpu_irq); | |
562 | if (firmware_has_feature(FW_FEATURE_LPAR)) | |
563 | rc = request_irq(ipi, xics_ipi_action_lpar, IRQF_DISABLED, | |
564 | "IPI", NULL); | |
565 | else | |
566 | rc = request_irq(ipi, xics_ipi_action_direct, IRQF_DISABLED, | |
567 | "IPI", NULL); | |
568 | BUG_ON(rc); | |
569 | } | |
570 | ||
571 | int __init smp_xics_probe(void) | |
572 | { | |
573 | xics_request_ipi(); | |
574 | ||
575 | return cpus_weight(cpu_possible_map); | |
576 | } | |
577 | ||
578 | #endif /* CONFIG_SMP */ | |
579 | ||
580 | ||
581 | /* Initialization */ | |
582 | ||
583 | static void xics_update_irq_servers(void) | |
584 | { | |
585 | int i, j; | |
586 | struct device_node *np; | |
587 | u32 ilen; | |
588 | const u32 *ireg, *isize; | |
589 | u32 hcpuid; | |
590 | ||
591 | /* Find the server numbers for the boot cpu. */ | |
592 | np = of_get_cpu_node(boot_cpuid, NULL); | |
593 | BUG_ON(!np); | |
594 | ||
595 | ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen); | |
596 | if (!ireg) { | |
597 | of_node_put(np); | |
598 | return; | |
599 | } | |
600 | ||
601 | i = ilen / sizeof(int); | |
602 | hcpuid = get_hard_smp_processor_id(boot_cpuid); | |
603 | ||
604 | /* Global interrupt distribution server is specified in the last | |
605 | * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last | |
606 | * entry fom this property for current boot cpu id and use it as | |
607 | * default distribution server | |
608 | */ | |
609 | for (j = 0; j < i; j += 2) { | |
610 | if (ireg[j] == hcpuid) { | |
611 | default_server = hcpuid; | |
612 | default_distrib_server = ireg[j+1]; | |
613 | ||
614 | isize = of_get_property(np, | |
615 | "ibm,interrupt-server#-size", NULL); | |
616 | if (isize) | |
617 | interrupt_server_size = *isize; | |
618 | } | |
619 | } | |
620 | ||
621 | of_node_put(np); | |
622 | } | |
623 | ||
0ebfff14 BH |
624 | static void __init xics_map_one_cpu(int hw_id, unsigned long addr, |
625 | unsigned long size) | |
1da177e4 | 626 | { |
0ebfff14 | 627 | #ifdef CONFIG_SMP |
1da177e4 | 628 | int i; |
1da177e4 | 629 | |
0ebfff14 BH |
630 | /* This may look gross but it's good enough for now, we don't quite |
631 | * have a hard -> linux processor id matching. | |
632 | */ | |
633 | for_each_possible_cpu(i) { | |
634 | if (!cpu_present(i)) | |
635 | continue; | |
636 | if (hw_id == get_hard_smp_processor_id(i)) { | |
637 | xics_per_cpu[i] = ioremap(addr, size); | |
638 | return; | |
639 | } | |
640 | } | |
641 | #else | |
642 | if (hw_id != 0) | |
643 | return; | |
644 | xics_per_cpu[0] = ioremap(addr, size); | |
645 | #endif /* CONFIG_SMP */ | |
646 | } | |
1da177e4 | 647 | |
0ebfff14 BH |
648 | static void __init xics_init_one_node(struct device_node *np, |
649 | unsigned int *indx) | |
650 | { | |
651 | unsigned int ilen; | |
954a46e2 | 652 | const u32 *ireg; |
1da177e4 | 653 | |
0ebfff14 BH |
654 | /* This code does the theorically broken assumption that the interrupt |
655 | * server numbers are the same as the hard CPU numbers. | |
656 | * This happens to be the case so far but we are playing with fire... | |
657 | * should be fixed one of these days. -BenH. | |
658 | */ | |
e2eb6392 | 659 | ireg = of_get_property(np, "ibm,interrupt-server-ranges", NULL); |
1da177e4 | 660 | |
0ebfff14 BH |
661 | /* Do that ever happen ? we'll know soon enough... but even good'old |
662 | * f80 does have that property .. | |
663 | */ | |
664 | WARN_ON(ireg == NULL); | |
1da177e4 LT |
665 | if (ireg) { |
666 | /* | |
667 | * set node starting index for this node | |
668 | */ | |
0ebfff14 | 669 | *indx = *ireg; |
1da177e4 | 670 | } |
e2eb6392 | 671 | ireg = of_get_property(np, "reg", &ilen); |
1da177e4 LT |
672 | if (!ireg) |
673 | panic("xics_init_IRQ: can't find interrupt reg property"); | |
007e8f51 | 674 | |
0ebfff14 BH |
675 | while (ilen >= (4 * sizeof(u32))) { |
676 | unsigned long addr, size; | |
677 | ||
678 | /* XXX Use proper OF parsing code here !!! */ | |
679 | addr = (unsigned long)*ireg++ << 32; | |
680 | ilen -= sizeof(u32); | |
681 | addr |= *ireg++; | |
682 | ilen -= sizeof(u32); | |
683 | size = (unsigned long)*ireg++ << 32; | |
684 | ilen -= sizeof(u32); | |
685 | size |= *ireg++; | |
686 | ilen -= sizeof(u32); | |
687 | xics_map_one_cpu(*indx, addr, size); | |
688 | (*indx)++; | |
689 | } | |
690 | } | |
691 | ||
0ebfff14 BH |
692 | void __init xics_init_IRQ(void) |
693 | { | |
0ebfff14 | 694 | struct device_node *np; |
de0723dc | 695 | u32 indx = 0; |
0ebfff14 BH |
696 | int found = 0; |
697 | ||
698 | ppc64_boot_msg(0x20, "XICS Init"); | |
699 | ||
700 | ibm_get_xive = rtas_token("ibm,get-xive"); | |
701 | ibm_set_xive = rtas_token("ibm,set-xive"); | |
702 | ibm_int_on = rtas_token("ibm,int-on"); | |
703 | ibm_int_off = rtas_token("ibm,int-off"); | |
704 | ||
705 | for_each_node_by_type(np, "PowerPC-External-Interrupt-Presentation") { | |
706 | found = 1; | |
707 | if (firmware_has_feature(FW_FEATURE_LPAR)) | |
708 | break; | |
709 | xics_init_one_node(np, &indx); | |
710 | } | |
711 | if (found == 0) | |
712 | return; | |
713 | ||
de0723dc | 714 | xics_update_irq_servers(); |
302905a3 | 715 | xics_init_host(); |
1da177e4 | 716 | |
0ebfff14 BH |
717 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
718 | ppc_md.get_irq = xics_get_irq_lpar; | |
719 | else | |
b9e5b4e6 | 720 | ppc_md.get_irq = xics_get_irq_direct; |
1da177e4 | 721 | |
6c80a21c | 722 | xics_setup_cpu(); |
1da177e4 | 723 | |
0ebfff14 | 724 | ppc64_boot_msg(0x21, "XICS Done"); |
1da177e4 | 725 | } |
b9e5b4e6 | 726 | |
0641cc91 | 727 | /* Cpu startup, shutdown, and hotplug */ |
1da177e4 | 728 | |
0641cc91 | 729 | static void xics_set_cpu_priority(unsigned char cppr) |
1da177e4 | 730 | { |
b9e5b4e6 | 731 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
0641cc91 | 732 | lpar_cppr_info(cppr); |
b9e5b4e6 | 733 | else |
0641cc91 MM |
734 | direct_cppr_info(cppr); |
735 | iosync(); | |
1da177e4 | 736 | } |
d13f7208 | 737 | |
0641cc91 MM |
738 | |
739 | void xics_setup_cpu(void) | |
d13f7208 | 740 | { |
0641cc91 | 741 | xics_set_cpu_priority(0xff); |
d13f7208 | 742 | |
0641cc91 MM |
743 | /* |
744 | * Put the calling processor into the GIQ. This is really only | |
745 | * necessary from a secondary thread as the OF start-cpu interface | |
746 | * performs this function for us on primary threads. | |
747 | * | |
748 | * XXX: undo of teardown on kexec needs this too, as may hotplug | |
749 | */ | |
750 | rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, | |
751 | (1UL << interrupt_server_size) - 1 - default_distrib_server, 1); | |
d13f7208 MM |
752 | } |
753 | ||
f10095c3 | 754 | void xics_teardown_cpu(void) |
fce0d574 S |
755 | { |
756 | int cpu = smp_processor_id(); | |
fce0d574 | 757 | |
d7cf0edb | 758 | xics_set_cpu_priority(0); |
81bbbe92 | 759 | |
6e99e458 BH |
760 | /* |
761 | * Clear IPI | |
762 | */ | |
763 | if (firmware_has_feature(FW_FEATURE_LPAR)) | |
764 | lpar_qirr_info(cpu, 0xff); | |
765 | else | |
766 | direct_qirr_info(cpu, 0xff); | |
c3e8506c NF |
767 | } |
768 | ||
769 | void xics_kexec_teardown_cpu(int secondary) | |
770 | { | |
771 | unsigned int ipi; | |
772 | struct irq_desc *desc; | |
773 | ||
774 | xics_teardown_cpu(); | |
6e99e458 | 775 | |
81bbbe92 | 776 | /* |
c3e8506c | 777 | * we need to EOI the IPI |
81bbbe92 HM |
778 | * |
779 | * probably need to check all the other interrupts too | |
780 | * should we be flagging idle loop instead? | |
781 | * or creating some task to be scheduled? | |
782 | */ | |
0ebfff14 BH |
783 | |
784 | ipi = irq_find_mapping(xics_host, XICS_IPI); | |
785 | if (ipi == XICS_IRQ_SPURIOUS) | |
786 | return; | |
787 | desc = get_irq_desc(ipi); | |
b9e5b4e6 | 788 | if (desc->chip && desc->chip->eoi) |
6e99e458 | 789 | desc->chip->eoi(ipi); |
81bbbe92 | 790 | |
fce0d574 | 791 | /* |
6d22d85a PM |
792 | * Some machines need to have at least one cpu in the GIQ, |
793 | * so leave the master cpu in the group. | |
fce0d574 | 794 | */ |
81bbbe92 | 795 | if (secondary) |
81b73dd9 | 796 | rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, |
0ebfff14 BH |
797 | (1UL << interrupt_server_size) - 1 - |
798 | default_distrib_server, 0); | |
fce0d574 S |
799 | } |
800 | ||
1da177e4 LT |
801 | #ifdef CONFIG_HOTPLUG_CPU |
802 | ||
803 | /* Interrupts are disabled. */ | |
804 | void xics_migrate_irqs_away(void) | |
805 | { | |
806 | int status; | |
d7cf0edb MM |
807 | int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id(); |
808 | unsigned int irq, virq; | |
1da177e4 | 809 | |
302905a3 MM |
810 | /* If we used to be the default server, move to the new "boot_cpuid" */ |
811 | if (hw_cpu == default_server) | |
812 | xics_update_irq_servers(); | |
813 | ||
1da177e4 | 814 | /* Reject any interrupt that was queued to us... */ |
d7cf0edb | 815 | xics_set_cpu_priority(0); |
1da177e4 LT |
816 | |
817 | /* remove ourselves from the global interrupt queue */ | |
81b73dd9 | 818 | status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, |
1da177e4 LT |
819 | (1UL << interrupt_server_size) - 1 - default_distrib_server, 0); |
820 | WARN_ON(status < 0); | |
821 | ||
822 | /* Allow IPIs again... */ | |
d7cf0edb | 823 | xics_set_cpu_priority(DEFAULT_PRIORITY); |
1da177e4 LT |
824 | |
825 | for_each_irq(virq) { | |
b9e5b4e6 | 826 | struct irq_desc *desc; |
1da177e4 LT |
827 | int xics_status[2]; |
828 | unsigned long flags; | |
829 | ||
830 | /* We cant set affinity on ISA interrupts */ | |
0ebfff14 | 831 | if (virq < NUM_ISA_INTERRUPTS) |
1da177e4 | 832 | continue; |
0ebfff14 BH |
833 | if (irq_map[virq].host != xics_host) |
834 | continue; | |
835 | irq = (unsigned int)irq_map[virq].hwirq; | |
1da177e4 | 836 | /* We need to get IPIs still. */ |
0ebfff14 | 837 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) |
1da177e4 | 838 | continue; |
0ebfff14 | 839 | desc = get_irq_desc(virq); |
1da177e4 LT |
840 | |
841 | /* We only need to migrate enabled IRQS */ | |
d1bef4ed | 842 | if (desc == NULL || desc->chip == NULL |
1da177e4 | 843 | || desc->action == NULL |
d1bef4ed | 844 | || desc->chip->set_affinity == NULL) |
1da177e4 LT |
845 | continue; |
846 | ||
847 | spin_lock_irqsave(&desc->lock, flags); | |
848 | ||
849 | status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq); | |
850 | if (status) { | |
26370322 | 851 | printk(KERN_ERR "migrate_irqs_away: irq=%u " |
1da177e4 LT |
852 | "ibm,get-xive returns %d\n", |
853 | virq, status); | |
854 | goto unlock; | |
855 | } | |
856 | ||
857 | /* | |
858 | * We only support delivery to all cpus or to one cpu. | |
859 | * The irq has to be migrated only in the single cpu | |
860 | * case. | |
861 | */ | |
d7cf0edb | 862 | if (xics_status[0] != hw_cpu) |
1da177e4 LT |
863 | goto unlock; |
864 | ||
26370322 | 865 | printk(KERN_WARNING "IRQ %u affinity broken off cpu %u\n", |
1da177e4 LT |
866 | virq, cpu); |
867 | ||
868 | /* Reset affinity to all cpus */ | |
a52572dd | 869 | irq_desc[virq].affinity = CPU_MASK_ALL; |
d1bef4ed | 870 | desc->chip->set_affinity(virq, CPU_MASK_ALL); |
1da177e4 LT |
871 | unlock: |
872 | spin_unlock_irqrestore(&desc->lock, flags); | |
873 | } | |
874 | } | |
875 | #endif |