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1da177e4 1/*
69a80d3f 2 * SMP support for pSeries machines.
1da177e4
LT
3 *
4 * Dave Engebretsen, Peter Bergner, and
5 * Mike Corrigan {engebret|bergner|mikec}@us.ibm.com
6 *
7 * Plus various changes from other IBM teams...
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#undef DEBUG
16
1da177e4
LT
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/sched.h>
20#include <linux/smp.h>
21#include <linux/interrupt.h>
22#include <linux/delay.h>
23#include <linux/init.h>
24#include <linux/spinlock.h>
25#include <linux/cache.h>
26#include <linux/err.h>
27#include <linux/sysdev.h>
28#include <linux/cpu.h>
29
30#include <asm/ptrace.h>
31#include <asm/atomic.h>
32#include <asm/irq.h>
33#include <asm/page.h>
34#include <asm/pgtable.h>
35#include <asm/io.h>
36#include <asm/prom.h>
37#include <asm/smp.h>
38#include <asm/paca.h>
39#include <asm/time.h>
40#include <asm/machdep.h>
007e8f51 41#include "xics.h"
1da177e4 42#include <asm/cputable.h>
1ababe11 43#include <asm/firmware.h>
1da177e4
LT
44#include <asm/system.h>
45#include <asm/rtas.h>
1da177e4 46#include <asm/pSeries_reconfig.h>
bbeb3f4c 47#include <asm/mpic.h>
271c3f35 48#include <asm/vdso_datapage.h>
8d089085 49#include <asm/cputhreads.h>
1da177e4 50
a1218720 51#include "plpar_wrappers.h"
8feaeca2 52#include "pseries.h"
a1218720 53
1da177e4 54#ifdef DEBUG
f9e4ec57 55#include <asm/udbg.h>
1da177e4
LT
56#define DBG(fmt...) udbg_printf(fmt)
57#else
58#define DBG(fmt...)
59#endif
60
61/*
62 * The primary thread of each non-boot processor is recorded here before
63 * smp init.
64 */
65static cpumask_t of_spin_map;
66
f39b7a55 67extern void generic_secondary_smp_init(unsigned long);
1da177e4 68
1da177e4
LT
69/**
70 * smp_startup_cpu() - start the given cpu
71 *
72 * At boot time, there is nothing to do for primary threads which were
73 * started from Open Firmware. For anything else, call RTAS with the
74 * appropriate start location.
75 *
76 * Returns:
77 * 0 - failure
78 * 1 - success
79 */
80static inline int __devinit smp_startup_cpu(unsigned int lcpu)
81{
82 int status;
83 unsigned long start_here = __pa((u32)*((unsigned long *)
f39b7a55 84 generic_secondary_smp_init));
1da177e4 85 unsigned int pcpu;
1ed2fd2d 86 int start_cpu;
1da177e4
LT
87
88 if (cpu_isset(lcpu, of_spin_map))
89 /* Already started by OF and sitting in spin loop */
90 return 1;
91
92 pcpu = get_hard_smp_processor_id(lcpu);
93
94 /* Fixup atomic count: it exited inside IRQ handler. */
b5e2fc1c 95 task_thread_info(paca[lcpu].__current)->preempt_count = 0;
1da177e4 96
1ed2fd2d
AB
97 /*
98 * If the RTAS start-cpu token does not exist then presume the
99 * cpu is already spinning.
100 */
101 start_cpu = rtas_token("start-cpu");
102 if (start_cpu == RTAS_UNKNOWN_SERVICE)
103 return 1;
104
496b7a51 105 status = rtas_call(start_cpu, 3, 1, NULL, pcpu, start_here, pcpu);
1da177e4
LT
106 if (status != 0) {
107 printk(KERN_ERR "start-cpu failed: %i\n", status);
108 return 0;
109 }
1ed2fd2d 110
1da177e4
LT
111 return 1;
112}
113
cebf589c 114#ifdef CONFIG_XICS
1da177e4
LT
115static inline void smp_xics_do_message(int cpu, int msg)
116{
117 set_bit(msg, &xics_ipi_message[cpu].value);
118 mb();
119 xics_cause_IPI(cpu);
120}
121
122static void smp_xics_message_pass(int target, int msg)
123{
124 unsigned int i;
125
126 if (target < NR_CPUS) {
127 smp_xics_do_message(target, msg);
128 } else {
129 for_each_online_cpu(i) {
130 if (target == MSG_ALL_BUT_SELF
131 && i == smp_processor_id())
132 continue;
133 smp_xics_do_message(i, msg);
134 }
135 }
136}
137
138static int __init smp_xics_probe(void)
139{
140 xics_request_IPIs();
141
142 return cpus_weight(cpu_possible_map);
143}
144
145static void __devinit smp_xics_setup_cpu(int cpu)
146{
147 if (cpu != boot_cpuid)
148 xics_setup_cpu();
149
1ababe11 150 if (firmware_has_feature(FW_FEATURE_SPLPAR))
1da177e4
LT
151 vpa_init(cpu);
152
153 cpu_clear(cpu, of_spin_map);
154
1da177e4 155}
cebf589c 156#endif /* CONFIG_XICS */
1da177e4
LT
157
158static DEFINE_SPINLOCK(timebase_lock);
159static unsigned long timebase = 0;
160
161static void __devinit pSeries_give_timebase(void)
162{
163 spin_lock(&timebase_lock);
164 rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL);
165 timebase = get_tb();
166 spin_unlock(&timebase_lock);
167
168 while (timebase)
169 barrier();
170 rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL);
171}
172
173static void __devinit pSeries_take_timebase(void)
174{
175 while (!timebase)
176 barrier();
177 spin_lock(&timebase_lock);
178 set_tb(timebase >> 32, timebase & 0xffffffff);
179 timebase = 0;
180 spin_unlock(&timebase_lock);
181}
182
183static void __devinit smp_pSeries_kick_cpu(int nr)
184{
185 BUG_ON(nr < 0 || nr >= NR_CPUS);
186
187 if (!smp_startup_cpu(nr))
188 return;
189
190 /*
191 * The processor is currently spinning, waiting for the
192 * cpu_start field to become non-zero After we set cpu_start,
193 * the processor will continue on to secondary_start
194 */
195 paca[nr].cpu_start = 1;
196}
197
198static int smp_pSeries_cpu_bootable(unsigned int nr)
199{
200 /* Special case - we inhibit secondary thread startup
201 * during boot if the user requests it. Odd-numbered
202 * cpus are assumed to be secondary threads.
203 */
204 if (system_state < SYSTEM_RUNNING &&
0231c290 205 cpu_has_feature(CPU_FTR_SMT) &&
8d089085 206 !smt_enabled_at_boot && cpu_thread_in_core(nr) != 0)
1da177e4
LT
207 return 0;
208
209 return 1;
210}
cebf589c 211#ifdef CONFIG_MPIC
1da177e4
LT
212static struct smp_ops_t pSeries_mpic_smp_ops = {
213 .message_pass = smp_mpic_message_pass,
214 .probe = smp_mpic_probe,
215 .kick_cpu = smp_pSeries_kick_cpu,
216 .setup_cpu = smp_mpic_setup_cpu,
217};
cebf589c
AB
218#endif
219#ifdef CONFIG_XICS
1da177e4
LT
220static struct smp_ops_t pSeries_xics_smp_ops = {
221 .message_pass = smp_xics_message_pass,
222 .probe = smp_xics_probe,
223 .kick_cpu = smp_pSeries_kick_cpu,
224 .setup_cpu = smp_xics_setup_cpu,
225 .cpu_bootable = smp_pSeries_cpu_bootable,
226};
cebf589c 227#endif
1da177e4
LT
228
229/* This is called very early */
0ebfff14 230static void __init smp_init_pseries(void)
1da177e4
LT
231{
232 int i;
233
234 DBG(" -> smp_init_pSeries()\n");
235
1da177e4 236 /* Mark threads which are still spinning in hold loops. */
0231c290
AB
237 if (cpu_has_feature(CPU_FTR_SMT)) {
238 for_each_present_cpu(i) {
1da177e4
LT
239 if (i % 2 == 0)
240 /*
241 * Even-numbered logical cpus correspond to
242 * primary threads.
243 */
244 cpu_set(i, of_spin_map);
245 }
0231c290 246 } else {
1da177e4 247 of_spin_map = cpu_present_map;
0231c290 248 }
1da177e4
LT
249
250 cpu_clear(boot_cpuid, of_spin_map);
251
252 /* Non-lpar has additional take/give timebase */
253 if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) {
254 smp_ops->give_timebase = pSeries_give_timebase;
255 smp_ops->take_timebase = pSeries_take_timebase;
256 }
257
258 DBG(" <- smp_init_pSeries()\n");
259}
260
0ebfff14
BH
261#ifdef CONFIG_MPIC
262void __init smp_init_pseries_mpic(void)
263{
264 smp_ops = &pSeries_mpic_smp_ops;
265
266 smp_init_pseries();
267}
268#endif
269
270void __init smp_init_pseries_xics(void)
271{
272 smp_ops = &pSeries_xics_smp_ops;
273
274 smp_init_pseries();
275}