[net-next-2.6.git] / arch / powerpc / platforms / chrp / setup.c

/*
 *  Copyright (C) 1995  Linus Torvalds
 *  Adapted from 'alpha' version by Gary Thomas
 *  Modified by Cort Dougan (cort@cs.nmt.edu)
 */

/*
 * bootup setup stuff..
 */

#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/stddef.h>
#include <linux/unistd.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/user.h>
#include <linux/a.out.h>
#include <linux/tty.h>
#include <linux/major.h>
#include <linux/interrupt.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/version.h>
#include <linux/adb.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/ide.h>
#include <linux/console.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <linux/initrd.h>
#include <linux/module.h>
#include <linux/timer.h>

#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/prom.h>
#include <asm/gg2.h>
#include <asm/pci-bridge.h>
#include <asm/dma.h>
#include <asm/machdep.h>
#include <asm/irq.h>
#include <asm/hydra.h>
#include <asm/sections.h>
#include <asm/time.h>
#include <asm/i8259.h>
#include <asm/mpic.h>
#include <asm/rtas.h>
#include <asm/xmon.h>

#include "chrp.h"

void rtas_indicator_progress(char *, unsigned short);

int _chrp_type;
EXPORT_SYMBOL(_chrp_type);

struct mpic *chrp_mpic;

/* Used for doing CHRP event-scans */
DEFINE_PER_CPU(struct timer_list, heartbeat_timer);
unsigned long event_scan_interval;

/*
 * XXX this should be in xmon.h, but putting it there means xmon.h
 * has to include <linux/interrupt.h> (to get irqreturn_t), which
 * causes all sorts of problems.  -- paulus
 */
extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);

extern unsigned long loops_per_jiffy;

#ifdef CONFIG_SMP
extern struct smp_ops_t chrp_smp_ops;
#endif

static const char *gg2_memtypes[4] = {
	"FPM", "SDRAM", "EDO", "BEDO"
};
static const char *gg2_cachesizes[4] = {
	"256 KB", "512 KB", "1 MB", "Reserved"
};
static const char *gg2_cachetypes[4] = {
	"Asynchronous", "Reserved", "Flow-Through Synchronous",
	"Pipelined Synchronous"
};
static const char *gg2_cachemodes[4] = {
	"Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
};

void chrp_show_cpuinfo(struct seq_file *m)
{
	int i, sdramen;
	unsigned int t;
	struct device_node *root;
	const char *model = "";

	root = find_path_device("/");
	if (root)
		model = get_property(root, "model", NULL);
	seq_printf(m, "machine\t\t: CHRP %s\n", model);

	/* longtrail (goldengate) stuff */
	if (!strncmp(model, "IBM,LongTrail", 13)) {
		/* VLSI VAS96011/12 `Golden Gate 2' */
		/* Memory banks */
		sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
			   >>31) & 1;
		for (i = 0; i < (sdramen ? 4 : 6); i++) {
			t = in_le32(gg2_pci_config_base+
						 GG2_PCI_DRAM_BANK0+
						 i*4);
			if (!(t & 1))
				continue;
			switch ((t>>8) & 0x1f) {
			case 0x1f:
				model = "4 MB";
				break;
			case 0x1e:
				model = "8 MB";
				break;
			case 0x1c:
				model = "16 MB";
				break;
			case 0x18:
				model = "32 MB";
				break;
			case 0x10:
				model = "64 MB";
				break;
			case 0x00:
				model = "128 MB";
				break;
			default:
				model = "Reserved";
				break;
			}
			seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
				   gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
		}
		/* L2 cache */
		t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
		seq_printf(m, "board l2\t: %s %s (%s)\n",
			   gg2_cachesizes[(t>>7) & 3],
			   gg2_cachetypes[(t>>2) & 3],
			   gg2_cachemodes[t & 3]);
	}
}

/*
 *  Fixes for the National Semiconductor PC78308VUL SuperI/O
 *
 *  Some versions of Open Firmware incorrectly initialize the IRQ settings
 *  for keyboard and mouse
 */
static inline void __init sio_write(u8 val, u8 index)
{
	outb(index, 0x15c);
	outb(val, 0x15d);
}

static inline u8 __init sio_read(u8 index)
{
	outb(index, 0x15c);
	return inb(0x15d);
}

static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
				     u8 type)
{
	u8 level0, type0, active;

	/* select logical device */
	sio_write(device, 0x07);
	active = sio_read(0x30);
	level0 = sio_read(0x70);
	type0 = sio_read(0x71);
	if (level0 != level || type0 != type || !active) {
		printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
		       "remapping to level %d, type %d, active\n",
		       name, level0, type0, !active ? "in" : "", level, type);
		sio_write(0x01, 0x30);
		sio_write(level, 0x70);
		sio_write(type, 0x71);
	}
}

static void __init sio_init(void)
{
	struct device_node *root;

	if ((root = find_path_device("/")) &&
	    !strncmp(get_property(root, "model", NULL), "IBM,LongTrail", 13)) {
		/* logical device 0 (KBC/Keyboard) */
		sio_fixup_irq("keyboard", 0, 1, 2);
		/* select logical device 1 (KBC/Mouse) */
		sio_fixup_irq("mouse", 1, 12, 2);
	}
}


static void __init pegasos_set_l2cr(void)
{
	struct device_node *np;

	/* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
	if (_chrp_type != _CHRP_Pegasos)
		return;

	/* Enable L2 cache if needed */
	np = find_type_devices("cpu");
	if (np != NULL) {
		unsigned int *l2cr = (unsigned int *)
			get_property (np, "l2cr", NULL);
		if (l2cr == NULL) {
			printk ("Pegasos l2cr : no cpu l2cr property found\n");
			return;
		}
		if (!((*l2cr) & 0x80000000)) {
			printk ("Pegasos l2cr : L2 cache was not active, "
				"activating\n");
			_set_L2CR(0);
			_set_L2CR((*l2cr) | 0x80000000);
		}
	}
}

void __init chrp_setup_arch(void)
{
	struct device_node *root = find_path_device ("/");
	char *machine = NULL;

	/* init to some ~sane value until calibrate_delay() runs */
	loops_per_jiffy = 50000000/HZ;

	if (root)
		machine = get_property(root, "model", NULL);
	if (machine && strncmp(machine, "Pegasos", 7) == 0) {
		_chrp_type = _CHRP_Pegasos;
	} else if (machine && strncmp(machine, "IBM", 3) == 0) {
		_chrp_type = _CHRP_IBM;
	} else if (machine && strncmp(machine, "MOT", 3) == 0) {
		_chrp_type = _CHRP_Motorola;
	} else {
		/* Let's assume it is an IBM chrp if all else fails */
		_chrp_type = _CHRP_IBM;
	}
	printk("chrp type = %x\n", _chrp_type);

	rtas_initialize();
	if (rtas_token("display-character") >= 0)
		ppc_md.progress = rtas_progress;

	/* use RTAS time-of-day routines if available */
	if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
		ppc_md.get_boot_time	= rtas_get_boot_time;
		ppc_md.get_rtc_time	= rtas_get_rtc_time;
		ppc_md.set_rtc_time	= rtas_set_rtc_time;
	}

#ifdef CONFIG_BLK_DEV_INITRD
	/* this is fine for chrp */
	initrd_below_start_ok = 1;

	if (initrd_start)
		ROOT_DEV = Root_RAM0;
	else
#endif
		ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */

	/* On pegasos, enable the L2 cache if not already done by OF */
	pegasos_set_l2cr();

	/* Lookup PCI host bridges */
	chrp_find_bridges();

	/*
	 *  Temporary fixes for PCI devices.
	 *  -- Geert
	 */
	hydra_init();		/* Mac I/O */

	/*
	 *  Fix the Super I/O configuration
	 */
	sio_init();

	pci_create_OF_bus_map();

#ifdef CONFIG_SMP
	smp_ops = &chrp_smp_ops;
#endif /* CONFIG_SMP */

	/*
	 * Print the banner, then scroll down so boot progress
	 * can be printed.  -- Cort
	 */
	if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
}

void
chrp_event_scan(unsigned long unused)
{
	unsigned char log[1024];
	int ret = 0;

	/* XXX: we should loop until the hardware says no more error logs -- Cort */
	rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0,
		  __pa(log), 1024);
	mod_timer(&__get_cpu_var(heartbeat_timer),
		  jiffies + event_scan_interval);
}

void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc,
			struct pt_regs *regs)
{
	unsigned int max = 100;

	while(max--) {
		int irq = i8259_irq(regs);
		if (max == 99)
			desc->chip->eoi(irq);
		if (irq < 0)
			break;
		generic_handle_irq(irq, regs);
	};
}

/*
 * Finds the open-pic node and sets up the mpic driver.
 */
static void __init chrp_find_openpic(void)
{
	struct device_node *np, *root;
	int len, i, j, irq_count;
	int isu_size, idu_size;
	unsigned int *iranges, *opprop = NULL;
	int oplen = 0;
	unsigned long opaddr;
	int na = 1;
	unsigned char init_senses[NR_IRQS - NUM_8259_INTERRUPTS];

	np = find_type_devices("open-pic");
	if (np == NULL)
		return;
	root = find_path_device("/");
	if (root) {
		opprop = (unsigned int *) get_property
			(root, "platform-open-pic", &oplen);
		na = prom_n_addr_cells(root);
	}
	if (opprop && oplen >= na * sizeof(unsigned int)) {
		opaddr = opprop[na-1];	/* assume 32-bit */
		oplen /= na * sizeof(unsigned int);
	} else {
		struct resource r;
		if (of_address_to_resource(np, 0, &r))
			return;
		opaddr = r.start;
		oplen = 0;
	}

	printk(KERN_INFO "OpenPIC at %lx\n", opaddr);

	irq_count = NR_IRQS - NUM_ISA_INTERRUPTS - 4; /* leave room for IPIs */
	prom_get_irq_senses(init_senses, NUM_ISA_INTERRUPTS, NR_IRQS - 4);
	/* i8259 cascade is always positive level */
	init_senses[0] = IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE;

	iranges = (unsigned int *) get_property(np, "interrupt-ranges", &len);
	if (iranges == NULL)
		len = 0;	/* non-distributed mpic */
	else
		len /= 2 * sizeof(unsigned int);

	/*
	 * The first pair of cells in interrupt-ranges refers to the
	 * IDU; subsequent pairs refer to the ISUs.
	 */
	if (oplen < len) {
		printk(KERN_ERR "Insufficient addresses for distributed"
		       " OpenPIC (%d < %d)\n", oplen, len);
		len = oplen;
	}

	isu_size = 0;
	idu_size = 0;
	if (len > 0 && iranges[1] != 0) {
		printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
		       iranges[0], iranges[0] + iranges[1] - 1);
		idu_size = iranges[1];
	}
	if (len > 1)
		isu_size = iranges[3];

	chrp_mpic = mpic_alloc(opaddr, MPIC_PRIMARY,
			       isu_size, NUM_ISA_INTERRUPTS, irq_count,
			       NR_IRQS - 4, init_senses, irq_count,
			       " MPIC    ");
	if (chrp_mpic == NULL) {
		printk(KERN_ERR "Failed to allocate MPIC structure\n");
		return;
	}

	j = na - 1;
	for (i = 1; i < len; ++i) {
		iranges += 2;
		j += na;
		printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
		       iranges[0], iranges[0] + iranges[1] - 1,
		       opprop[j]);
		mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
	}

	mpic_init(chrp_mpic);
	set_irq_chained_handler(NUM_ISA_INTERRUPTS, chrp_8259_cascade);
}

#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
static struct irqaction xmon_irqaction = {
	.handler = xmon_irq,
	.mask = CPU_MASK_NONE,
	.name = "XMON break",
};
#endif

void __init chrp_init_IRQ(void)
{
	struct device_node *np;
	unsigned long chrp_int_ack = 0;
#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
	struct device_node *kbd;
#endif

	for (np = find_devices("pci"); np != NULL; np = np->next) {
		unsigned int *addrp = (unsigned int *)
			get_property(np, "8259-interrupt-acknowledge", NULL);

		if (addrp == NULL)
			continue;
		chrp_int_ack = addrp[prom_n_addr_cells(np)-1];
		break;
	}
	if (np == NULL)
		printk(KERN_ERR "Cannot find PCI interrupt acknowledge address\n");

	chrp_find_openpic();

	i8259_init(chrp_int_ack, 0);

	if (_chrp_type == _CHRP_Pegasos)
		ppc_md.get_irq        = i8259_irq;

#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
	/* see if there is a keyboard in the device tree
	   with a parent of type "adb" */
	for (kbd = find_devices("keyboard"); kbd; kbd = kbd->next)
		if (kbd->parent && kbd->parent->type
		    && strcmp(kbd->parent->type, "adb") == 0)
			break;
	if (kbd)
		setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
#endif
}

void __init
chrp_init2(void)
{
	struct device_node *device;
	unsigned int *p = NULL;

#ifdef CONFIG_NVRAM
	chrp_nvram_init();
#endif

	request_region(0x20,0x20,"pic1");
	request_region(0xa0,0x20,"pic2");
	request_region(0x00,0x20,"dma1");
	request_region(0x40,0x20,"timer");
	request_region(0x80,0x10,"dma page reg");
	request_region(0xc0,0x20,"dma2");

	/* Get the event scan rate for the rtas so we know how
	 * often it expects a heartbeat. -- Cort
	 */
	device = find_devices("rtas");
	if (device)
		p = (unsigned int *) get_property
			(device, "rtas-event-scan-rate", NULL);
	if (p && *p) {
		/*
		 * Arrange to call chrp_event_scan at least *p times
		 * per minute.  We use 59 rather than 60 here so that
		 * the rate will be slightly higher than the minimum.
		 * This all assumes we don't do hotplug CPU on any
		 * machine that needs the event scans done.
		 */
		unsigned long interval, offset;
		int cpu, ncpus;
		struct timer_list *timer;

		interval = HZ * 59 / *p;
		offset = HZ;
		ncpus = num_online_cpus();
		event_scan_interval = ncpus * interval;
		for (cpu = 0; cpu < ncpus; ++cpu) {
			timer = &per_cpu(heartbeat_timer, cpu);
			setup_timer(timer, chrp_event_scan, 0);
			timer->expires = jiffies + offset;
			add_timer_on(timer, cpu);
			offset += interval;
		}
		printk("RTAS Event Scan Rate: %u (%lu jiffies)\n",
		       *p, interval);
	}

	if (ppc_md.progress)
		ppc_md.progress("  Have fun!    ", 0x7777);
}

static int __init chrp_probe(void)
{
 	char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(),
 					  "device_type", NULL);
 	if (dtype == NULL)
 		return 0;
 	if (strcmp(dtype, "chrp"))
		return 0;

	ISA_DMA_THRESHOLD = ~0L;
	DMA_MODE_READ = 0x44;
	DMA_MODE_WRITE = 0x48;
	isa_io_base = CHRP_ISA_IO_BASE;		/* default value */
	ppc_do_canonicalize_irqs = 1;

	/* Assume we have an 8259... */
	__irq_offset_value = NUM_ISA_INTERRUPTS;

	return 1;
}

define_machine(chrp) {
	.name			= "CHRP",
	.probe			= chrp_probe,
	.setup_arch		= chrp_setup_arch,
	.init			= chrp_init2,
	.show_cpuinfo		= chrp_show_cpuinfo,
	.init_IRQ		= chrp_init_IRQ,
	.get_irq		= mpic_get_irq,
	.pcibios_fixup		= chrp_pcibios_fixup,
	.restart		= rtas_restart,
	.power_off		= rtas_power_off,
	.halt			= rtas_halt,
	.time_init		= chrp_time_init,
	.set_rtc_time		= chrp_set_rtc_time,
	.get_rtc_time		= chrp_get_rtc_time,
	.calibrate_decr		= generic_calibrate_decr,
	.phys_mem_access_prot	= pci_phys_mem_access_prot,
};
Commit	Line	Data
bbd0abda	1	/*
bbd0abda PM	2	* Copyright (C) 1995 Linus Torvalds
	3	* Adapted from 'alpha' version by Gary Thomas
	4	* Modified by Cort Dougan (cort@cs.nmt.edu)
	5	*/
	6
	7	/*
	8	* bootup setup stuff..
	9	*/
	10
bbd0abda PM	11	#include <linux/errno.h>
	12	#include <linux/sched.h>
	13	#include <linux/kernel.h>
	14	#include <linux/mm.h>
	15	#include <linux/stddef.h>
	16	#include <linux/unistd.h>
	17	#include <linux/ptrace.h>
	18	#include <linux/slab.h>
	19	#include <linux/user.h>
	20	#include <linux/a.out.h>
	21	#include <linux/tty.h>
	22	#include <linux/major.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/reboot.h>
	25	#include <linux/init.h>
	26	#include <linux/pci.h>
	27	#include <linux/version.h>
	28	#include <linux/adb.h>
	29	#include <linux/module.h>
	30	#include <linux/delay.h>
	31	#include <linux/ide.h>
	32	#include <linux/console.h>
	33	#include <linux/seq_file.h>
	34	#include <linux/root_dev.h>
	35	#include <linux/initrd.h>
	36	#include <linux/module.h>
9618edab	37	#include <linux/timer.h>
bbd0abda PM	38
	39	#include <asm/io.h>
	40	#include <asm/pgtable.h>
	41	#include <asm/prom.h>
	42	#include <asm/gg2.h>
	43	#include <asm/pci-bridge.h>
	44	#include <asm/dma.h>
	45	#include <asm/machdep.h>
	46	#include <asm/irq.h>
	47	#include <asm/hydra.h>
	48	#include <asm/sections.h>
	49	#include <asm/time.h>
bbd0abda PM	50	#include <asm/i8259.h>
	51	#include <asm/mpic.h>
	52	#include <asm/rtas.h>
	53	#include <asm/xmon.h>
	54
35e95e63	55	#include "chrp.h"
bbd0abda	56
bbd0abda	57	void rtas_indicator_progress(char *, unsigned short);
bbd0abda PM	58
	59	int _chrp_type;
	60	EXPORT_SYMBOL(_chrp_type);
	61
	62	struct mpic *chrp_mpic;
	63
9618edab PM	64	/* Used for doing CHRP event-scans */
	65	DEFINE_PER_CPU(struct timer_list, heartbeat_timer);
	66	unsigned long event_scan_interval;
	67
bbd0abda PM	68	/*
	69	* XXX this should be in xmon.h, but putting it there means xmon.h
	70	* has to include <linux/interrupt.h> (to get irqreturn_t), which
	71	* causes all sorts of problems. -- paulus
	72	*/
	73	extern irqreturn_t xmon_irq(int, void , struct pt_regs );
	74
	75	extern unsigned long loops_per_jiffy;
	76
	77	#ifdef CONFIG_SMP
	78	extern struct smp_ops_t chrp_smp_ops;
	79	#endif
	80
	81	static const char *gg2_memtypes[4] = {
	82	"FPM", "SDRAM", "EDO", "BEDO"
	83	};
	84	static const char *gg2_cachesizes[4] = {
	85	"256 KB", "512 KB", "1 MB", "Reserved"
	86	};
	87	static const char *gg2_cachetypes[4] = {
	88	"Asynchronous", "Reserved", "Flow-Through Synchronous",
	89	"Pipelined Synchronous"
	90	};
	91	static const char *gg2_cachemodes[4] = {
	92	"Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
	93	};
	94
	95	void chrp_show_cpuinfo(struct seq_file *m)
	96	{
	97	int i, sdramen;
	98	unsigned int t;
	99	struct device_node *root;
	100	const char *model = "";
	101
	102	root = find_path_device("/");
	103	if (root)
	104	model = get_property(root, "model", NULL);
	105	seq_printf(m, "machine\t\t: CHRP %s\n", model);
	106
	107	/* longtrail (goldengate) stuff */
	108	if (!strncmp(model, "IBM,LongTrail", 13)) {
	109	/* VLSI VAS96011/12 `Golden Gate 2' */
	110	/* Memory banks */
	111	sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
	112	>>31) & 1;
	113	for (i = 0; i < (sdramen ? 4 : 6); i++) {
	114	t = in_le32(gg2_pci_config_base+
	115	GG2_PCI_DRAM_BANK0+
	116	i*4);
	117	if (!(t & 1))
	118	continue;
	119	switch ((t>>8) & 0x1f) {
	120	case 0x1f:
	121	model = "4 MB";
	122	break;
	123	case 0x1e:
	124	model = "8 MB";
	125	break;
	126	case 0x1c:
	127	model = "16 MB";
	128	break;
	129	case 0x18:
	130	model = "32 MB";
	131	break;
132	case 0x10:
133	model = "64 MB";
134	break;
135	case 0x00:
136	model = "128 MB";
137	break;
138	default:
139	model = "Reserved";
140	break;
141	}
142	seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
143	gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
144	}
145	/* L2 cache */
146	t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
147	seq_printf(m, "board l2\t: %s %s (%s)\n",
148	gg2_cachesizes[(t>>7) & 3],
149	gg2_cachetypes[(t>>2) & 3],
150	gg2_cachemodes[t & 3]);
151	}
152	}
153
154	/*
155	* Fixes for the National Semiconductor PC78308VUL SuperI/O
156	*
157	* Some versions of Open Firmware incorrectly initialize the IRQ settings
158	* for keyboard and mouse
159	*/
160	static inline void __init sio_write(u8 val, u8 index)
161	{
162	outb(index, 0x15c);
163	outb(val, 0x15d);
164	}
165
166	static inline u8 __init sio_read(u8 index)
167	{
168	outb(index, 0x15c);
169	return inb(0x15d);
170	}
171
172	static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
173	u8 type)
174	{
175	u8 level0, type0, active;
176
177	/* select logical device */
178	sio_write(device, 0x07);
179	active = sio_read(0x30);
180	level0 = sio_read(0x70);
181	type0 = sio_read(0x71);
182	if (level0 != level \|\| type0 != type \|\| !active) {
183	printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
184	"remapping to level %d, type %d, active\n",
185	name, level0, type0, !active ? "in" : "", level, type);
186	sio_write(0x01, 0x30);
187	sio_write(level, 0x70);
188	sio_write(type, 0x71);
189	}
190	}
191
192	static void __init sio_init(void)
193	{
194	struct device_node *root;
195
196	if ((root = find_path_device("/")) &&
197	!strncmp(get_property(root, "model", NULL), "IBM,LongTrail", 13)) {
198	/* logical device 0 (KBC/Keyboard) */
199	sio_fixup_irq("keyboard", 0, 1, 2);
200	/* select logical device 1 (KBC/Mouse) */
201	sio_fixup_irq("mouse", 1, 12, 2);
202	}
203	}
204
205
206	static void __init pegasos_set_l2cr(void)
207	{
208	struct device_node *np;
209
210	/* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
211	if (_chrp_type != _CHRP_Pegasos)
212	return;
213
214	/* Enable L2 cache if needed */
215	np = find_type_devices("cpu");
216	if (np != NULL) {
217	unsigned int l2cr = (unsigned int )
218	get_property (np, "l2cr", NULL);
219	if (l2cr == NULL) {
220	printk ("Pegasos l2cr : no cpu l2cr property found\n");
221	return;
222	}
223	if (!((*l2cr) & 0x80000000)) {
224	printk ("Pegasos l2cr : L2 cache was not active, "
225	"activating\n");
226	_set_L2CR(0);
227	_set_L2CR((*l2cr) \| 0x80000000);
228	}
229	}
230	}
231
232	void __init chrp_setup_arch(void)
233	{
234	struct device_node *root = find_path_device ("/");
235	char *machine = NULL;
bbd0abda PM	236
	237	/* init to some ~sane value until calibrate_delay() runs */
	238	loops_per_jiffy = 50000000/HZ;
	239
	240	if (root)
	241	machine = get_property(root, "model", NULL);
	242	if (machine && strncmp(machine, "Pegasos", 7) == 0) {
	243	_chrp_type = _CHRP_Pegasos;
	244	} else if (machine && strncmp(machine, "IBM", 3) == 0) {
	245	_chrp_type = _CHRP_IBM;
	246	} else if (machine && strncmp(machine, "MOT", 3) == 0) {
	247	_chrp_type = _CHRP_Motorola;
	248	} else {
	249	/* Let's assume it is an IBM chrp if all else fails */
	250	_chrp_type = _CHRP_IBM;
	251	}
	252	printk("chrp type = %x\n", _chrp_type);
	253
	254	rtas_initialize();
	255	if (rtas_token("display-character") >= 0)
	256	ppc_md.progress = rtas_progress;
	257
49e16b7b PM	258	/* use RTAS time-of-day routines if available */
	259	if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
	260	ppc_md.get_boot_time = rtas_get_boot_time;
	261	ppc_md.get_rtc_time = rtas_get_rtc_time;
	262	ppc_md.set_rtc_time = rtas_set_rtc_time;
	263	}
	264
bbd0abda PM	265	#ifdef CONFIG_BLK_DEV_INITRD
	266	/* this is fine for chrp */
	267	initrd_below_start_ok = 1;
	268
	269	if (initrd_start)
	270	ROOT_DEV = Root_RAM0;
	271	else
	272	#endif
	273	ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */
	274
	275	/* On pegasos, enable the L2 cache if not already done by OF */
	276	pegasos_set_l2cr();
	277
	278	/* Lookup PCI host bridges */
	279	chrp_find_bridges();
	280
	281	/*
	282	* Temporary fixes for PCI devices.
	283	* -- Geert
	284	*/
	285	hydra_init(); /* Mac I/O */
	286
	287	/*
	288	* Fix the Super I/O configuration
	289	*/
	290	sio_init();
	291
bbd0abda PM	292	pci_create_OF_bus_map();
bbd0abda PM	293
e8222502 BH	294	#ifdef CONFIG_SMP
	295	smp_ops = &chrp_smp_ops;
	296	#endif /* CONFIG_SMP */
	297
bbd0abda PM	298	/*
	299	* Print the banner, then scroll down so boot progress
	300	* can be printed. -- Cort
	301	*/
	302	if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
	303	}
	304
	305	void
9618edab	306	chrp_event_scan(unsigned long unused)
bbd0abda PM	307	{
	308	unsigned char log[1024];
	309	int ret = 0;
	310
	311	/* XXX: we should loop until the hardware says no more error logs -- Cort */
	312	rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0,
	313	__pa(log), 1024);
9618edab PM	314	mod_timer(&__get_cpu_var(heartbeat_timer),
9618edab PM	315	jiffies + event_scan_interval);
bbd0abda PM	316	}
bbd0abda PM	317
b9e5b4e6 BH	318	void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc,
	319	struct pt_regs *regs)
	320	{
	321	unsigned int max = 100;
	322
	323	while(max--) {
	324	int irq = i8259_irq(regs);
	325	if (max == 99)
	326	desc->chip->eoi(irq);
	327	if (irq < 0)
	328	break;
	329	generic_handle_irq(irq, regs);
	330	};
	331	}
	332
bbd0abda PM	333	/*
	334	* Finds the open-pic node and sets up the mpic driver.
	335	*/
	336	static void __init chrp_find_openpic(void)
	337	{
	338	struct device_node np, root;
	339	int len, i, j, irq_count;
	340	int isu_size, idu_size;
	341	unsigned int iranges, opprop = NULL;
	342	int oplen = 0;
	343	unsigned long opaddr;
	344	int na = 1;
	345	unsigned char init_senses[NR_IRQS - NUM_8259_INTERRUPTS];
	346
	347	np = find_type_devices("open-pic");
	348	if (np == NULL)
	349	return;
	350	root = find_path_device("/");
	351	if (root) {
	352	opprop = (unsigned int *) get_property
	353	(root, "platform-open-pic", &oplen);
	354	na = prom_n_addr_cells(root);
	355	}
	356	if (opprop && oplen >= na * sizeof(unsigned int)) {
	357	opaddr = opprop[na-1]; /* assume 32-bit */
	358	oplen /= na * sizeof(unsigned int);
	359	} else {
575e3216 DW	360	struct resource r;
575e3216 DW	361	if (of_address_to_resource(np, 0, &r))
bbd0abda	362	return;
575e3216	363	opaddr = r.start;
bbd0abda PM	364	oplen = 0;
	365	}
	366
	367	printk(KERN_INFO "OpenPIC at %lx\n", opaddr);
	368
	369	irq_count = NR_IRQS - NUM_ISA_INTERRUPTS - 4; /* leave room for IPIs */
a23414be PM	370	prom_get_irq_senses(init_senses, NUM_ISA_INTERRUPTS, NR_IRQS - 4);
	371	/* i8259 cascade is always positive level */
	372	init_senses[0] = IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE;
bbd0abda PM	373
	374	iranges = (unsigned int *) get_property(np, "interrupt-ranges", &len);
	375	if (iranges == NULL)
	376	len = 0; /* non-distributed mpic */
	377	else
	378	len /= 2 * sizeof(unsigned int);
	379
	380	/*
	381	* The first pair of cells in interrupt-ranges refers to the
	382	* IDU; subsequent pairs refer to the ISUs.
	383	*/
	384	if (oplen < len) {
	385	printk(KERN_ERR "Insufficient addresses for distributed"
575e3216	386	" OpenPIC (%d < %d)\n", oplen, len);
bbd0abda PM	387	len = oplen;
	388	}
	389
	390	isu_size = 0;
	391	idu_size = 0;
	392	if (len > 0 && iranges[1] != 0) {
	393	printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
	394	iranges[0], iranges[0] + iranges[1] - 1);
	395	idu_size = iranges[1];
	396	}
	397	if (len > 1)
	398	isu_size = iranges[3];
	399
	400	chrp_mpic = mpic_alloc(opaddr, MPIC_PRIMARY,
	401	isu_size, NUM_ISA_INTERRUPTS, irq_count,
	402	NR_IRQS - 4, init_senses, irq_count,
	403	" MPIC ");
	404	if (chrp_mpic == NULL) {
	405	printk(KERN_ERR "Failed to allocate MPIC structure\n");
	406	return;
	407	}
	408
	409	j = na - 1;
	410	for (i = 1; i < len; ++i) {
	411	iranges += 2;
	412	j += na;
	413	printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
	414	iranges[0], iranges[0] + iranges[1] - 1,
	415	opprop[j]);
	416	mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
	417	}
	418
	419	mpic_init(chrp_mpic);
b9e5b4e6	420	set_irq_chained_handler(NUM_ISA_INTERRUPTS, chrp_8259_cascade);
bbd0abda PM	421	}
	422
	423	#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
	424	static struct irqaction xmon_irqaction = {
	425	.handler = xmon_irq,
	426	.mask = CPU_MASK_NONE,
	427	.name = "XMON break",
	428	};
	429	#endif
	430
	431	void __init chrp_init_IRQ(void)
	432	{
	433	struct device_node *np;
	434	unsigned long chrp_int_ack = 0;
	435	#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
	436	struct device_node *kbd;
	437	#endif
	438
	439	for (np = find_devices("pci"); np != NULL; np = np->next) {
	440	unsigned int addrp = (unsigned int )
	441	get_property(np, "8259-interrupt-acknowledge", NULL);
	442
	443	if (addrp == NULL)
	444	continue;
	445	chrp_int_ack = addrp[prom_n_addr_cells(np)-1];
	446	break;
	447	}
	448	if (np == NULL)
	449	printk(KERN_ERR "Cannot find PCI interrupt acknowledge address\n");
	450
	451	chrp_find_openpic();
	452
	453	i8259_init(chrp_int_ack, 0);
	454
	455	if (_chrp_type == _CHRP_Pegasos)
	456	ppc_md.get_irq = i8259_irq;
bbd0abda PM	457
	458	#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
	459	/* see if there is a keyboard in the device tree
	460	with a parent of type "adb" */
	461	for (kbd = find_devices("keyboard"); kbd; kbd = kbd->next)
	462	if (kbd->parent && kbd->parent->type
	463	&& strcmp(kbd->parent->type, "adb") == 0)
	464	break;
	465	if (kbd)
	466	setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
	467	#endif
	468	}
	469
	470	void __init
	471	chrp_init2(void)
	472	{
9618edab PM	473	struct device_node *device;
	474	unsigned int *p = NULL;
	475
35e95e63 OH	476	#ifdef CONFIG_NVRAM
	477	chrp_nvram_init();
	478	#endif
	479
bbd0abda PM	480	request_region(0x20,0x20,"pic1");
	481	request_region(0xa0,0x20,"pic2");
	482	request_region(0x00,0x20,"dma1");
	483	request_region(0x40,0x20,"timer");
	484	request_region(0x80,0x10,"dma page reg");
	485	request_region(0xc0,0x20,"dma2");
	486
9618edab PM	487	/* Get the event scan rate for the rtas so we know how
	488	* often it expects a heartbeat. -- Cort
	489	*/
	490	device = find_devices("rtas");
	491	if (device)
	492	p = (unsigned int *) get_property
	493	(device, "rtas-event-scan-rate", NULL);
	494	if (p && *p) {
	495	/*
	496	* Arrange to call chrp_event_scan at least *p times
	497	* per minute. We use 59 rather than 60 here so that
	498	* the rate will be slightly higher than the minimum.
	499	* This all assumes we don't do hotplug CPU on any
	500	* machine that needs the event scans done.
	501	*/
	502	unsigned long interval, offset;
	503	int cpu, ncpus;
	504	struct timer_list *timer;
	505
	506	interval = HZ * 59 / *p;
	507	offset = HZ;
	508	ncpus = num_online_cpus();
	509	event_scan_interval = ncpus * interval;
	510	for (cpu = 0; cpu < ncpus; ++cpu) {
	511	timer = &per_cpu(heartbeat_timer, cpu);
	512	setup_timer(timer, chrp_event_scan, 0);
	513	timer->expires = jiffies + offset;
	514	add_timer_on(timer, cpu);
	515	offset += interval;
	516	}
	517	printk("RTAS Event Scan Rate: %u (%lu jiffies)\n",
	518	*p, interval);
	519	}
	520
bbd0abda PM	521	if (ppc_md.progress)
	522	ppc_md.progress(" Have fun! ", 0x7777);
	523	}
	524
e8222502	525	static int __init chrp_probe(void)
bbd0abda	526	{
e8222502 BH	527	char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(),
	528	"device_type", NULL);
	529	if (dtype == NULL)
	530	return 0;
	531	if (strcmp(dtype, "chrp"))
	532	return 0;
	533
bbd0abda PM	534	ISA_DMA_THRESHOLD = ~0L;
	535	DMA_MODE_READ = 0x44;
	536	DMA_MODE_WRITE = 0x48;
	537	isa_io_base = CHRP_ISA_IO_BASE; /* default value */
	538	ppc_do_canonicalize_irqs = 1;
	539
	540	/* Assume we have an 8259... */
	541	__irq_offset_value = NUM_ISA_INTERRUPTS;
	542
b86756ae	543	return 1;
bbd0abda	544	}
b86756ae PM	545
	546	define_machine(chrp) {
	547	.name = "CHRP",
	548	.probe = chrp_probe,
	549	.setup_arch = chrp_setup_arch,
	550	.init = chrp_init2,
	551	.show_cpuinfo = chrp_show_cpuinfo,
	552	.init_IRQ = chrp_init_IRQ,
	553	.get_irq = mpic_get_irq,
	554	.pcibios_fixup = chrp_pcibios_fixup,
	555	.restart = rtas_restart,
	556	.power_off = rtas_power_off,
	557	.halt = rtas_halt,
	558	.time_init = chrp_time_init,
	559	.set_rtc_time = chrp_set_rtc_time,
	560	.get_rtc_time = chrp_get_rtc_time,
	561	.calibrate_decr = generic_calibrate_decr,
	562	.phys_mem_access_prot = pci_phys_mem_access_prot,
	563	};