[net-next-2.6.git] / arch / powerpc / platforms / chrp / setup.c

/*
 *  Copyright (C) 1995  Linus Torvalds
 *  Adapted from 'alpha' version by Gary Thomas
 *  Modified by Cort Dougan (cort@cs.nmt.edu)
 */

/*
 * bootup setup stuff..
 */

#include <linux/config.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/stddef.h>
#include <linux/unistd.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/user.h>
#include <linux/a.out.h>
#include <linux/tty.h>
#include <linux/major.h>
#include <linux/interrupt.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/version.h>
#include <linux/adb.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/ide.h>
#include <linux/console.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <linux/initrd.h>
#include <linux/module.h>

#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/prom.h>
#include <asm/gg2.h>
#include <asm/pci-bridge.h>
#include <asm/dma.h>
#include <asm/machdep.h>
#include <asm/irq.h>
#include <asm/hydra.h>
#include <asm/sections.h>
#include <asm/time.h>
#include <asm/i8259.h>
#include <asm/mpic.h>
#include <asm/rtas.h>
#include <asm/xmon.h>

#include "chrp.h"

void rtas_indicator_progress(char *, unsigned short);

int _chrp_type;
EXPORT_SYMBOL(_chrp_type);

struct mpic *chrp_mpic;

/*
 * XXX this should be in xmon.h, but putting it there means xmon.h
 * has to include <linux/interrupt.h> (to get irqreturn_t), which
 * causes all sorts of problems.  -- paulus
 */
extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);

extern unsigned long loops_per_jiffy;

#ifdef CONFIG_SMP
extern struct smp_ops_t chrp_smp_ops;
#endif

static const char *gg2_memtypes[4] = {
	"FPM", "SDRAM", "EDO", "BEDO"
};
static const char *gg2_cachesizes[4] = {
	"256 KB", "512 KB", "1 MB", "Reserved"
};
static const char *gg2_cachetypes[4] = {
	"Asynchronous", "Reserved", "Flow-Through Synchronous",
	"Pipelined Synchronous"
};
static const char *gg2_cachemodes[4] = {
	"Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
};

void chrp_show_cpuinfo(struct seq_file *m)
{
	int i, sdramen;
	unsigned int t;
	struct device_node *root;
	const char *model = "";

	root = find_path_device("/");
	if (root)
		model = get_property(root, "model", NULL);
	seq_printf(m, "machine\t\t: CHRP %s\n", model);

	/* longtrail (goldengate) stuff */
	if (!strncmp(model, "IBM,LongTrail", 13)) {
		/* VLSI VAS96011/12 `Golden Gate 2' */
		/* Memory banks */
		sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
			   >>31) & 1;
		for (i = 0; i < (sdramen ? 4 : 6); i++) {
			t = in_le32(gg2_pci_config_base+
						 GG2_PCI_DRAM_BANK0+
						 i*4);
			if (!(t & 1))
				continue;
			switch ((t>>8) & 0x1f) {
			case 0x1f:
				model = "4 MB";
				break;
			case 0x1e:
				model = "8 MB";
				break;
			case 0x1c:
				model = "16 MB";
				break;
			case 0x18:
				model = "32 MB";
				break;
			case 0x10:
				model = "64 MB";
				break;
			case 0x00:
				model = "128 MB";
				break;
			default:
				model = "Reserved";
				break;
			}
			seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
				   gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
		}
		/* L2 cache */
		t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
		seq_printf(m, "board l2\t: %s %s (%s)\n",
			   gg2_cachesizes[(t>>7) & 3],
			   gg2_cachetypes[(t>>2) & 3],
			   gg2_cachemodes[t & 3]);
	}
}

/*
 *  Fixes for the National Semiconductor PC78308VUL SuperI/O
 *
 *  Some versions of Open Firmware incorrectly initialize the IRQ settings
 *  for keyboard and mouse
 */
static inline void __init sio_write(u8 val, u8 index)
{
	outb(index, 0x15c);
	outb(val, 0x15d);
}

static inline u8 __init sio_read(u8 index)
{
	outb(index, 0x15c);
	return inb(0x15d);
}

static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
				     u8 type)
{
	u8 level0, type0, active;

	/* select logical device */
	sio_write(device, 0x07);
	active = sio_read(0x30);
	level0 = sio_read(0x70);
	type0 = sio_read(0x71);
	if (level0 != level || type0 != type || !active) {
		printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
		       "remapping to level %d, type %d, active\n",
		       name, level0, type0, !active ? "in" : "", level, type);
		sio_write(0x01, 0x30);
		sio_write(level, 0x70);
		sio_write(type, 0x71);
	}
}

static void __init sio_init(void)
{
	struct device_node *root;

	if ((root = find_path_device("/")) &&
	    !strncmp(get_property(root, "model", NULL), "IBM,LongTrail", 13)) {
		/* logical device 0 (KBC/Keyboard) */
		sio_fixup_irq("keyboard", 0, 1, 2);
		/* select logical device 1 (KBC/Mouse) */
		sio_fixup_irq("mouse", 1, 12, 2);
	}
}


static void __init pegasos_set_l2cr(void)
{
	struct device_node *np;

	/* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
	if (_chrp_type != _CHRP_Pegasos)
		return;

	/* Enable L2 cache if needed */
	np = find_type_devices("cpu");
	if (np != NULL) {
		unsigned int *l2cr = (unsigned int *)
			get_property (np, "l2cr", NULL);
		if (l2cr == NULL) {
			printk ("Pegasos l2cr : no cpu l2cr property found\n");
			return;
		}
		if (!((*l2cr) & 0x80000000)) {
			printk ("Pegasos l2cr : L2 cache was not active, "
				"activating\n");
			_set_L2CR(0);
			_set_L2CR((*l2cr) | 0x80000000);
		}
	}
}

void __init chrp_setup_arch(void)
{
	struct device_node *root = find_path_device ("/");
	char *machine = NULL;
	struct device_node *device;
	unsigned int *p = NULL;

	/* init to some ~sane value until calibrate_delay() runs */
	loops_per_jiffy = 50000000/HZ;

	if (root)
		machine = get_property(root, "model", NULL);
	if (machine && strncmp(machine, "Pegasos", 7) == 0) {
		_chrp_type = _CHRP_Pegasos;
	} else if (machine && strncmp(machine, "IBM", 3) == 0) {
		_chrp_type = _CHRP_IBM;
	} else if (machine && strncmp(machine, "MOT", 3) == 0) {
		_chrp_type = _CHRP_Motorola;
	} else {
		/* Let's assume it is an IBM chrp if all else fails */
		_chrp_type = _CHRP_IBM;
	}
	printk("chrp type = %x\n", _chrp_type);

	rtas_initialize();
	if (rtas_token("display-character") >= 0)
		ppc_md.progress = rtas_progress;

	/* use RTAS time-of-day routines if available */
	if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
		ppc_md.get_boot_time	= rtas_get_boot_time;
		ppc_md.get_rtc_time	= rtas_get_rtc_time;
		ppc_md.set_rtc_time	= rtas_set_rtc_time;
	}

#ifdef CONFIG_BLK_DEV_INITRD
	/* this is fine for chrp */
	initrd_below_start_ok = 1;

	if (initrd_start)
		ROOT_DEV = Root_RAM0;
	else
#endif
		ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */

	/* On pegasos, enable the L2 cache if not already done by OF */
	pegasos_set_l2cr();

	/* Lookup PCI host bridges */
	chrp_find_bridges();

	/*
	 *  Temporary fixes for PCI devices.
	 *  -- Geert
	 */
	hydra_init();		/* Mac I/O */

	/*
	 *  Fix the Super I/O configuration
	 */
	sio_init();

	/* Get the event scan rate for the rtas so we know how
	 * often it expects a heartbeat. -- Cort
	 */
	device = find_devices("rtas");
	if (device)
		p = (unsigned int *) get_property
			(device, "rtas-event-scan-rate", NULL);
	if (p && *p) {
		ppc_md.heartbeat = chrp_event_scan;
		ppc_md.heartbeat_reset = HZ / (*p * 30) - 1;
		ppc_md.heartbeat_count = 1;
		printk("RTAS Event Scan Rate: %u (%lu jiffies)\n",
		       *p, ppc_md.heartbeat_reset);
	}

	pci_create_OF_bus_map();

	/*
	 * Print the banner, then scroll down so boot progress
	 * can be printed.  -- Cort
	 */
	if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
}

void
chrp_event_scan(void)
{
	unsigned char log[1024];
	int ret = 0;

	/* XXX: we should loop until the hardware says no more error logs -- Cort */
	rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0,
		  __pa(log), 1024);
	ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
}

/*
 * Finds the open-pic node and sets up the mpic driver.
 */
static void __init chrp_find_openpic(void)
{
	struct device_node *np, *root;
	int len, i, j, irq_count;
	int isu_size, idu_size;
	unsigned int *iranges, *opprop = NULL;
	int oplen = 0;
	unsigned long opaddr;
	int na = 1;
	unsigned char init_senses[NR_IRQS - NUM_8259_INTERRUPTS];

	np = find_type_devices("open-pic");
	if (np == NULL)
		return;
	root = find_path_device("/");
	if (root) {
		opprop = (unsigned int *) get_property
			(root, "platform-open-pic", &oplen);
		na = prom_n_addr_cells(root);
	}
	if (opprop && oplen >= na * sizeof(unsigned int)) {
		opaddr = opprop[na-1];	/* assume 32-bit */
		oplen /= na * sizeof(unsigned int);
	} else {
		struct resource r;
		if (of_address_to_resource(np, 0, &r))
			return;
		opaddr = r.start;
		oplen = 0;
	}

	printk(KERN_INFO "OpenPIC at %lx\n", opaddr);

	irq_count = NR_IRQS - NUM_ISA_INTERRUPTS - 4; /* leave room for IPIs */
	prom_get_irq_senses(init_senses, NUM_ISA_INTERRUPTS, NR_IRQS - 4);
	/* i8259 cascade is always positive level */
	init_senses[0] = IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE;

	iranges = (unsigned int *) get_property(np, "interrupt-ranges", &len);
	if (iranges == NULL)
		len = 0;	/* non-distributed mpic */
	else
		len /= 2 * sizeof(unsigned int);

	/*
	 * The first pair of cells in interrupt-ranges refers to the
	 * IDU; subsequent pairs refer to the ISUs.
	 */
	if (oplen < len) {
		printk(KERN_ERR "Insufficient addresses for distributed"
		       " OpenPIC (%d < %d)\n", oplen, len);
		len = oplen;
	}

	isu_size = 0;
	idu_size = 0;
	if (len > 0 && iranges[1] != 0) {
		printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
		       iranges[0], iranges[0] + iranges[1] - 1);
		idu_size = iranges[1];
	}
	if (len > 1)
		isu_size = iranges[3];

	chrp_mpic = mpic_alloc(opaddr, MPIC_PRIMARY,
			       isu_size, NUM_ISA_INTERRUPTS, irq_count,
			       NR_IRQS - 4, init_senses, irq_count,
			       " MPIC    ");
	if (chrp_mpic == NULL) {
		printk(KERN_ERR "Failed to allocate MPIC structure\n");
		return;
	}

	j = na - 1;
	for (i = 1; i < len; ++i) {
		iranges += 2;
		j += na;
		printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
		       iranges[0], iranges[0] + iranges[1] - 1,
		       opprop[j]);
		mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
	}

	mpic_init(chrp_mpic);
	mpic_setup_cascade(NUM_ISA_INTERRUPTS, i8259_irq_cascade, NULL);
}

#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
static struct irqaction xmon_irqaction = {
	.handler = xmon_irq,
	.mask = CPU_MASK_NONE,
	.name = "XMON break",
};
#endif

void __init chrp_init_IRQ(void)
{
	struct device_node *np;
	unsigned long chrp_int_ack = 0;
#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
	struct device_node *kbd;
#endif

	for (np = find_devices("pci"); np != NULL; np = np->next) {
		unsigned int *addrp = (unsigned int *)
			get_property(np, "8259-interrupt-acknowledge", NULL);

		if (addrp == NULL)
			continue;
		chrp_int_ack = addrp[prom_n_addr_cells(np)-1];
		break;
	}
	if (np == NULL)
		printk(KERN_ERR "Cannot find PCI interrupt acknowledge address\n");

	chrp_find_openpic();

	i8259_init(chrp_int_ack, 0);

	if (_chrp_type == _CHRP_Pegasos)
		ppc_md.get_irq        = i8259_irq;
	else
		ppc_md.get_irq        = mpic_get_irq;

#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
	/* see if there is a keyboard in the device tree
	   with a parent of type "adb" */
	for (kbd = find_devices("keyboard"); kbd; kbd = kbd->next)
		if (kbd->parent && kbd->parent->type
		    && strcmp(kbd->parent->type, "adb") == 0)
			break;
	if (kbd)
		setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
#endif
}

void __init
chrp_init2(void)
{
#ifdef CONFIG_NVRAM
	chrp_nvram_init();
#endif

	request_region(0x20,0x20,"pic1");
	request_region(0xa0,0x20,"pic2");
	request_region(0x00,0x20,"dma1");
	request_region(0x40,0x20,"timer");
	request_region(0x80,0x10,"dma page reg");
	request_region(0xc0,0x20,"dma2");

	if (ppc_md.progress)
		ppc_md.progress("  Have fun!    ", 0x7777);
}

void __init chrp_init(void)
{
	ISA_DMA_THRESHOLD = ~0L;
	DMA_MODE_READ = 0x44;
	DMA_MODE_WRITE = 0x48;
	isa_io_base = CHRP_ISA_IO_BASE;		/* default value */
	ppc_do_canonicalize_irqs = 1;

	/* Assume we have an 8259... */
	__irq_offset_value = NUM_ISA_INTERRUPTS;

	ppc_md.setup_arch     = chrp_setup_arch;
	ppc_md.show_cpuinfo   = chrp_show_cpuinfo;

	ppc_md.init_IRQ       = chrp_init_IRQ;
	ppc_md.init           = chrp_init2;

	ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;

	ppc_md.restart        = rtas_restart;
	ppc_md.power_off      = rtas_power_off;
	ppc_md.halt           = rtas_halt;

	ppc_md.time_init      = chrp_time_init;
	ppc_md.calibrate_decr = generic_calibrate_decr;

	/* this may get overridden with rtas routines later... */
	ppc_md.set_rtc_time   = chrp_set_rtc_time;
	ppc_md.get_rtc_time   = chrp_get_rtc_time;

#ifdef CONFIG_SMP
	smp_ops = &chrp_smp_ops;
#endif /* CONFIG_SMP */
}
Commit	Line	Data
bbd0abda	1	/*
bbd0abda PM	2	* Copyright (C) 1995 Linus Torvalds
	3	* Adapted from 'alpha' version by Gary Thomas
	4	* Modified by Cort Dougan (cort@cs.nmt.edu)
	5	*/
	6
	7	/*
	8	* bootup setup stuff..
	9	*/
	10
	11	#include <linux/config.h>
	12	#include <linux/errno.h>
	13	#include <linux/sched.h>
	14	#include <linux/kernel.h>
	15	#include <linux/mm.h>
	16	#include <linux/stddef.h>
	17	#include <linux/unistd.h>
	18	#include <linux/ptrace.h>
	19	#include <linux/slab.h>
	20	#include <linux/user.h>
	21	#include <linux/a.out.h>
	22	#include <linux/tty.h>
	23	#include <linux/major.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/reboot.h>
	26	#include <linux/init.h>
	27	#include <linux/pci.h>
	28	#include <linux/version.h>
	29	#include <linux/adb.h>
	30	#include <linux/module.h>
	31	#include <linux/delay.h>
	32	#include <linux/ide.h>
	33	#include <linux/console.h>
	34	#include <linux/seq_file.h>
	35	#include <linux/root_dev.h>
	36	#include <linux/initrd.h>
	37	#include <linux/module.h>
	38
	39	#include <asm/io.h>
	40	#include <asm/pgtable.h>
	41	#include <asm/prom.h>
	42	#include <asm/gg2.h>
	43	#include <asm/pci-bridge.h>
	44	#include <asm/dma.h>
	45	#include <asm/machdep.h>
	46	#include <asm/irq.h>
	47	#include <asm/hydra.h>
	48	#include <asm/sections.h>
	49	#include <asm/time.h>
bbd0abda PM	50	#include <asm/i8259.h>
	51	#include <asm/mpic.h>
	52	#include <asm/rtas.h>
	53	#include <asm/xmon.h>
	54
35e95e63	55	#include "chrp.h"
bbd0abda	56
bbd0abda	57	void rtas_indicator_progress(char *, unsigned short);
bbd0abda PM	58
	59	int _chrp_type;
	60	EXPORT_SYMBOL(_chrp_type);
	61
	62	struct mpic *chrp_mpic;
	63
	64	/*
	65	* XXX this should be in xmon.h, but putting it there means xmon.h
	66	* has to include <linux/interrupt.h> (to get irqreturn_t), which
	67	* causes all sorts of problems. -- paulus
	68	*/
	69	extern irqreturn_t xmon_irq(int, void , struct pt_regs );
	70
	71	extern unsigned long loops_per_jiffy;
	72
	73	#ifdef CONFIG_SMP
	74	extern struct smp_ops_t chrp_smp_ops;
	75	#endif
	76
	77	static const char *gg2_memtypes[4] = {
	78	"FPM", "SDRAM", "EDO", "BEDO"
	79	};
	80	static const char *gg2_cachesizes[4] = {
	81	"256 KB", "512 KB", "1 MB", "Reserved"
	82	};
	83	static const char *gg2_cachetypes[4] = {
	84	"Asynchronous", "Reserved", "Flow-Through Synchronous",
	85	"Pipelined Synchronous"
	86	};
	87	static const char *gg2_cachemodes[4] = {
	88	"Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
	89	};
	90
	91	void chrp_show_cpuinfo(struct seq_file *m)
	92	{
	93	int i, sdramen;
	94	unsigned int t;
	95	struct device_node *root;
	96	const char *model = "";
	97
	98	root = find_path_device("/");
	99	if (root)
	100	model = get_property(root, "model", NULL);
	101	seq_printf(m, "machine\t\t: CHRP %s\n", model);
	102
	103	/* longtrail (goldengate) stuff */
	104	if (!strncmp(model, "IBM,LongTrail", 13)) {
	105	/* VLSI VAS96011/12 `Golden Gate 2' */
	106	/* Memory banks */
	107	sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
	108	>>31) & 1;
	109	for (i = 0; i < (sdramen ? 4 : 6); i++) {
	110	t = in_le32(gg2_pci_config_base+
	111	GG2_PCI_DRAM_BANK0+
	112	i*4);
	113	if (!(t & 1))
	114	continue;
	115	switch ((t>>8) & 0x1f) {
	116	case 0x1f:
	117	model = "4 MB";
	118	break;
	119	case 0x1e:
	120	model = "8 MB";
	121	break;
122	case 0x1c:
123	model = "16 MB";
124	break;
125	case 0x18:
126	model = "32 MB";
127	break;
128	case 0x10:
129	model = "64 MB";
130	break;
131	case 0x00:
132	model = "128 MB";
133	break;
134	default:
135	model = "Reserved";
136	break;
137	}
138	seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
139	gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
140	}
141	/* L2 cache */
142	t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
143	seq_printf(m, "board l2\t: %s %s (%s)\n",
144	gg2_cachesizes[(t>>7) & 3],
145	gg2_cachetypes[(t>>2) & 3],
146	gg2_cachemodes[t & 3]);
147	}
148	}
149
150	/*
151	* Fixes for the National Semiconductor PC78308VUL SuperI/O
152	*
153	* Some versions of Open Firmware incorrectly initialize the IRQ settings
154	* for keyboard and mouse
155	*/
156	static inline void __init sio_write(u8 val, u8 index)
157	{
158	outb(index, 0x15c);
159	outb(val, 0x15d);
160	}
161
162	static inline u8 __init sio_read(u8 index)
163	{
164	outb(index, 0x15c);
165	return inb(0x15d);
166	}
167
168	static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
169	u8 type)
170	{
171	u8 level0, type0, active;
172
173	/* select logical device */
174	sio_write(device, 0x07);
175	active = sio_read(0x30);
176	level0 = sio_read(0x70);
177	type0 = sio_read(0x71);
178	if (level0 != level \|\| type0 != type \|\| !active) {
179	printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
180	"remapping to level %d, type %d, active\n",
181	name, level0, type0, !active ? "in" : "", level, type);
182	sio_write(0x01, 0x30);
183	sio_write(level, 0x70);
184	sio_write(type, 0x71);
185	}
186	}
187
188	static void __init sio_init(void)
189	{
190	struct device_node *root;
191
192	if ((root = find_path_device("/")) &&
193	!strncmp(get_property(root, "model", NULL), "IBM,LongTrail", 13)) {
194	/* logical device 0 (KBC/Keyboard) */
195	sio_fixup_irq("keyboard", 0, 1, 2);
196	/* select logical device 1 (KBC/Mouse) */
197	sio_fixup_irq("mouse", 1, 12, 2);
198	}
199	}
200
201
202	static void __init pegasos_set_l2cr(void)
203	{
204	struct device_node *np;
205
206	/* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
207	if (_chrp_type != _CHRP_Pegasos)
208	return;
209
210	/* Enable L2 cache if needed */
211	np = find_type_devices("cpu");
212	if (np != NULL) {
213	unsigned int l2cr = (unsigned int )
214	get_property (np, "l2cr", NULL);
215	if (l2cr == NULL) {
216	printk ("Pegasos l2cr : no cpu l2cr property found\n");
217	return;
218	}
219	if (!((*l2cr) & 0x80000000)) {
220	printk ("Pegasos l2cr : L2 cache was not active, "
221	"activating\n");
222	_set_L2CR(0);
223	_set_L2CR((*l2cr) \| 0x80000000);
224	}
225	}
226	}
227
228	void __init chrp_setup_arch(void)
229	{
230	struct device_node *root = find_path_device ("/");
231	char *machine = NULL;
232	struct device_node *device;
233	unsigned int *p = NULL;
234
235	/* init to some ~sane value until calibrate_delay() runs */
236	loops_per_jiffy = 50000000/HZ;
237
238	if (root)
239	machine = get_property(root, "model", NULL);
240	if (machine && strncmp(machine, "Pegasos", 7) == 0) {
241	_chrp_type = _CHRP_Pegasos;
242	} else if (machine && strncmp(machine, "IBM", 3) == 0) {
243	_chrp_type = _CHRP_IBM;
244	} else if (machine && strncmp(machine, "MOT", 3) == 0) {
245	_chrp_type = _CHRP_Motorola;
246	} else {
247	/* Let's assume it is an IBM chrp if all else fails */
248	_chrp_type = _CHRP_IBM;
249	}
250	printk("chrp type = %x\n", _chrp_type);
251
252	rtas_initialize();
253	if (rtas_token("display-character") >= 0)
254	ppc_md.progress = rtas_progress;
255
49e16b7b PM	256	/* use RTAS time-of-day routines if available */
	257	if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
	258	ppc_md.get_boot_time = rtas_get_boot_time;
	259	ppc_md.get_rtc_time = rtas_get_rtc_time;
	260	ppc_md.set_rtc_time = rtas_set_rtc_time;
	261	}
	262
bbd0abda PM	263	#ifdef CONFIG_BLK_DEV_INITRD
	264	/* this is fine for chrp */
	265	initrd_below_start_ok = 1;
	266
	267	if (initrd_start)
	268	ROOT_DEV = Root_RAM0;
	269	else
	270	#endif
	271	ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */
	272
	273	/* On pegasos, enable the L2 cache if not already done by OF */
	274	pegasos_set_l2cr();
	275
	276	/* Lookup PCI host bridges */
	277	chrp_find_bridges();
	278
	279	/*
	280	* Temporary fixes for PCI devices.
	281	* -- Geert
	282	*/
	283	hydra_init(); /* Mac I/O */
	284
	285	/*
	286	* Fix the Super I/O configuration
	287	*/
	288	sio_init();
	289
	290	/* Get the event scan rate for the rtas so we know how
	291	* often it expects a heartbeat. -- Cort
	292	*/
	293	device = find_devices("rtas");
	294	if (device)
	295	p = (unsigned int *) get_property
	296	(device, "rtas-event-scan-rate", NULL);
	297	if (p && *p) {
	298	ppc_md.heartbeat = chrp_event_scan;
	299	ppc_md.heartbeat_reset = HZ / (p 30) - 1;
	300	ppc_md.heartbeat_count = 1;
	301	printk("RTAS Event Scan Rate: %u (%lu jiffies)\n",
	302	*p, ppc_md.heartbeat_reset);
	303	}
	304
	305	pci_create_OF_bus_map();
	306
	307	/*
	308	* Print the banner, then scroll down so boot progress
	309	* can be printed. -- Cort
	310	*/
	311	if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
	312	}
	313
	314	void
	315	chrp_event_scan(void)
	316	{
	317	unsigned char log[1024];
	318	int ret = 0;
	319
	320	/* XXX: we should loop until the hardware says no more error logs -- Cort */
	321	rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0,
	322	__pa(log), 1024);
	323	ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
	324	}
	325
	326	/*
327	* Finds the open-pic node and sets up the mpic driver.
328	*/
329	static void __init chrp_find_openpic(void)
330	{
331	struct device_node np, root;
332	int len, i, j, irq_count;
333	int isu_size, idu_size;
334	unsigned int iranges, opprop = NULL;
335	int oplen = 0;
336	unsigned long opaddr;
337	int na = 1;
338	unsigned char init_senses[NR_IRQS - NUM_8259_INTERRUPTS];
339
340	np = find_type_devices("open-pic");
341	if (np == NULL)
342	return;
343	root = find_path_device("/");
344	if (root) {
345	opprop = (unsigned int *) get_property
346	(root, "platform-open-pic", &oplen);
347	na = prom_n_addr_cells(root);
348	}
349	if (opprop && oplen >= na * sizeof(unsigned int)) {
350	opaddr = opprop[na-1]; /* assume 32-bit */
351	oplen /= na * sizeof(unsigned int);
352	} else {
575e3216 DW	353	struct resource r;
575e3216 DW	354	if (of_address_to_resource(np, 0, &r))
bbd0abda	355	return;
575e3216	356	opaddr = r.start;
bbd0abda PM	357	oplen = 0;
	358	}
	359
	360	printk(KERN_INFO "OpenPIC at %lx\n", opaddr);
	361
	362	irq_count = NR_IRQS - NUM_ISA_INTERRUPTS - 4; /* leave room for IPIs */
a23414be PM	363	prom_get_irq_senses(init_senses, NUM_ISA_INTERRUPTS, NR_IRQS - 4);
	364	/* i8259 cascade is always positive level */
	365	init_senses[0] = IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE;
bbd0abda PM	366
	367	iranges = (unsigned int *) get_property(np, "interrupt-ranges", &len);
	368	if (iranges == NULL)
	369	len = 0; /* non-distributed mpic */
	370	else
	371	len /= 2 * sizeof(unsigned int);
	372
	373	/*
	374	* The first pair of cells in interrupt-ranges refers to the
	375	* IDU; subsequent pairs refer to the ISUs.
	376	*/
	377	if (oplen < len) {
	378	printk(KERN_ERR "Insufficient addresses for distributed"
575e3216	379	" OpenPIC (%d < %d)\n", oplen, len);
bbd0abda PM	380	len = oplen;
	381	}
	382
	383	isu_size = 0;
	384	idu_size = 0;
	385	if (len > 0 && iranges[1] != 0) {
	386	printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
	387	iranges[0], iranges[0] + iranges[1] - 1);
	388	idu_size = iranges[1];
	389	}
	390	if (len > 1)
	391	isu_size = iranges[3];
	392
	393	chrp_mpic = mpic_alloc(opaddr, MPIC_PRIMARY,
	394	isu_size, NUM_ISA_INTERRUPTS, irq_count,
	395	NR_IRQS - 4, init_senses, irq_count,
	396	" MPIC ");
	397	if (chrp_mpic == NULL) {
	398	printk(KERN_ERR "Failed to allocate MPIC structure\n");
	399	return;
	400	}
	401
	402	j = na - 1;
	403	for (i = 1; i < len; ++i) {
	404	iranges += 2;
	405	j += na;
	406	printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
	407	iranges[0], iranges[0] + iranges[1] - 1,
	408	opprop[j]);
	409	mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
	410	}
	411
	412	mpic_init(chrp_mpic);
	413	mpic_setup_cascade(NUM_ISA_INTERRUPTS, i8259_irq_cascade, NULL);
	414	}
	415
	416	#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
	417	static struct irqaction xmon_irqaction = {
	418	.handler = xmon_irq,
	419	.mask = CPU_MASK_NONE,
	420	.name = "XMON break",
	421	};
	422	#endif
	423
	424	void __init chrp_init_IRQ(void)
	425	{
	426	struct device_node *np;
	427	unsigned long chrp_int_ack = 0;
	428	#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
	429	struct device_node *kbd;
	430	#endif
	431
	432	for (np = find_devices("pci"); np != NULL; np = np->next) {
	433	unsigned int addrp = (unsigned int )
	434	get_property(np, "8259-interrupt-acknowledge", NULL);
	435
	436	if (addrp == NULL)
	437	continue;
	438	chrp_int_ack = addrp[prom_n_addr_cells(np)-1];
	439	break;
	440	}
	441	if (np == NULL)
	442	printk(KERN_ERR "Cannot find PCI interrupt acknowledge address\n");
	443
444	chrp_find_openpic();
445
446	i8259_init(chrp_int_ack, 0);
447
448	if (_chrp_type == _CHRP_Pegasos)
449	ppc_md.get_irq = i8259_irq;
450	else
451	ppc_md.get_irq = mpic_get_irq;
452
453	#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
454	/* see if there is a keyboard in the device tree
455	with a parent of type "adb" */
456	for (kbd = find_devices("keyboard"); kbd; kbd = kbd->next)
457	if (kbd->parent && kbd->parent->type
458	&& strcmp(kbd->parent->type, "adb") == 0)
459	break;
460	if (kbd)
461	setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
462	#endif
463	}
464
465	void __init
466	chrp_init2(void)
467	{
35e95e63 OH	468	#ifdef CONFIG_NVRAM
	469	chrp_nvram_init();
	470	#endif
	471
bbd0abda PM	472	request_region(0x20,0x20,"pic1");
	473	request_region(0xa0,0x20,"pic2");
	474	request_region(0x00,0x20,"dma1");
	475	request_region(0x40,0x20,"timer");
	476	request_region(0x80,0x10,"dma page reg");
	477	request_region(0xc0,0x20,"dma2");
	478
	479	if (ppc_md.progress)
	480	ppc_md.progress(" Have fun! ", 0x7777);
	481	}
	482
	483	void __init chrp_init(void)
	484	{
	485	ISA_DMA_THRESHOLD = ~0L;
	486	DMA_MODE_READ = 0x44;
	487	DMA_MODE_WRITE = 0x48;
	488	isa_io_base = CHRP_ISA_IO_BASE; /* default value */
	489	ppc_do_canonicalize_irqs = 1;
	490
	491	/* Assume we have an 8259... */
	492	__irq_offset_value = NUM_ISA_INTERRUPTS;
	493
	494	ppc_md.setup_arch = chrp_setup_arch;
	495	ppc_md.show_cpuinfo = chrp_show_cpuinfo;
	496
	497	ppc_md.init_IRQ = chrp_init_IRQ;
	498	ppc_md.init = chrp_init2;
	499
	500	ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
	501
	502	ppc_md.restart = rtas_restart;
	503	ppc_md.power_off = rtas_power_off;
	504	ppc_md.halt = rtas_halt;
	505
	506	ppc_md.time_init = chrp_time_init;
03478804	507	ppc_md.calibrate_decr = generic_calibrate_decr;
49e16b7b PM	508
49e16b7b PM	509	/* this may get overridden with rtas routines later... */
bbd0abda PM	510	ppc_md.set_rtc_time = chrp_set_rtc_time;
bbd0abda PM	511	ppc_md.get_rtc_time = chrp_get_rtc_time;
bbd0abda PM	512
	513	#ifdef CONFIG_SMP
	514	smp_ops = &chrp_smp_ops;
	515	#endif /* CONFIG_SMP */
	516	}