[net-next-2.6.git] / arch / powerpc / platforms / chrp / setup.c

/*
 *  arch/ppc/platforms/setup.c
 *
 *  Copyright (C) 1995  Linus Torvalds
 *  Adapted from 'alpha' version by Gary Thomas
 *  Modified by Cort Dougan (cort@cs.nmt.edu)
 */

/*
 * bootup setup stuff..
 */

#include <linux/config.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/stddef.h>
#include <linux/unistd.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/user.h>
#include <linux/a.out.h>
#include <linux/tty.h>
#include <linux/major.h>
#include <linux/interrupt.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/version.h>
#include <linux/adb.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/ide.h>
#include <linux/console.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <linux/initrd.h>
#include <linux/module.h>

#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/prom.h>
#include <asm/gg2.h>
#include <asm/pci-bridge.h>
#include <asm/dma.h>
#include <asm/machdep.h>
#include <asm/irq.h>
#include <asm/hydra.h>
#include <asm/sections.h>
#include <asm/time.h>
#include <asm/i8259.h>
#include <asm/mpic.h>
#include <asm/rtas.h>
#include <asm/xmon.h>

#include "chrp.h"

void rtas_indicator_progress(char *, unsigned short);

int _chrp_type;
EXPORT_SYMBOL(_chrp_type);

struct mpic *chrp_mpic;

/*
 * XXX this should be in xmon.h, but putting it there means xmon.h
 * has to include <linux/interrupt.h> (to get irqreturn_t), which
 * causes all sorts of problems.  -- paulus
 */
extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);

extern unsigned long loops_per_jiffy;

#ifdef CONFIG_SMP
extern struct smp_ops_t chrp_smp_ops;
#endif

static const char *gg2_memtypes[4] = {
	"FPM", "SDRAM", "EDO", "BEDO"
};
static const char *gg2_cachesizes[4] = {
	"256 KB", "512 KB", "1 MB", "Reserved"
};
static const char *gg2_cachetypes[4] = {
	"Asynchronous", "Reserved", "Flow-Through Synchronous",
	"Pipelined Synchronous"
};
static const char *gg2_cachemodes[4] = {
	"Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
};

void chrp_show_cpuinfo(struct seq_file *m)
{
	int i, sdramen;
	unsigned int t;
	struct device_node *root;
	const char *model = "";

	root = find_path_device("/");
	if (root)
		model = get_property(root, "model", NULL);
	seq_printf(m, "machine\t\t: CHRP %s\n", model);

	/* longtrail (goldengate) stuff */
	if (!strncmp(model, "IBM,LongTrail", 13)) {
		/* VLSI VAS96011/12 `Golden Gate 2' */
		/* Memory banks */
		sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
			   >>31) & 1;
		for (i = 0; i < (sdramen ? 4 : 6); i++) {
			t = in_le32(gg2_pci_config_base+
						 GG2_PCI_DRAM_BANK0+
						 i*4);
			if (!(t & 1))
				continue;
			switch ((t>>8) & 0x1f) {
			case 0x1f:
				model = "4 MB";
				break;
			case 0x1e:
				model = "8 MB";
				break;
			case 0x1c:
				model = "16 MB";
				break;
			case 0x18:
				model = "32 MB";
				break;
			case 0x10:
				model = "64 MB";
				break;
			case 0x00:
				model = "128 MB";
				break;
			default:
				model = "Reserved";
				break;
			}
			seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
				   gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
		}
		/* L2 cache */
		t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
		seq_printf(m, "board l2\t: %s %s (%s)\n",
			   gg2_cachesizes[(t>>7) & 3],
			   gg2_cachetypes[(t>>2) & 3],
			   gg2_cachemodes[t & 3]);
	}
}

/*
 *  Fixes for the National Semiconductor PC78308VUL SuperI/O
 *
 *  Some versions of Open Firmware incorrectly initialize the IRQ settings
 *  for keyboard and mouse
 */
static inline void __init sio_write(u8 val, u8 index)
{
	outb(index, 0x15c);
	outb(val, 0x15d);
}

static inline u8 __init sio_read(u8 index)
{
	outb(index, 0x15c);
	return inb(0x15d);
}

static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
				     u8 type)
{
	u8 level0, type0, active;

	/* select logical device */
	sio_write(device, 0x07);
	active = sio_read(0x30);
	level0 = sio_read(0x70);
	type0 = sio_read(0x71);
	if (level0 != level || type0 != type || !active) {
		printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
		       "remapping to level %d, type %d, active\n",
		       name, level0, type0, !active ? "in" : "", level, type);
		sio_write(0x01, 0x30);
		sio_write(level, 0x70);
		sio_write(type, 0x71);
	}
}

static void __init sio_init(void)
{
	struct device_node *root;

	if ((root = find_path_device("/")) &&
	    !strncmp(get_property(root, "model", NULL), "IBM,LongTrail", 13)) {
		/* logical device 0 (KBC/Keyboard) */
		sio_fixup_irq("keyboard", 0, 1, 2);
		/* select logical device 1 (KBC/Mouse) */
		sio_fixup_irq("mouse", 1, 12, 2);
	}
}


static void __init pegasos_set_l2cr(void)
{
	struct device_node *np;

	/* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
	if (_chrp_type != _CHRP_Pegasos)
		return;

	/* Enable L2 cache if needed */
	np = find_type_devices("cpu");
	if (np != NULL) {
		unsigned int *l2cr = (unsigned int *)
			get_property (np, "l2cr", NULL);
		if (l2cr == NULL) {
			printk ("Pegasos l2cr : no cpu l2cr property found\n");
			return;
		}
		if (!((*l2cr) & 0x80000000)) {
			printk ("Pegasos l2cr : L2 cache was not active, "
				"activating\n");
			_set_L2CR(0);
			_set_L2CR((*l2cr) | 0x80000000);
		}
	}
}

void __init chrp_setup_arch(void)
{
	struct device_node *root = find_path_device ("/");
	char *machine = NULL;
	struct device_node *device;
	unsigned int *p = NULL;

	/* init to some ~sane value until calibrate_delay() runs */
	loops_per_jiffy = 50000000/HZ;

	if (root)
		machine = get_property(root, "model", NULL);
	if (machine && strncmp(machine, "Pegasos", 7) == 0) {
		_chrp_type = _CHRP_Pegasos;
	} else if (machine && strncmp(machine, "IBM", 3) == 0) {
		_chrp_type = _CHRP_IBM;
	} else if (machine && strncmp(machine, "MOT", 3) == 0) {
		_chrp_type = _CHRP_Motorola;
	} else {
		/* Let's assume it is an IBM chrp if all else fails */
		_chrp_type = _CHRP_IBM;
	}
	printk("chrp type = %x\n", _chrp_type);

	rtas_initialize();
	if (rtas_token("display-character") >= 0)
		ppc_md.progress = rtas_progress;

	/* use RTAS time-of-day routines if available */
	if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
		ppc_md.get_boot_time	= rtas_get_boot_time;
		ppc_md.get_rtc_time	= rtas_get_rtc_time;
		ppc_md.set_rtc_time	= rtas_set_rtc_time;
	}

#ifdef CONFIG_BLK_DEV_INITRD
	/* this is fine for chrp */
	initrd_below_start_ok = 1;

	if (initrd_start)
		ROOT_DEV = Root_RAM0;
	else
#endif
		ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */

	/* On pegasos, enable the L2 cache if not already done by OF */
	pegasos_set_l2cr();

	/* Lookup PCI host bridges */
	chrp_find_bridges();

	/*
	 *  Temporary fixes for PCI devices.
	 *  -- Geert
	 */
	hydra_init();		/* Mac I/O */

	/*
	 *  Fix the Super I/O configuration
	 */
	sio_init();

	/* Get the event scan rate for the rtas so we know how
	 * often it expects a heartbeat. -- Cort
	 */
	device = find_devices("rtas");
	if (device)
		p = (unsigned int *) get_property
			(device, "rtas-event-scan-rate", NULL);
	if (p && *p) {
		ppc_md.heartbeat = chrp_event_scan;
		ppc_md.heartbeat_reset = HZ / (*p * 30) - 1;
		ppc_md.heartbeat_count = 1;
		printk("RTAS Event Scan Rate: %u (%lu jiffies)\n",
		       *p, ppc_md.heartbeat_reset);
	}

	pci_create_OF_bus_map();

	/*
	 * Print the banner, then scroll down so boot progress
	 * can be printed.  -- Cort
	 */
	if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
}

void
chrp_event_scan(void)
{
	unsigned char log[1024];
	int ret = 0;

	/* XXX: we should loop until the hardware says no more error logs -- Cort */
	rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0,
		  __pa(log), 1024);
	ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
}

/*
 * Finds the open-pic node and sets up the mpic driver.
 */
static void __init chrp_find_openpic(void)
{
	struct device_node *np, *root;
	int len, i, j, irq_count;
	int isu_size, idu_size;
	unsigned int *iranges, *opprop = NULL;
	int oplen = 0;
	unsigned long opaddr;
	int na = 1;
	unsigned char init_senses[NR_IRQS - NUM_8259_INTERRUPTS];

	np = find_type_devices("open-pic");
	if (np == NULL)
		return;
	root = find_path_device("/");
	if (root) {
		opprop = (unsigned int *) get_property
			(root, "platform-open-pic", &oplen);
		na = prom_n_addr_cells(root);
	}
	if (opprop && oplen >= na * sizeof(unsigned int)) {
		opaddr = opprop[na-1];	/* assume 32-bit */
		oplen /= na * sizeof(unsigned int);
	} else {
		if (np->n_addrs == 0)
			return;
		opaddr = np->addrs[0].address;
		oplen = 0;
	}

	printk(KERN_INFO "OpenPIC at %lx\n", opaddr);

	irq_count = NR_IRQS - NUM_ISA_INTERRUPTS - 4; /* leave room for IPIs */
	prom_get_irq_senses(init_senses, NUM_ISA_INTERRUPTS, NR_IRQS - 4);
	/* i8259 cascade is always positive level */
	init_senses[0] = IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE;

	iranges = (unsigned int *) get_property(np, "interrupt-ranges", &len);
	if (iranges == NULL)
		len = 0;	/* non-distributed mpic */
	else
		len /= 2 * sizeof(unsigned int);

	/*
	 * The first pair of cells in interrupt-ranges refers to the
	 * IDU; subsequent pairs refer to the ISUs.
	 */
	if (oplen < len) {
		printk(KERN_ERR "Insufficient addresses for distributed"
		       " OpenPIC (%d < %d)\n", np->n_addrs, len);
		len = oplen;
	}

	isu_size = 0;
	idu_size = 0;
	if (len > 0 && iranges[1] != 0) {
		printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
		       iranges[0], iranges[0] + iranges[1] - 1);
		idu_size = iranges[1];
	}
	if (len > 1)
		isu_size = iranges[3];

	chrp_mpic = mpic_alloc(opaddr, MPIC_PRIMARY,
			       isu_size, NUM_ISA_INTERRUPTS, irq_count,
			       NR_IRQS - 4, init_senses, irq_count,
			       " MPIC    ");
	if (chrp_mpic == NULL) {
		printk(KERN_ERR "Failed to allocate MPIC structure\n");
		return;
	}

	j = na - 1;
	for (i = 1; i < len; ++i) {
		iranges += 2;
		j += na;
		printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
		       iranges[0], iranges[0] + iranges[1] - 1,
		       opprop[j]);
		mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
	}

	mpic_init(chrp_mpic);
	mpic_setup_cascade(NUM_ISA_INTERRUPTS, i8259_irq_cascade, NULL);
}

#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
static struct irqaction xmon_irqaction = {
	.handler = xmon_irq,
	.mask = CPU_MASK_NONE,
	.name = "XMON break",
};
#endif

void __init chrp_init_IRQ(void)
{
	struct device_node *np;
	unsigned long chrp_int_ack = 0;
#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
	struct device_node *kbd;
#endif

	for (np = find_devices("pci"); np != NULL; np = np->next) {
		unsigned int *addrp = (unsigned int *)
			get_property(np, "8259-interrupt-acknowledge", NULL);

		if (addrp == NULL)
			continue;
		chrp_int_ack = addrp[prom_n_addr_cells(np)-1];
		break;
	}
	if (np == NULL)
		printk(KERN_ERR "Cannot find PCI interrupt acknowledge address\n");

	chrp_find_openpic();

	i8259_init(chrp_int_ack, 0);

	if (_chrp_type == _CHRP_Pegasos)
		ppc_md.get_irq        = i8259_irq;
	else
		ppc_md.get_irq        = mpic_get_irq;

#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
	/* see if there is a keyboard in the device tree
	   with a parent of type "adb" */
	for (kbd = find_devices("keyboard"); kbd; kbd = kbd->next)
		if (kbd->parent && kbd->parent->type
		    && strcmp(kbd->parent->type, "adb") == 0)
			break;
	if (kbd)
		setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
#endif
}

void __init
chrp_init2(void)
{
#ifdef CONFIG_NVRAM
	chrp_nvram_init();
#endif

	request_region(0x20,0x20,"pic1");
	request_region(0xa0,0x20,"pic2");
	request_region(0x00,0x20,"dma1");
	request_region(0x40,0x20,"timer");
	request_region(0x80,0x10,"dma page reg");
	request_region(0xc0,0x20,"dma2");

	if (ppc_md.progress)
		ppc_md.progress("  Have fun!    ", 0x7777);
}

void __init chrp_init(void)
{
	ISA_DMA_THRESHOLD = ~0L;
	DMA_MODE_READ = 0x44;
	DMA_MODE_WRITE = 0x48;
	isa_io_base = CHRP_ISA_IO_BASE;		/* default value */
	ppc_do_canonicalize_irqs = 1;

	/* Assume we have an 8259... */
	__irq_offset_value = NUM_ISA_INTERRUPTS;

	ppc_md.setup_arch     = chrp_setup_arch;
	ppc_md.show_cpuinfo   = chrp_show_cpuinfo;

	ppc_md.init_IRQ       = chrp_init_IRQ;
	ppc_md.init           = chrp_init2;

	ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;

	ppc_md.restart        = rtas_restart;
	ppc_md.power_off      = rtas_power_off;
	ppc_md.halt           = rtas_halt;

	ppc_md.time_init      = chrp_time_init;
	ppc_md.calibrate_decr = chrp_calibrate_decr;

	/* this may get overridden with rtas routines later... */
	ppc_md.set_rtc_time   = chrp_set_rtc_time;
	ppc_md.get_rtc_time   = chrp_get_rtc_time;

#ifdef CONFIG_SMP
	smp_ops = &chrp_smp_ops;
#endif /* CONFIG_SMP */
}
Commit	Line	Data
bbd0abda PM	1	/*
	2	* arch/ppc/platforms/setup.c
	3	*
	4	* Copyright (C) 1995 Linus Torvalds
	5	* Adapted from 'alpha' version by Gary Thomas
	6	* Modified by Cort Dougan (cort@cs.nmt.edu)
	7	*/
	8
	9	/*
	10	* bootup setup stuff..
	11	*/
	12
	13	#include <linux/config.h>
	14	#include <linux/errno.h>
	15	#include <linux/sched.h>
	16	#include <linux/kernel.h>
	17	#include <linux/mm.h>
	18	#include <linux/stddef.h>
	19	#include <linux/unistd.h>
	20	#include <linux/ptrace.h>
	21	#include <linux/slab.h>
	22	#include <linux/user.h>
	23	#include <linux/a.out.h>
	24	#include <linux/tty.h>
	25	#include <linux/major.h>
	26	#include <linux/interrupt.h>
	27	#include <linux/reboot.h>
	28	#include <linux/init.h>
	29	#include <linux/pci.h>
	30	#include <linux/version.h>
	31	#include <linux/adb.h>
	32	#include <linux/module.h>
	33	#include <linux/delay.h>
	34	#include <linux/ide.h>
	35	#include <linux/console.h>
	36	#include <linux/seq_file.h>
	37	#include <linux/root_dev.h>
	38	#include <linux/initrd.h>
	39	#include <linux/module.h>
	40
	41	#include <asm/io.h>
	42	#include <asm/pgtable.h>
	43	#include <asm/prom.h>
	44	#include <asm/gg2.h>
	45	#include <asm/pci-bridge.h>
	46	#include <asm/dma.h>
	47	#include <asm/machdep.h>
	48	#include <asm/irq.h>
	49	#include <asm/hydra.h>
	50	#include <asm/sections.h>
	51	#include <asm/time.h>
bbd0abda PM	52	#include <asm/i8259.h>
	53	#include <asm/mpic.h>
	54	#include <asm/rtas.h>
	55	#include <asm/xmon.h>
	56
35e95e63	57	#include "chrp.h"
bbd0abda	58
bbd0abda	59	void rtas_indicator_progress(char *, unsigned short);
bbd0abda PM	60
	61	int _chrp_type;
	62	EXPORT_SYMBOL(_chrp_type);
	63
	64	struct mpic *chrp_mpic;
	65
	66	/*
	67	* XXX this should be in xmon.h, but putting it there means xmon.h
	68	* has to include <linux/interrupt.h> (to get irqreturn_t), which
	69	* causes all sorts of problems. -- paulus
	70	*/
	71	extern irqreturn_t xmon_irq(int, void , struct pt_regs );
	72
	73	extern unsigned long loops_per_jiffy;
	74
	75	#ifdef CONFIG_SMP
	76	extern struct smp_ops_t chrp_smp_ops;
	77	#endif
	78
	79	static const char *gg2_memtypes[4] = {
	80	"FPM", "SDRAM", "EDO", "BEDO"
	81	};
	82	static const char *gg2_cachesizes[4] = {
	83	"256 KB", "512 KB", "1 MB", "Reserved"
	84	};
	85	static const char *gg2_cachetypes[4] = {
	86	"Asynchronous", "Reserved", "Flow-Through Synchronous",
	87	"Pipelined Synchronous"
	88	};
	89	static const char *gg2_cachemodes[4] = {
	90	"Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
	91	};
	92
	93	void chrp_show_cpuinfo(struct seq_file *m)
	94	{
	95	int i, sdramen;
	96	unsigned int t;
	97	struct device_node *root;
	98	const char *model = "";
	99
	100	root = find_path_device("/");
	101	if (root)
	102	model = get_property(root, "model", NULL);
	103	seq_printf(m, "machine\t\t: CHRP %s\n", model);
	104
	105	/* longtrail (goldengate) stuff */
	106	if (!strncmp(model, "IBM,LongTrail", 13)) {
	107	/* VLSI VAS96011/12 `Golden Gate 2' */
	108	/* Memory banks */
	109	sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
	110	>>31) & 1;
	111	for (i = 0; i < (sdramen ? 4 : 6); i++) {
	112	t = in_le32(gg2_pci_config_base+
	113	GG2_PCI_DRAM_BANK0+
	114	i*4);
	115	if (!(t & 1))
	116	continue;
	117	switch ((t>>8) & 0x1f) {
	118	case 0x1f:
	119	model = "4 MB";
	120	break;
	121	case 0x1e:
	122	model = "8 MB";
	123	break;
124	case 0x1c:
125	model = "16 MB";
126	break;
127	case 0x18:
128	model = "32 MB";
129	break;
130	case 0x10:
131	model = "64 MB";
132	break;
133	case 0x00:
134	model = "128 MB";
135	break;
136	default:
137	model = "Reserved";
138	break;
139	}
140	seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
141	gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
142	}
143	/* L2 cache */
144	t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
145	seq_printf(m, "board l2\t: %s %s (%s)\n",
146	gg2_cachesizes[(t>>7) & 3],
147	gg2_cachetypes[(t>>2) & 3],
148	gg2_cachemodes[t & 3]);
149	}
150	}
151
152	/*
153	* Fixes for the National Semiconductor PC78308VUL SuperI/O
154	*
155	* Some versions of Open Firmware incorrectly initialize the IRQ settings
156	* for keyboard and mouse
157	*/
158	static inline void __init sio_write(u8 val, u8 index)
159	{
160	outb(index, 0x15c);
161	outb(val, 0x15d);
162	}
163
164	static inline u8 __init sio_read(u8 index)
165	{
166	outb(index, 0x15c);
167	return inb(0x15d);
168	}
169
170	static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
171	u8 type)
172	{
173	u8 level0, type0, active;
174
175	/* select logical device */
176	sio_write(device, 0x07);
177	active = sio_read(0x30);
178	level0 = sio_read(0x70);
179	type0 = sio_read(0x71);
180	if (level0 != level \|\| type0 != type \|\| !active) {
181	printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
182	"remapping to level %d, type %d, active\n",
183	name, level0, type0, !active ? "in" : "", level, type);
184	sio_write(0x01, 0x30);
185	sio_write(level, 0x70);
186	sio_write(type, 0x71);
187	}
188	}
189
190	static void __init sio_init(void)
191	{
192	struct device_node *root;
193
194	if ((root = find_path_device("/")) &&
195	!strncmp(get_property(root, "model", NULL), "IBM,LongTrail", 13)) {
196	/* logical device 0 (KBC/Keyboard) */
197	sio_fixup_irq("keyboard", 0, 1, 2);
198	/* select logical device 1 (KBC/Mouse) */
199	sio_fixup_irq("mouse", 1, 12, 2);
200	}
201	}
202
203
204	static void __init pegasos_set_l2cr(void)
205	{
206	struct device_node *np;
207
208	/* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
209	if (_chrp_type != _CHRP_Pegasos)
210	return;
211
212	/* Enable L2 cache if needed */
213	np = find_type_devices("cpu");
214	if (np != NULL) {
215	unsigned int l2cr = (unsigned int )
216	get_property (np, "l2cr", NULL);
217	if (l2cr == NULL) {
218	printk ("Pegasos l2cr : no cpu l2cr property found\n");
219	return;
220	}
221	if (!((*l2cr) & 0x80000000)) {
222	printk ("Pegasos l2cr : L2 cache was not active, "
223	"activating\n");
224	_set_L2CR(0);
225	_set_L2CR((*l2cr) \| 0x80000000);
226	}
227	}
228	}
229
230	void __init chrp_setup_arch(void)
231	{
232	struct device_node *root = find_path_device ("/");
233	char *machine = NULL;
234	struct device_node *device;
235	unsigned int *p = NULL;
236
237	/* init to some ~sane value until calibrate_delay() runs */
238	loops_per_jiffy = 50000000/HZ;
239
240	if (root)
241	machine = get_property(root, "model", NULL);
242	if (machine && strncmp(machine, "Pegasos", 7) == 0) {
243	_chrp_type = _CHRP_Pegasos;
244	} else if (machine && strncmp(machine, "IBM", 3) == 0) {
245	_chrp_type = _CHRP_IBM;
246	} else if (machine && strncmp(machine, "MOT", 3) == 0) {
247	_chrp_type = _CHRP_Motorola;
248	} else {
249	/* Let's assume it is an IBM chrp if all else fails */
250	_chrp_type = _CHRP_IBM;
251	}
252	printk("chrp type = %x\n", _chrp_type);
253
254	rtas_initialize();
255	if (rtas_token("display-character") >= 0)
256	ppc_md.progress = rtas_progress;
257
49e16b7b PM	258	/* use RTAS time-of-day routines if available */
	259	if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
	260	ppc_md.get_boot_time = rtas_get_boot_time;
	261	ppc_md.get_rtc_time = rtas_get_rtc_time;
	262	ppc_md.set_rtc_time = rtas_set_rtc_time;
	263	}
	264
bbd0abda PM	265	#ifdef CONFIG_BLK_DEV_INITRD
	266	/* this is fine for chrp */
	267	initrd_below_start_ok = 1;
	268
	269	if (initrd_start)
	270	ROOT_DEV = Root_RAM0;
	271	else
	272	#endif
	273	ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */
	274
	275	/* On pegasos, enable the L2 cache if not already done by OF */
	276	pegasos_set_l2cr();
	277
	278	/* Lookup PCI host bridges */
	279	chrp_find_bridges();
	280
	281	/*
	282	* Temporary fixes for PCI devices.
	283	* -- Geert
	284	*/
	285	hydra_init(); /* Mac I/O */
	286
	287	/*
	288	* Fix the Super I/O configuration
	289	*/
	290	sio_init();
	291
	292	/* Get the event scan rate for the rtas so we know how
	293	* often it expects a heartbeat. -- Cort
	294	*/
	295	device = find_devices("rtas");
	296	if (device)
	297	p = (unsigned int *) get_property
	298	(device, "rtas-event-scan-rate", NULL);
	299	if (p && *p) {
	300	ppc_md.heartbeat = chrp_event_scan;
	301	ppc_md.heartbeat_reset = HZ / (p 30) - 1;
	302	ppc_md.heartbeat_count = 1;
	303	printk("RTAS Event Scan Rate: %u (%lu jiffies)\n",
	304	*p, ppc_md.heartbeat_reset);
	305	}
	306
	307	pci_create_OF_bus_map();
	308
	309	/*
	310	* Print the banner, then scroll down so boot progress
	311	* can be printed. -- Cort
	312	*/
	313	if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
	314	}
	315
	316	void
	317	chrp_event_scan(void)
	318	{
	319	unsigned char log[1024];
	320	int ret = 0;
	321
	322	/* XXX: we should loop until the hardware says no more error logs -- Cort */
	323	rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0,
	324	__pa(log), 1024);
	325	ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
	326	}
	327
	328	/*
329	* Finds the open-pic node and sets up the mpic driver.
330	*/
331	static void __init chrp_find_openpic(void)
332	{
333	struct device_node np, root;
334	int len, i, j, irq_count;
335	int isu_size, idu_size;
336	unsigned int iranges, opprop = NULL;
337	int oplen = 0;
338	unsigned long opaddr;
339	int na = 1;
340	unsigned char init_senses[NR_IRQS - NUM_8259_INTERRUPTS];
341
342	np = find_type_devices("open-pic");
343	if (np == NULL)
344	return;
345	root = find_path_device("/");
346	if (root) {
347	opprop = (unsigned int *) get_property
348	(root, "platform-open-pic", &oplen);
349	na = prom_n_addr_cells(root);
350	}
351	if (opprop && oplen >= na * sizeof(unsigned int)) {
352	opaddr = opprop[na-1]; /* assume 32-bit */
353	oplen /= na * sizeof(unsigned int);
354	} else {
355	if (np->n_addrs == 0)
356	return;
357	opaddr = np->addrs[0].address;
358	oplen = 0;
359	}
360
361	printk(KERN_INFO "OpenPIC at %lx\n", opaddr);
362
363	irq_count = NR_IRQS - NUM_ISA_INTERRUPTS - 4; /* leave room for IPIs */
a23414be PM	364	prom_get_irq_senses(init_senses, NUM_ISA_INTERRUPTS, NR_IRQS - 4);
	365	/* i8259 cascade is always positive level */
	366	init_senses[0] = IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE;
bbd0abda PM	367
	368	iranges = (unsigned int *) get_property(np, "interrupt-ranges", &len);
	369	if (iranges == NULL)
	370	len = 0; /* non-distributed mpic */
	371	else
	372	len /= 2 * sizeof(unsigned int);
	373
	374	/*
	375	* The first pair of cells in interrupt-ranges refers to the
	376	* IDU; subsequent pairs refer to the ISUs.
	377	*/
	378	if (oplen < len) {
	379	printk(KERN_ERR "Insufficient addresses for distributed"
	380	" OpenPIC (%d < %d)\n", np->n_addrs, len);
	381	len = oplen;
	382	}
	383
	384	isu_size = 0;
	385	idu_size = 0;
	386	if (len > 0 && iranges[1] != 0) {
	387	printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
	388	iranges[0], iranges[0] + iranges[1] - 1);
	389	idu_size = iranges[1];
	390	}
	391	if (len > 1)
	392	isu_size = iranges[3];
	393
	394	chrp_mpic = mpic_alloc(opaddr, MPIC_PRIMARY,
	395	isu_size, NUM_ISA_INTERRUPTS, irq_count,
	396	NR_IRQS - 4, init_senses, irq_count,
	397	" MPIC ");
	398	if (chrp_mpic == NULL) {
	399	printk(KERN_ERR "Failed to allocate MPIC structure\n");
	400	return;
	401	}
	402
	403	j = na - 1;
	404	for (i = 1; i < len; ++i) {
	405	iranges += 2;
	406	j += na;
	407	printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
	408	iranges[0], iranges[0] + iranges[1] - 1,
	409	opprop[j]);
	410	mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
	411	}
	412
	413	mpic_init(chrp_mpic);
	414	mpic_setup_cascade(NUM_ISA_INTERRUPTS, i8259_irq_cascade, NULL);
	415	}
	416
	417	#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
	418	static struct irqaction xmon_irqaction = {
	419	.handler = xmon_irq,
	420	.mask = CPU_MASK_NONE,
	421	.name = "XMON break",
	422	};
	423	#endif
	424
	425	void __init chrp_init_IRQ(void)
	426	{
	427	struct device_node *np;
	428	unsigned long chrp_int_ack = 0;
	429	#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
	430	struct device_node *kbd;
431	#endif
432
433	for (np = find_devices("pci"); np != NULL; np = np->next) {
434	unsigned int addrp = (unsigned int )
435	get_property(np, "8259-interrupt-acknowledge", NULL);
436
437	if (addrp == NULL)
438	continue;
439	chrp_int_ack = addrp[prom_n_addr_cells(np)-1];
440	break;
441	}
442	if (np == NULL)
443	printk(KERN_ERR "Cannot find PCI interrupt acknowledge address\n");
444
445	chrp_find_openpic();
446
447	i8259_init(chrp_int_ack, 0);
448
449	if (_chrp_type == _CHRP_Pegasos)
450	ppc_md.get_irq = i8259_irq;
451	else
452	ppc_md.get_irq = mpic_get_irq;
453
454	#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
455	/* see if there is a keyboard in the device tree
456	with a parent of type "adb" */
457	for (kbd = find_devices("keyboard"); kbd; kbd = kbd->next)
458	if (kbd->parent && kbd->parent->type
459	&& strcmp(kbd->parent->type, "adb") == 0)
460	break;
461	if (kbd)
462	setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
463	#endif
464	}
465
466	void __init
467	chrp_init2(void)
468	{
35e95e63 OH	469	#ifdef CONFIG_NVRAM
	470	chrp_nvram_init();
	471	#endif
	472
bbd0abda PM	473	request_region(0x20,0x20,"pic1");
	474	request_region(0xa0,0x20,"pic2");
	475	request_region(0x00,0x20,"dma1");
	476	request_region(0x40,0x20,"timer");
	477	request_region(0x80,0x10,"dma page reg");
	478	request_region(0xc0,0x20,"dma2");
	479
	480	if (ppc_md.progress)
	481	ppc_md.progress(" Have fun! ", 0x7777);
	482	}
	483
	484	void __init chrp_init(void)
	485	{
	486	ISA_DMA_THRESHOLD = ~0L;
	487	DMA_MODE_READ = 0x44;
	488	DMA_MODE_WRITE = 0x48;
	489	isa_io_base = CHRP_ISA_IO_BASE; /* default value */
	490	ppc_do_canonicalize_irqs = 1;
	491
	492	/* Assume we have an 8259... */
	493	__irq_offset_value = NUM_ISA_INTERRUPTS;
	494
	495	ppc_md.setup_arch = chrp_setup_arch;
	496	ppc_md.show_cpuinfo = chrp_show_cpuinfo;
	497
	498	ppc_md.init_IRQ = chrp_init_IRQ;
	499	ppc_md.init = chrp_init2;
	500
	501	ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
	502
	503	ppc_md.restart = rtas_restart;
	504	ppc_md.power_off = rtas_power_off;
	505	ppc_md.halt = rtas_halt;
	506
	507	ppc_md.time_init = chrp_time_init;
49e16b7b PM	508	ppc_md.calibrate_decr = chrp_calibrate_decr;
	509
	510	/* this may get overridden with rtas routines later... */
bbd0abda PM	511	ppc_md.set_rtc_time = chrp_set_rtc_time;
bbd0abda PM	512	ppc_md.get_rtc_time = chrp_get_rtc_time;
bbd0abda PM	513
	514	#ifdef CONFIG_SMP
	515	smp_ops = &chrp_smp_ops;
	516	#endif /* CONFIG_SMP */
	517	}