[net-next-2.6.git] / arch / powerpc / platforms / cell / spider-pic.c

/*
 * External Interrupt Controller on Spider South Bridge
 *
 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
 *
 * Author: Arnd Bergmann <arndb@de.ibm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/ioport.h>

#include <asm/pgtable.h>
#include <asm/prom.h>
#include <asm/io.h>

#include "interrupt.h"

/* register layout taken from Spider spec, table 7.4-4 */
enum {
	TIR_DEN		= 0x004, /* Detection Enable Register */
	TIR_MSK		= 0x084, /* Mask Level Register */
	TIR_EDC		= 0x0c0, /* Edge Detection Clear Register */
	TIR_PNDA	= 0x100, /* Pending Register A */
	TIR_PNDB	= 0x104, /* Pending Register B */
	TIR_CS		= 0x144, /* Current Status Register */
	TIR_LCSA	= 0x150, /* Level Current Status Register A */
	TIR_LCSB	= 0x154, /* Level Current Status Register B */
	TIR_LCSC	= 0x158, /* Level Current Status Register C */
	TIR_LCSD	= 0x15c, /* Level Current Status Register D */
	TIR_CFGA	= 0x200, /* Setting Register A0 */
	TIR_CFGB	= 0x204, /* Setting Register B0 */
			/* 0x208 ... 0x3ff Setting Register An/Bn */
	TIR_PPNDA	= 0x400, /* Packet Pending Register A */
	TIR_PPNDB	= 0x404, /* Packet Pending Register B */
	TIR_PIERA	= 0x408, /* Packet Output Error Register A */
	TIR_PIERB	= 0x40c, /* Packet Output Error Register B */
	TIR_PIEN	= 0x444, /* Packet Output Enable Register */
	TIR_PIPND	= 0x454, /* Packet Output Pending Register */
	TIRDID		= 0x484, /* Spider Device ID Register */
	REISTIM		= 0x500, /* Reissue Command Timeout Time Setting */
	REISTIMEN	= 0x504, /* Reissue Command Timeout Setting */
	REISWAITEN	= 0x508, /* Reissue Wait Control*/
};

#define SPIDER_CHIP_COUNT	4
#define SPIDER_SRC_COUNT	64
#define SPIDER_IRQ_INVALID	63

struct spider_pic {
	struct irq_host		*host;
	struct device_node	*of_node;
	void __iomem		*regs;
	unsigned int		node_id;
};
static struct spider_pic spider_pics[SPIDER_CHIP_COUNT];

static struct spider_pic *spider_virq_to_pic(unsigned int virq)
{
	return irq_map[virq].host->host_data;
}

static void __iomem *spider_get_irq_config(struct spider_pic *pic,
					   unsigned int src)
{
	return pic->regs + TIR_CFGA + 8 * src;
}

static void spider_unmask_irq(unsigned int virq)
{
	struct spider_pic *pic = spider_virq_to_pic(virq);
	void __iomem *cfg = spider_get_irq_config(pic, irq_map[virq].hwirq);

	out_be32(cfg, in_be32(cfg) | 0x30000000u);
}

static void spider_mask_irq(unsigned int virq)
{
	struct spider_pic *pic = spider_virq_to_pic(virq);
	void __iomem *cfg = spider_get_irq_config(pic, irq_map[virq].hwirq);

	out_be32(cfg, in_be32(cfg) & ~0x30000000u);
}

static void spider_ack_irq(unsigned int virq)
{
	struct spider_pic *pic = spider_virq_to_pic(virq);
	unsigned int src = irq_map[virq].hwirq;

	/* Reset edge detection logic if necessary
	 */
	if (get_irq_desc(virq)->status & IRQ_LEVEL)
		return;

	/* Only interrupts 47 to 50 can be set to edge */
	if (src < 47 || src > 50)
		return;

	/* Perform the clear of the edge logic */
	out_be32(pic->regs + TIR_EDC, 0x100 | (src & 0xf));
}

static int spider_set_irq_type(unsigned int virq, unsigned int type)
{
	unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
	struct spider_pic *pic = spider_virq_to_pic(virq);
	unsigned int hw = irq_map[virq].hwirq;
	void __iomem *cfg = spider_get_irq_config(pic, hw);
	struct irq_desc *desc = get_irq_desc(virq);
	u32 old_mask;
	u32 ic;

	/* Note that only level high is supported for most interrupts */
	if (sense != IRQ_TYPE_NONE && sense != IRQ_TYPE_LEVEL_HIGH &&
	    (hw < 47 || hw > 50))
		return -EINVAL;

	/* Decode sense type */
	switch(sense) {
	case IRQ_TYPE_EDGE_RISING:
		ic = 0x3;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		ic = 0x2;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		ic = 0x0;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
	case IRQ_TYPE_NONE:
		ic = 0x1;
		break;
	default:
		return -EINVAL;
	}

	/* Update irq_desc */
	desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
	desc->status |= type & IRQ_TYPE_SENSE_MASK;
	if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
		desc->status |= IRQ_LEVEL;

	/* Configure the source. One gross hack that was there before and
	 * that I've kept around is the priority to the BE which I set to
	 * be the same as the interrupt source number. I don't know wether
	 * that's supposed to make any kind of sense however, we'll have to
	 * decide that, but for now, I'm not changing the behaviour.
	 */
	old_mask = in_be32(cfg) & 0x30000000u;
	out_be32(cfg, old_mask | (ic << 24) | (0x7 << 16) |
		 (pic->node_id << 4) | 0xe);
	out_be32(cfg + 4, (0x2 << 16) | (hw & 0xff));

	return 0;
}

static struct irq_chip spider_pic = {
	.typename = " SPIDER   ",
	.unmask = spider_unmask_irq,
	.mask = spider_mask_irq,
	.ack = spider_ack_irq,
	.set_type = spider_set_irq_type,
};

static int spider_host_match(struct irq_host *h, struct device_node *node)
{
	struct spider_pic *pic = h->host_data;
	return node == pic->of_node;
}

static int spider_host_map(struct irq_host *h, unsigned int virq,
			irq_hw_number_t hw)
{
	set_irq_chip_and_handler(virq, &spider_pic, handle_level_irq);

	/* Set default irq type */
	set_irq_type(virq, IRQ_TYPE_NONE);

	return 0;
}

static int spider_host_xlate(struct irq_host *h, struct device_node *ct,
			   u32 *intspec, unsigned int intsize,
			   irq_hw_number_t *out_hwirq, unsigned int *out_flags)

{
	/* Spider interrupts have 2 cells, first is the interrupt source,
	 * second, well, I don't know for sure yet ... We mask the top bits
	 * because old device-trees encode a node number in there
	 */
	*out_hwirq = intspec[0] & 0x3f;
	*out_flags = IRQ_TYPE_LEVEL_HIGH;
	return 0;
}

static struct irq_host_ops spider_host_ops = {
	.match = spider_host_match,
	.map = spider_host_map,
	.xlate = spider_host_xlate,
};

static void spider_irq_cascade(unsigned int irq, struct irq_desc *desc)
{
	struct spider_pic *pic = desc->handler_data;
	unsigned int cs, virq;

	cs = in_be32(pic->regs + TIR_CS) >> 24;
	if (cs == SPIDER_IRQ_INVALID)
		virq = NO_IRQ;
	else
		virq = irq_linear_revmap(pic->host, cs);
	if (virq != NO_IRQ)
		generic_handle_irq(virq);
	desc->chip->eoi(irq);
}

/* For hooking up the cascace we have a problem. Our device-tree is
 * crap and we don't know on which BE iic interrupt we are hooked on at
 * least not the "standard" way. We can reconstitute it based on two
 * informations though: which BE node we are connected to and wether
 * we are connected to IOIF0 or IOIF1. Right now, we really only care
 * about the IBM cell blade and we know that its firmware gives us an
 * interrupt-map property which is pretty strange.
 */
static unsigned int __init spider_find_cascade_and_node(struct spider_pic *pic)
{
	unsigned int virq;
	const u32 *imap, *tmp;
	int imaplen, intsize, unit;
	struct device_node *iic;

	/* First, we check wether we have a real "interrupts" in the device
	 * tree in case the device-tree is ever fixed
	 */
	struct of_irq oirq;
	if (of_irq_map_one(pic->of_node, 0, &oirq) == 0) {
		virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
					     oirq.size);
		return virq;
	}

	/* Now do the horrible hacks */
	tmp = get_property(pic->of_node, "#interrupt-cells", NULL);
	if (tmp == NULL)
		return NO_IRQ;
	intsize = *tmp;
	imap = get_property(pic->of_node, "interrupt-map", &imaplen);
	if (imap == NULL || imaplen < (intsize + 1))
		return NO_IRQ;
	iic = of_find_node_by_phandle(imap[intsize]);
	if (iic == NULL)
		return NO_IRQ;
	imap += intsize + 1;
	tmp = get_property(iic, "#interrupt-cells", NULL);
	if (tmp == NULL)
		return NO_IRQ;
	intsize = *tmp;
	/* Assume unit is last entry of interrupt specifier */
	unit = imap[intsize - 1];
	/* Ok, we have a unit, now let's try to get the node */
	tmp = get_property(iic, "ibm,interrupt-server-ranges", NULL);
	if (tmp == NULL) {
		of_node_put(iic);
		return NO_IRQ;
	}
	/* ugly as hell but works for now */
	pic->node_id = (*tmp) >> 1;
	of_node_put(iic);

	/* Ok, now let's get cracking. You may ask me why I just didn't match
	 * the iic host from the iic OF node, but that way I'm still compatible
	 * with really really old old firmwares for which we don't have a node
	 */
	/* Manufacture an IIC interrupt number of class 2 */
	virq = irq_create_mapping(NULL,
				  (pic->node_id << IIC_IRQ_NODE_SHIFT) |
				  (2 << IIC_IRQ_CLASS_SHIFT) |
				  unit);
	if (virq == NO_IRQ)
		printk(KERN_ERR "spider_pic: failed to map cascade !");
	return virq;
}


static void __init spider_init_one(struct device_node *of_node, int chip,
				   unsigned long addr)
{
	struct spider_pic *pic = &spider_pics[chip];
	int i, virq;

	/* Map registers */
	pic->regs = ioremap(addr, 0x1000);
	if (pic->regs == NULL)
		panic("spider_pic: can't map registers !");

	/* Allocate a host */
	pic->host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, SPIDER_SRC_COUNT,
				   &spider_host_ops, SPIDER_IRQ_INVALID);
	if (pic->host == NULL)
		panic("spider_pic: can't allocate irq host !");
	pic->host->host_data = pic;

	/* Fill out other bits */
	pic->of_node = of_node_get(of_node);

	/* Go through all sources and disable them */
	for (i = 0; i < SPIDER_SRC_COUNT; i++) {
		void __iomem *cfg = pic->regs + TIR_CFGA + 8 * i;
		out_be32(cfg, in_be32(cfg) & ~0x30000000u);
	}

	/* do not mask any interrupts because of level */
	out_be32(pic->regs + TIR_MSK, 0x0);

	/* enable interrupt packets to be output */
	out_be32(pic->regs + TIR_PIEN, in_be32(pic->regs + TIR_PIEN) | 0x1);

	/* Hook up the cascade interrupt to the iic and nodeid */
	virq = spider_find_cascade_and_node(pic);
	if (virq == NO_IRQ)
		return;
	set_irq_data(virq, pic);
	set_irq_chained_handler(virq, spider_irq_cascade);

	printk(KERN_INFO "spider_pic: node %d, addr: 0x%lx %s\n",
	       pic->node_id, addr, of_node->full_name);

	/* Enable the interrupt detection enable bit. Do this last! */
	out_be32(pic->regs + TIR_DEN, in_be32(pic->regs + TIR_DEN) | 0x1);
}

void __init spider_init_IRQ(void)
{
	struct resource r;
	struct device_node *dn;
	int chip = 0;

	/* XXX node numbers are totally bogus. We _hope_ we get the device
	 * nodes in the right order here but that's definitely not guaranteed,
	 * we need to get the node from the device tree instead.
	 * There is currently no proper property for it (but our whole
	 * device-tree is bogus anyway) so all we can do is pray or maybe test
	 * the address and deduce the node-id
	 */
	for (dn = NULL;
	     (dn = of_find_node_by_name(dn, "interrupt-controller"));) {
		if (device_is_compatible(dn, "CBEA,platform-spider-pic")) {
			if (of_address_to_resource(dn, 0, &r)) {
				printk(KERN_WARNING "spider-pic: Failed\n");
				continue;
			}
		} else if (device_is_compatible(dn, "sti,platform-spider-pic")
			   && (chip < 2)) {
			static long hard_coded_pics[] =
				{ 0x24000008000ul, 0x34000008000ul};
			r.start = hard_coded_pics[chip];
		} else
			continue;
		spider_init_one(dn, chip++, r.start);
	}
}
Commit	Line	Data
cebf589c AB	1	/*
	2	* External Interrupt Controller on Spider South Bridge
	3	*
	4	* (C) Copyright IBM Deutschland Entwicklung GmbH 2005
	5	*
	6	* Author: Arnd Bergmann <arndb@de.ibm.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2, or (at your option)
	11	* any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
	23	#include <linux/interrupt.h>
	24	#include <linux/irq.h>
0ebfff14	25	#include <linux/ioport.h>
cebf589c AB	26
	27	#include <asm/pgtable.h>
	28	#include <asm/prom.h>
	29	#include <asm/io.h>
	30
f3f66f59	31	#include "interrupt.h"
cebf589c AB	32
	33	/* register layout taken from Spider spec, table 7.4-4 */
	34	enum {
	35	TIR_DEN = 0x004, /* Detection Enable Register */
	36	TIR_MSK = 0x084, /* Mask Level Register */
	37	TIR_EDC = 0x0c0, /* Edge Detection Clear Register */
	38	TIR_PNDA = 0x100, /* Pending Register A */
	39	TIR_PNDB = 0x104, /* Pending Register B */
	40	TIR_CS = 0x144, /* Current Status Register */
	41	TIR_LCSA = 0x150, /* Level Current Status Register A */
	42	TIR_LCSB = 0x154, /* Level Current Status Register B */
	43	TIR_LCSC = 0x158, /* Level Current Status Register C */
	44	TIR_LCSD = 0x15c, /* Level Current Status Register D */
	45	TIR_CFGA = 0x200, /* Setting Register A0 */
	46	TIR_CFGB = 0x204, /* Setting Register B0 */
	47	/* 0x208 ... 0x3ff Setting Register An/Bn */
	48	TIR_PPNDA = 0x400, /* Packet Pending Register A */
	49	TIR_PPNDB = 0x404, /* Packet Pending Register B */
	50	TIR_PIERA = 0x408, /* Packet Output Error Register A */
	51	TIR_PIERB = 0x40c, /* Packet Output Error Register B */
	52	TIR_PIEN = 0x444, /* Packet Output Enable Register */
	53	TIR_PIPND = 0x454, /* Packet Output Pending Register */
	54	TIRDID = 0x484, /* Spider Device ID Register */
	55	REISTIM = 0x500, /* Reissue Command Timeout Time Setting */
	56	REISTIMEN = 0x504, /* Reissue Command Timeout Setting */
	57	REISWAITEN = 0x508, /* Reissue Wait Control*/
	58	};
	59
0ebfff14 BH	60	#define SPIDER_CHIP_COUNT 4
	61	#define SPIDER_SRC_COUNT 64
	62	#define SPIDER_IRQ_INVALID 63
cebf589c	63
0ebfff14 BH	64	struct spider_pic {
	65	struct irq_host *host;
	66	struct device_node *of_node;
	67	void __iomem *regs;
	68	unsigned int node_id;
	69	};
	70	static struct spider_pic spider_pics[SPIDER_CHIP_COUNT];
cebf589c	71
0ebfff14	72	static struct spider_pic *spider_virq_to_pic(unsigned int virq)
cebf589c	73	{
0ebfff14	74	return irq_map[virq].host->host_data;
cebf589c AB	75	}
cebf589c AB	76
0ebfff14 BH	77	static void __iomem spider_get_irq_config(struct spider_pic pic,
0ebfff14 BH	78	unsigned int src)
cebf589c	79	{
0ebfff14	80	return pic->regs + TIR_CFGA + 8 * src;
cebf589c AB	81	}
cebf589c AB	82
0ebfff14	83	static void spider_unmask_irq(unsigned int virq)
cebf589c	84	{
0ebfff14 BH	85	struct spider_pic *pic = spider_virq_to_pic(virq);
0ebfff14 BH	86	void __iomem *cfg = spider_get_irq_config(pic, irq_map[virq].hwirq);
cebf589c	87
0ebfff14	88	out_be32(cfg, in_be32(cfg) \| 0x30000000u);
cebf589c AB	89	}
cebf589c AB	90
0ebfff14	91	static void spider_mask_irq(unsigned int virq)
cebf589c	92	{
0ebfff14 BH	93	struct spider_pic *pic = spider_virq_to_pic(virq);
0ebfff14 BH	94	void __iomem *cfg = spider_get_irq_config(pic, irq_map[virq].hwirq);
cebf589c AB	95
	96	out_be32(cfg, in_be32(cfg) & ~0x30000000u);
	97	}
	98
0ebfff14	99	static void spider_ack_irq(unsigned int virq)
cebf589c	100	{
0ebfff14 BH	101	struct spider_pic *pic = spider_virq_to_pic(virq);
	102	unsigned int src = irq_map[virq].hwirq;
	103
	104	/* Reset edge detection logic if necessary
b9e5b4e6	105	*/
0ebfff14 BH	106	if (get_irq_desc(virq)->status & IRQ_LEVEL)
	107	return;
	108
	109	/* Only interrupts 47 to 50 can be set to edge */
	110	if (src < 47 \|\| src > 50)
	111	return;
	112
	113	/* Perform the clear of the edge logic */
	114	out_be32(pic->regs + TIR_EDC, 0x100 \| (src & 0xf));
cebf589c AB	115	}
cebf589c AB	116
6e99e458	117	static int spider_set_irq_type(unsigned int virq, unsigned int type)
cebf589c	118	{
6e99e458 BH	119	unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
	120	struct spider_pic *pic = spider_virq_to_pic(virq);
	121	unsigned int hw = irq_map[virq].hwirq;
0ebfff14	122	void __iomem *cfg = spider_get_irq_config(pic, hw);
6e99e458 BH	123	struct irq_desc *desc = get_irq_desc(virq);
6e99e458 BH	124	u32 old_mask;
0ebfff14 BH	125	u32 ic;
	126
	127	/* Note that only level high is supported for most interrupts */
	128	if (sense != IRQ_TYPE_NONE && sense != IRQ_TYPE_LEVEL_HIGH &&
	129	(hw < 47 \|\| hw > 50))
	130	return -EINVAL;
	131
	132	/* Decode sense type */
	133	switch(sense) {
	134	case IRQ_TYPE_EDGE_RISING:
	135	ic = 0x3;
	136	break;
	137	case IRQ_TYPE_EDGE_FALLING:
	138	ic = 0x2;
	139	break;
	140	case IRQ_TYPE_LEVEL_LOW:
	141	ic = 0x0;
0ebfff14 BH	142	break;
	143	case IRQ_TYPE_LEVEL_HIGH:
	144	case IRQ_TYPE_NONE:
	145	ic = 0x1;
0ebfff14 BH	146	break;
	147	default:
	148	return -EINVAL;
	149	}
cebf589c	150
6e99e458 BH	151	/* Update irq_desc */
	152	desc->status &= ~(IRQ_TYPE_SENSE_MASK \| IRQ_LEVEL);
	153	desc->status \|= type & IRQ_TYPE_SENSE_MASK;
	154	if (type & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW))
	155	desc->status \|= IRQ_LEVEL;
	156
0ebfff14 BH	157	/* Configure the source. One gross hack that was there before and
	158	* that I've kept around is the priority to the BE which I set to
	159	* be the same as the interrupt source number. I don't know wether
	160	* that's supposed to make any kind of sense however, we'll have to
	161	* decide that, but for now, I'm not changing the behaviour.
	162	*/
6e99e458 BH	163	old_mask = in_be32(cfg) & 0x30000000u;
	164	out_be32(cfg, old_mask \| (ic << 24) \| (0x7 << 16) \|
	165	(pic->node_id << 4) \| 0xe);
0ebfff14	166	out_be32(cfg + 4, (0x2 << 16) \| (hw & 0xff));
cebf589c	167
6e99e458 BH	168	return 0;
	169	}
	170
	171	static struct irq_chip spider_pic = {
	172	.typename = " SPIDER ",
	173	.unmask = spider_unmask_irq,
	174	.mask = spider_mask_irq,
	175	.ack = spider_ack_irq,
	176	.set_type = spider_set_irq_type,
	177	};
	178
	179	static int spider_host_match(struct irq_host h, struct device_node node)
	180	{
	181	struct spider_pic *pic = h->host_data;
	182	return node == pic->of_node;
	183	}
	184
	185	static int spider_host_map(struct irq_host *h, unsigned int virq,
	186	irq_hw_number_t hw)
	187	{
0ebfff14	188	set_irq_chip_and_handler(virq, &spider_pic, handle_level_irq);
6e99e458 BH	189
	190	/* Set default irq type */
	191	set_irq_type(virq, IRQ_TYPE_NONE);
	192
0ebfff14 BH	193	return 0;
	194	}
	195
	196	static int spider_host_xlate(struct irq_host h, struct device_node ct,
	197	u32 *intspec, unsigned int intsize,
	198	irq_hw_number_t out_hwirq, unsigned int out_flags)
	199
	200	{
	201	/* Spider interrupts have 2 cells, first is the interrupt source,
	202	* second, well, I don't know for sure yet ... We mask the top bits
	203	* because old device-trees encode a node number in there
	204	*/
	205	*out_hwirq = intspec[0] & 0x3f;
	206	*out_flags = IRQ_TYPE_LEVEL_HIGH;
	207	return 0;
cebf589c	208	}
d0e57c68	209
0ebfff14 BH	210	static struct irq_host_ops spider_host_ops = {
	211	.match = spider_host_match,
	212	.map = spider_host_map,
	213	.xlate = spider_host_xlate,
	214	};
	215
7d12e780	216	static void spider_irq_cascade(unsigned int irq, struct irq_desc *desc)
b9e5b4e6	217	{
0ebfff14 BH	218	struct spider_pic *pic = desc->handler_data;
0ebfff14 BH	219	unsigned int cs, virq;
b9e5b4e6	220
0ebfff14 BH	221	cs = in_be32(pic->regs + TIR_CS) >> 24;
	222	if (cs == SPIDER_IRQ_INVALID)
	223	virq = NO_IRQ;
	224	else
	225	virq = irq_linear_revmap(pic->host, cs);
	226	if (virq != NO_IRQ)
7d12e780	227	generic_handle_irq(virq);
b9e5b4e6 BH	228	desc->chip->eoi(irq);
	229	}
	230
0ebfff14 BH	231	/* For hooking up the cascace we have a problem. Our device-tree is
	232	* crap and we don't know on which BE iic interrupt we are hooked on at
	233	* least not the "standard" way. We can reconstitute it based on two
	234	* informations though: which BE node we are connected to and wether
	235	* we are connected to IOIF0 or IOIF1. Right now, we really only care
	236	* about the IBM cell blade and we know that its firmware gives us an
	237	* interrupt-map property which is pretty strange.
	238	*/
	239	static unsigned int __init spider_find_cascade_and_node(struct spider_pic *pic)
	240	{
	241	unsigned int virq;
c61c27d5	242	const u32 imap, tmp;
0ebfff14 BH	243	int imaplen, intsize, unit;
0ebfff14 BH	244	struct device_node *iic;
0ebfff14	245
0ebfff14 BH	246	/* First, we check wether we have a real "interrupts" in the device
	247	* tree in case the device-tree is ever fixed
	248	*/
	249	struct of_irq oirq;
	250	if (of_irq_map_one(pic->of_node, 0, &oirq) == 0) {
	251	virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
	252	oirq.size);
f7e2ce78	253	return virq;
0ebfff14	254	}
0ebfff14 BH	255
0ebfff14 BH	256	/* Now do the horrible hacks */
c61c27d5	257	tmp = get_property(pic->of_node, "#interrupt-cells", NULL);
0ebfff14 BH	258	if (tmp == NULL)
	259	return NO_IRQ;
	260	intsize = *tmp;
c61c27d5	261	imap = get_property(pic->of_node, "interrupt-map", &imaplen);
0ebfff14 BH	262	if (imap == NULL \|\| imaplen < (intsize + 1))
	263	return NO_IRQ;
	264	iic = of_find_node_by_phandle(imap[intsize]);
	265	if (iic == NULL)
	266	return NO_IRQ;
	267	imap += intsize + 1;
c61c27d5	268	tmp = get_property(iic, "#interrupt-cells", NULL);
0ebfff14 BH	269	if (tmp == NULL)
	270	return NO_IRQ;
	271	intsize = *tmp;
	272	/* Assume unit is last entry of interrupt specifier */
	273	unit = imap[intsize - 1];
	274	/* Ok, we have a unit, now let's try to get the node */
c61c27d5	275	tmp = get_property(iic, "ibm,interrupt-server-ranges", NULL);
0ebfff14 BH	276	if (tmp == NULL) {
	277	of_node_put(iic);
	278	return NO_IRQ;
	279	}
	280	/* ugly as hell but works for now */
	281	pic->node_id = (*tmp) >> 1;
	282	of_node_put(iic);
	283
	284	/* Ok, now let's get cracking. You may ask me why I just didn't match
	285	* the iic host from the iic OF node, but that way I'm still compatible
	286	* with really really old old firmwares for which we don't have a node
	287	*/
0ebfff14	288	/* Manufacture an IIC interrupt number of class 2 */
2e194583 BH	289	virq = irq_create_mapping(NULL,
	290	(pic->node_id << IIC_IRQ_NODE_SHIFT) \|
	291	(2 << IIC_IRQ_CLASS_SHIFT) \|
	292	unit);
0ebfff14 BH	293	if (virq == NO_IRQ)
	294	printk(KERN_ERR "spider_pic: failed to map cascade !");
	295	return virq;
	296	}
	297
d0e57c68	298
0ebfff14 BH	299	static void __init spider_init_one(struct device_node *of_node, int chip,
0ebfff14 BH	300	unsigned long addr)
cebf589c	301	{
0ebfff14 BH	302	struct spider_pic *pic = &spider_pics[chip];
0ebfff14 BH	303	int i, virq;
b9e5b4e6	304
0ebfff14 BH	305	/* Map registers */
	306	pic->regs = ioremap(addr, 0x1000);
	307	if (pic->regs == NULL)
b9e5b4e6 BH	308	panic("spider_pic: can't map registers !");
b9e5b4e6 BH	309
0ebfff14 BH	310	/* Allocate a host */
	311	pic->host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, SPIDER_SRC_COUNT,
	312	&spider_host_ops, SPIDER_IRQ_INVALID);
	313	if (pic->host == NULL)
	314	panic("spider_pic: can't allocate irq host !");
	315	pic->host->host_data = pic;
b9e5b4e6	316
0ebfff14 BH	317	/* Fill out other bits */
	318	pic->of_node = of_node_get(of_node);
	319
	320	/* Go through all sources and disable them */
	321	for (i = 0; i < SPIDER_SRC_COUNT; i++) {
	322	void __iomem cfg = pic->regs + TIR_CFGA + 8 i;
	323	out_be32(cfg, in_be32(cfg) & ~0x30000000u);
d0e57c68	324	}
b9e5b4e6 BH	325
b9e5b4e6 BH	326	/* do not mask any interrupts because of level */
0ebfff14	327	out_be32(pic->regs + TIR_MSK, 0x0);
b9e5b4e6 BH	328
b9e5b4e6 BH	329	/* enable interrupt packets to be output */
0ebfff14	330	out_be32(pic->regs + TIR_PIEN, in_be32(pic->regs + TIR_PIEN) \| 0x1);
b9e5b4e6	331
0ebfff14 BH	332	/* Hook up the cascade interrupt to the iic and nodeid */
	333	virq = spider_find_cascade_and_node(pic);
	334	if (virq == NO_IRQ)
	335	return;
	336	set_irq_data(virq, pic);
	337	set_irq_chained_handler(virq, spider_irq_cascade);
	338
	339	printk(KERN_INFO "spider_pic: node %d, addr: 0x%lx %s\n",
	340	pic->node_id, addr, of_node->full_name);
b9e5b4e6 BH	341
b9e5b4e6 BH	342	/* Enable the interrupt detection enable bit. Do this last! */
0ebfff14	343	out_be32(pic->regs + TIR_DEN, in_be32(pic->regs + TIR_DEN) \| 0x1);
d0e57c68 JO	344	}
d0e57c68 JO	345
b9e5b4e6	346	void __init spider_init_IRQ(void)
d0e57c68	347	{
0ebfff14	348	struct resource r;
d0e57c68	349	struct device_node *dn;
0ebfff14 BH	350	int chip = 0;
	351
	352	/* XXX node numbers are totally bogus. We _hope_ we get the device
	353	* nodes in the right order here but that's definitely not guaranteed,
	354	* we need to get the node from the device tree instead.
	355	* There is currently no proper property for it (but our whole
	356	* device-tree is bogus anyway) so all we can do is pray or maybe test
	357	* the address and deduce the node-id
b9e5b4e6	358	*/
0ebfff14 BH	359	for (dn = NULL;
	360	(dn = of_find_node_by_name(dn, "interrupt-controller"));) {
	361	if (device_is_compatible(dn, "CBEA,platform-spider-pic")) {
	362	if (of_address_to_resource(dn, 0, &r)) {
	363	printk(KERN_WARNING "spider-pic: Failed\n");
	364	continue;
	365	}
	366	} else if (device_is_compatible(dn, "sti,platform-spider-pic")
	367	&& (chip < 2)) {
	368	static long hard_coded_pics[] =
43b4f406	369	{ 0x24000008000ul, 0x34000008000ul};
0ebfff14	370	r.start = hard_coded_pics[chip];
d0e57c68 JO	371	} else
d0e57c68 JO	372	continue;
0ebfff14	373	spider_init_one(dn, chip++, r.start);
cebf589c AB	374	}
cebf589c AB	375	}