[net-next-2.6.git] / arch / powerpc / platforms / 85xx / mpc85xx_mds.c

/*
 * Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved.
 *
 * Author: Andy Fleming <afleming@freescale.com>
 *
 * Based on 83xx/mpc8360e_pb.c by:
 *	   Li Yang <LeoLi@freescale.com>
 *	   Yin Olivia <Hong-hua.Yin@freescale.com>
 *
 * Description:
 * MPC85xx MDS board specific routines.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/major.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/initrd.h>
#include <linux/module.h>
#include <linux/fsl_devices.h>
#include <linux/of_platform.h>
#include <linux/of_device.h>
#include <linux/phy.h>
#include <linux/lmb.h>

#include <asm/system.h>
#include <asm/atomic.h>
#include <asm/time.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/irq.h>
#include <mm/mmu_decl.h>
#include <asm/prom.h>
#include <asm/udbg.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include <sysdev/simple_gpio.h>
#include <asm/qe.h>
#include <asm/qe_ic.h>
#include <asm/mpic.h>
#include <asm/swiotlb.h>

#undef DEBUG
#ifdef DEBUG
#define DBG(fmt...) udbg_printf(fmt)
#else
#define DBG(fmt...)
#endif

#define MV88E1111_SCR	0x10
#define MV88E1111_SCR_125CLK	0x0010
static int mpc8568_fixup_125_clock(struct phy_device *phydev)
{
	int scr;
	int err;

	/* Workaround for the 125 CLK Toggle */
	scr = phy_read(phydev, MV88E1111_SCR);

	if (scr < 0)
		return scr;

	err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));

	if (err)
		return err;

	err = phy_write(phydev, MII_BMCR, BMCR_RESET);

	if (err)
		return err;

	scr = phy_read(phydev, MV88E1111_SCR);

	if (scr < 0)
		return scr;

	err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);

	return err;
}

static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
{
	int temp;
	int err;

	/* Errata */
	err = phy_write(phydev,29, 0x0006);

	if (err)
		return err;

	temp = phy_read(phydev, 30);

	if (temp < 0)
		return temp;

	temp = (temp & (~0x8000)) | 0x4000;
	err = phy_write(phydev,30, temp);

	if (err)
		return err;

	err = phy_write(phydev,29, 0x000a);

	if (err)
		return err;

	temp = phy_read(phydev, 30);

	if (temp < 0)
		return temp;

	temp = phy_read(phydev, 30);

	if (temp < 0)
		return temp;

	temp &= ~0x0020;

	err = phy_write(phydev,30,temp);

	if (err)
		return err;

	/* Disable automatic MDI/MDIX selection */
	temp = phy_read(phydev, 16);

	if (temp < 0)
		return temp;

	temp &= ~0x0060;
	err = phy_write(phydev,16,temp);

	return err;
}

/* ************************************************************************
 *
 * Setup the architecture
 *
 */
static void __init mpc85xx_mds_setup_arch(void)
{
	struct device_node *np;
	static u8 __iomem *bcsr_regs = NULL;
#ifdef CONFIG_PCI
	struct pci_controller *hose;
#endif
	dma_addr_t max = 0xffffffff;

	if (ppc_md.progress)
		ppc_md.progress("mpc85xx_mds_setup_arch()", 0);

	/* Map BCSR area */
	np = of_find_node_by_name(NULL, "bcsr");
	if (np != NULL) {
		struct resource res;

		of_address_to_resource(np, 0, &res);
		bcsr_regs = ioremap(res.start, res.end - res.start +1);
		of_node_put(np);
	}

#ifdef CONFIG_PCI
	for_each_node_by_type(np, "pci") {
		if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
		    of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
			struct resource rsrc;
			of_address_to_resource(np, 0, &rsrc);
			if ((rsrc.start & 0xfffff) == 0x8000)
				fsl_add_bridge(np, 1);
			else
				fsl_add_bridge(np, 0);

			hose = pci_find_hose_for_OF_device(np);
			max = min(max, hose->dma_window_base_cur +
					hose->dma_window_size);
		}
	}
#endif

#ifdef CONFIG_QUICC_ENGINE
	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
	if (!np) {
		np = of_find_node_by_name(NULL, "qe");
		if (!np)
			return;
	}

	qe_reset();
	of_node_put(np);

	np = of_find_node_by_name(NULL, "par_io");
	if (np) {
		struct device_node *ucc;

		par_io_init(np);
		of_node_put(np);

		for_each_node_by_name(ucc, "ucc")
			par_io_of_config(ucc);
	}

	if (bcsr_regs) {
		if (machine_is(mpc8568_mds)) {
#define BCSR_UCC1_GETH_EN	(0x1 << 7)
#define BCSR_UCC2_GETH_EN	(0x1 << 7)
#define BCSR_UCC1_MODE_MSK	(0x3 << 4)
#define BCSR_UCC2_MODE_MSK	(0x3 << 0)

			/* Turn off UCC1 & UCC2 */
			clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
			clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);

			/* Mode is RGMII, all bits clear */
			clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
						 BCSR_UCC2_MODE_MSK);

			/* Turn UCC1 & UCC2 on */
			setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
			setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
		} else if (machine_is(mpc8569_mds)) {
#define BCSR7_UCC12_GETHnRST	(0x1 << 2)
#define BCSR8_UEM_MARVELL_RST	(0x1 << 1)
			/*
			 * U-Boot mangles interrupt polarity for Marvell PHYs,
			 * so reset built-in and UEM Marvell PHYs, this puts
			 * the PHYs into their normal state.
			 */
			clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
			setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);

			setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
			clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
		}
		iounmap(bcsr_regs);
	}
#endif	/* CONFIG_QUICC_ENGINE */

#ifdef CONFIG_SWIOTLB
	if (lmb_end_of_DRAM() > max) {
		ppc_swiotlb_enable = 1;
		set_pci_dma_ops(&swiotlb_dma_ops);
		ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
	}
#endif
}


static int __init board_fixups(void)
{
	char phy_id[20];
	char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
	struct device_node *mdio;
	struct resource res;
	int i;

	for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
		mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);

		of_address_to_resource(mdio, 0, &res);
		snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
			(unsigned long long)res.start, 1);

		phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
		phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);

		/* Register a workaround for errata */
		snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
			(unsigned long long)res.start, 7);
		phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);

		of_node_put(mdio);
	}

	return 0;
}
machine_arch_initcall(mpc8568_mds, board_fixups);
machine_arch_initcall(mpc8569_mds, board_fixups);

static struct of_device_id mpc85xx_ids[] = {
	{ .type = "soc", },
	{ .compatible = "soc", },
	{ .compatible = "simple-bus", },
	{ .type = "qe", },
	{ .compatible = "fsl,qe", },
	{ .compatible = "gianfar", },
	{ .compatible = "fsl,rapidio-delta", },
	{ .compatible = "fsl,mpc8548-guts", },
	{},
};

static int __init mpc85xx_publish_devices(void)
{
	if (machine_is(mpc8569_mds))
		simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");

	/* Publish the QE devices */
	of_platform_bus_probe(NULL, mpc85xx_ids, NULL);

	return 0;
}
machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);

machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);

static void __init mpc85xx_mds_pic_init(void)
{
	struct mpic *mpic;
	struct resource r;
	struct device_node *np = NULL;

	np = of_find_node_by_type(NULL, "open-pic");
	if (!np)
		return;

	if (of_address_to_resource(np, 0, &r)) {
		printk(KERN_ERR "Failed to map mpic register space\n");
		of_node_put(np);
		return;
	}

	mpic = mpic_alloc(np, r.start,
			MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
			MPIC_BROKEN_FRR_NIRQS,
			0, 256, " OpenPIC  ");
	BUG_ON(mpic == NULL);
	of_node_put(np);

	mpic_init(mpic);

#ifdef CONFIG_QUICC_ENGINE
	np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
	if (!np) {
		np = of_find_node_by_type(NULL, "qeic");
		if (!np)
			return;
	}
	qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
	of_node_put(np);
#endif				/* CONFIG_QUICC_ENGINE */
}

static int __init mpc85xx_mds_probe(void)
{
        unsigned long root = of_get_flat_dt_root();

        return of_flat_dt_is_compatible(root, "MPC85xxMDS");
}

define_machine(mpc8568_mds) {
	.name		= "MPC8568 MDS",
	.probe		= mpc85xx_mds_probe,
	.setup_arch	= mpc85xx_mds_setup_arch,
	.init_IRQ	= mpc85xx_mds_pic_init,
	.get_irq	= mpic_get_irq,
	.restart	= fsl_rstcr_restart,
	.calibrate_decr	= generic_calibrate_decr,
	.progress	= udbg_progress,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
};

static int __init mpc8569_mds_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
}

define_machine(mpc8569_mds) {
	.name		= "MPC8569 MDS",
	.probe		= mpc8569_mds_probe,
	.setup_arch	= mpc85xx_mds_setup_arch,
	.init_IRQ	= mpc85xx_mds_pic_init,
	.get_irq	= mpic_get_irq,
	.restart	= fsl_rstcr_restart,
	.calibrate_decr	= generic_calibrate_decr,
	.progress	= udbg_progress,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
};
Commit	Line	Data
c2882bb1 AF	1	/*
	2	* Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved.
	3	*
	4	* Author: Andy Fleming <afleming@freescale.com>
	5	*
	6	* Based on 83xx/mpc8360e_pb.c by:
	7	* Li Yang <LeoLi@freescale.com>
	8	* Yin Olivia <Hong-hua.Yin@freescale.com>
	9	*
	10	* Description:
23f510bc	11	* MPC85xx MDS board specific routines.
c2882bb1 AF	12	*
	13	* This program is free software; you can redistribute it and/or modify it
	14	* under the terms of the GNU General Public License as published by the
	15	* Free Software Foundation; either version 2 of the License, or (at your
	16	* option) any later version.
	17	*/
	18
	19	#include <linux/stddef.h>
	20	#include <linux/kernel.h>
	21	#include <linux/init.h>
	22	#include <linux/errno.h>
	23	#include <linux/reboot.h>
	24	#include <linux/pci.h>
	25	#include <linux/kdev_t.h>
	26	#include <linux/major.h>
	27	#include <linux/console.h>
	28	#include <linux/delay.h>
	29	#include <linux/seq_file.h>
c2882bb1 AF	30	#include <linux/initrd.h>
	31	#include <linux/module.h>
	32	#include <linux/fsl_devices.h>
882407b9 JL	33	#include <linux/of_platform.h>
882407b9 JL	34	#include <linux/of_device.h>
94833a42	35	#include <linux/phy.h>
152d0182	36	#include <linux/lmb.h>
c2882bb1	37
c2882bb1 AF	38	#include <asm/system.h>
	39	#include <asm/atomic.h>
	40	#include <asm/time.h>
	41	#include <asm/io.h>
	42	#include <asm/machdep.h>
c2882bb1	43	#include <asm/pci-bridge.h>
c2882bb1 AF	44	#include <asm/irq.h>
	45	#include <mm/mmu_decl.h>
	46	#include <asm/prom.h>
	47	#include <asm/udbg.h>
	48	#include <sysdev/fsl_soc.h>
3f6c5dae	49	#include <sysdev/fsl_pci.h>
9b9d401b	50	#include <sysdev/simple_gpio.h>
c2882bb1 AF	51	#include <asm/qe.h>
	52	#include <asm/qe_ic.h>
	53	#include <asm/mpic.h>
152d0182	54	#include <asm/swiotlb.h>
c2882bb1	55
c2882bb1 AF	56	#undef DEBUG
	57	#ifdef DEBUG
	58	#define DBG(fmt...) udbg_printf(fmt)
	59	#else
	60	#define DBG(fmt...)
	61	#endif
	62
94833a42 AF	63	#define MV88E1111_SCR 0x10
	64	#define MV88E1111_SCR_125CLK 0x0010
	65	static int mpc8568_fixup_125_clock(struct phy_device *phydev)
	66	{
	67	int scr;
	68	int err;
	69
	70	/* Workaround for the 125 CLK Toggle */
	71	scr = phy_read(phydev, MV88E1111_SCR);
	72
	73	if (scr < 0)
	74	return scr;
	75
	76	err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
	77
	78	if (err)
	79	return err;
	80
	81	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	82
	83	if (err)
	84	return err;
	85
	86	scr = phy_read(phydev, MV88E1111_SCR);
	87
	88	if (scr < 0)
29827b02	89	return scr;
94833a42 AF	90
	91	err = phy_write(phydev, MV88E1111_SCR, scr \| 0x0008);
	92
	93	return err;
	94	}
	95
	96	static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
	97	{
	98	int temp;
	99	int err;
	100
	101	/* Errata */
	102	err = phy_write(phydev,29, 0x0006);
	103
	104	if (err)
	105	return err;
	106
	107	temp = phy_read(phydev, 30);
	108
	109	if (temp < 0)
	110	return temp;
	111
	112	temp = (temp & (~0x8000)) \| 0x4000;
	113	err = phy_write(phydev,30, temp);
	114
	115	if (err)
	116	return err;
	117
	118	err = phy_write(phydev,29, 0x000a);
	119
	120	if (err)
	121	return err;
	122
	123	temp = phy_read(phydev, 30);
	124
	125	if (temp < 0)
	126	return temp;
	127
	128	temp = phy_read(phydev, 30);
	129
	130	if (temp < 0)
	131	return temp;
	132
	133	temp &= ~0x0020;
	134
	135	err = phy_write(phydev,30,temp);
	136
	137	if (err)
	138	return err;
	139
	140	/* Disable automatic MDI/MDIX selection */
	141	temp = phy_read(phydev, 16);
	142
	143	if (temp < 0)
	144	return temp;
	145
	146	temp &= ~0x0060;
	147	err = phy_write(phydev,16,temp);
	148
	149	return err;
	150	}
	151
c2882bb1 AF	152	/* ************************************************************************
	153	*
	154	* Setup the architecture
	155	*
	156	*/
23f510bc	157	static void __init mpc85xx_mds_setup_arch(void)
c2882bb1 AF	158	{
c2882bb1 AF	159	struct device_node *np;
73f5b8f9	160	static u8 __iomem *bcsr_regs = NULL;
152d0182 KG	161	#ifdef CONFIG_PCI
	162	struct pci_controller *hose;
	163	#endif
	164	dma_addr_t max = 0xffffffff;
c2882bb1	165
c2882bb1	166	if (ppc_md.progress)
23f510bc	167	ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
c2882bb1	168
c2882bb1 AF	169	/* Map BCSR area */
	170	np = of_find_node_by_name(NULL, "bcsr");
	171	if (np != NULL) {
	172	struct resource res;
	173
	174	of_address_to_resource(np, 0, &res);
	175	bcsr_regs = ioremap(res.start, res.end - res.start +1);
	176	of_node_put(np);
	177	}
	178
	179	#ifdef CONFIG_PCI
c9438aff KG	180	for_each_node_by_type(np, "pci") {
	181	if (of_device_is_compatible(np, "fsl,mpc8540-pci") \|\|
	182	of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
	183	struct resource rsrc;
	184	of_address_to_resource(np, 0, &rsrc);
	185	if ((rsrc.start & 0xfffff) == 0x8000)
	186	fsl_add_bridge(np, 1);
	187	else
	188	fsl_add_bridge(np, 0);
152d0182 KG	189
	190	hose = pci_find_hose_for_OF_device(np);
	191	max = min(max, hose->dma_window_base_cur +
	192	hose->dma_window_size);
c9438aff KG	193	}
c9438aff KG	194	}
c2882bb1 AF	195	#endif
	196
	197	#ifdef CONFIG_QUICC_ENGINE
a2dd70a1 AV	198	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
	199	if (!np) {
	200	np = of_find_node_by_name(NULL, "qe");
	201	if (!np)
	202	return;
c2882bb1 AF	203	}
c2882bb1 AF	204
a2dd70a1 AV	205	qe_reset();
	206	of_node_put(np);
	207
	208	np = of_find_node_by_name(NULL, "par_io");
	209	if (np) {
	210	struct device_node *ucc;
c2882bb1 AF	211
	212	par_io_init(np);
	213	of_node_put(np);
	214
a2dd70a1	215	for_each_node_by_name(ucc, "ucc")
c2882bb1	216	par_io_of_config(ucc);
c2882bb1 AF	217	}
	218
	219	if (bcsr_regs) {
ea5130dc	220	if (machine_is(mpc8568_mds)) {
803dedb6 AV	221	#define BCSR_UCC1_GETH_EN (0x1 << 7)
	222	#define BCSR_UCC2_GETH_EN (0x1 << 7)
	223	#define BCSR_UCC1_MODE_MSK (0x3 << 4)
	224	#define BCSR_UCC2_MODE_MSK (0x3 << 0)
	225
ea5130dc HW	226	/* Turn off UCC1 & UCC2 */
	227	clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
	228	clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
803dedb6	229
ea5130dc HW	230	/* Mode is RGMII, all bits clear */
	231	clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK \|
	232	BCSR_UCC2_MODE_MSK);
c2882bb1	233
ea5130dc HW	234	/* Turn UCC1 & UCC2 on */
	235	setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
	236	setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
c4673f9a AV	237	} else if (machine_is(mpc8569_mds)) {
	238	#define BCSR7_UCC12_GETHnRST (0x1 << 2)
	239	#define BCSR8_UEM_MARVELL_RST (0x1 << 1)
	240	/*
	241	* U-Boot mangles interrupt polarity for Marvell PHYs,
	242	* so reset built-in and UEM Marvell PHYs, this puts
	243	* the PHYs into their normal state.
	244	*/
	245	clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
	246	setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
	247
	248	setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
	249	clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
ea5130dc	250	}
c2882bb1 AF	251	iounmap(bcsr_regs);
c2882bb1 AF	252	}
c2882bb1	253	#endif /* CONFIG_QUICC_ENGINE */
152d0182 KG	254
	255	#ifdef CONFIG_SWIOTLB
	256	if (lmb_end_of_DRAM() > max) {
	257	ppc_swiotlb_enable = 1;
3702977f	258	set_pci_dma_ops(&swiotlb_dma_ops);
762afb73	259	ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
152d0182 KG	260	}
152d0182 KG	261	#endif
c2882bb1 AF	262	}
c2882bb1 AF	263
94833a42 AF	264
	265	static int __init board_fixups(void)
	266	{
aab0d375	267	char phy_id[20];
94833a42 AF	268	char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
	269	struct device_node *mdio;
	270	struct resource res;
	271	int i;
	272
	273	for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
	274	mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
	275
	276	of_address_to_resource(mdio, 0, &res);
aab0d375	277	snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
24a99596	278	(unsigned long long)res.start, 1);
94833a42 AF	279
	280	phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
	281	phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
	282
	283	/* Register a workaround for errata */
aab0d375	284	snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
24a99596	285	(unsigned long long)res.start, 7);
94833a42 AF	286	phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
	287
	288	of_node_put(mdio);
	289	}
	290
	291	return 0;
	292	}
ea5130dc	293	machine_arch_initcall(mpc8568_mds, board_fixups);
4b3b42b3	294	machine_arch_initcall(mpc8569_mds, board_fixups);
94833a42	295
23f510bc	296	static struct of_device_id mpc85xx_ids[] = {
c2882bb1 AF	297	{ .type = "soc", },
c2882bb1 AF	298	{ .compatible = "soc", },
cf0d19fb	299	{ .compatible = "simple-bus", },
c2882bb1	300	{ .type = "qe", },
a2dd70a1	301	{ .compatible = "fsl,qe", },
84ba4a58	302	{ .compatible = "gianfar", },
fa874618	303	{ .compatible = "fsl,rapidio-delta", },
3cfee0aa	304	{ .compatible = "fsl,mpc8548-guts", },
c2882bb1 AF	305	{},
	306	};
	307
23f510bc	308	static int __init mpc85xx_publish_devices(void)
c2882bb1	309	{
9b9d401b AV	310	if (machine_is(mpc8569_mds))
	311	simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
	312
c2882bb1	313	/* Publish the QE devices */
277982e2	314	of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
c2882bb1 AF	315
	316	return 0;
	317	}
ea5130dc	318	machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
4b3b42b3	319	machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
c2882bb1	320
152d0182 KG	321	machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
	322	machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
	323
23f510bc	324	static void __init mpc85xx_mds_pic_init(void)
c2882bb1 AF	325	{
	326	struct mpic *mpic;
	327	struct resource r;
	328	struct device_node *np = NULL;
	329
	330	np = of_find_node_by_type(NULL, "open-pic");
	331	if (!np)
	332	return;
	333
	334	if (of_address_to_resource(np, 0, &r)) {
	335	printk(KERN_ERR "Failed to map mpic register space\n");
	336	of_node_put(np);
	337	return;
	338	}
	339
	340	mpic = mpic_alloc(np, r.start,
fa644298 AV	341	MPIC_PRIMARY \| MPIC_WANTS_RESET \| MPIC_BIG_ENDIAN \|
fa644298 AV	342	MPIC_BROKEN_FRR_NIRQS,
b533f8ae	343	0, 256, " OpenPIC ");
c2882bb1 AF	344	BUG_ON(mpic == NULL);
	345	of_node_put(np);
	346
c2882bb1 AF	347	mpic_init(mpic);
c2882bb1 AF	348
c2882bb1	349	#ifdef CONFIG_QUICC_ENGINE
a2dd70a1 AV	350	np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
	351	if (!np) {
	352	np = of_find_node_by_type(NULL, "qeic");
	353	if (!np)
	354	return;
	355	}
cccd2102	356	qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
c2882bb1 AF	357	of_node_put(np);
	358	#endif /* CONFIG_QUICC_ENGINE */
	359	}
	360
23f510bc	361	static int __init mpc85xx_mds_probe(void)
c2882bb1	362	{
6936c625	363	unsigned long root = of_get_flat_dt_root();
c2882bb1	364
6936c625	365	return of_flat_dt_is_compatible(root, "MPC85xxMDS");
c2882bb1 AF	366	}
c2882bb1 AF	367
ea5130dc HW	368	define_machine(mpc8568_mds) {
ea5130dc HW	369	.name = "MPC8568 MDS",
23f510bc KG	370	.probe = mpc85xx_mds_probe,
	371	.setup_arch = mpc85xx_mds_setup_arch,
	372	.init_IRQ = mpc85xx_mds_pic_init,
c2882bb1	373	.get_irq = mpic_get_irq,
e1c1575f	374	.restart = fsl_rstcr_restart,
c2882bb1 AF	375	.calibrate_decr = generic_calibrate_decr,
c2882bb1 AF	376	.progress = udbg_progress,
2af8569d	377	#ifdef CONFIG_PCI
aa3c1121	378	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
2af8569d	379	#endif
c2882bb1	380	};
4b3b42b3 HW	381
	382	static int __init mpc8569_mds_probe(void)
	383	{
	384	unsigned long root = of_get_flat_dt_root();
	385
	386	return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
	387	}
	388
	389	define_machine(mpc8569_mds) {
	390	.name = "MPC8569 MDS",
	391	.probe = mpc8569_mds_probe,
	392	.setup_arch = mpc85xx_mds_setup_arch,
	393	.init_IRQ = mpc85xx_mds_pic_init,
	394	.get_irq = mpic_get_irq,
	395	.restart = fsl_rstcr_restart,
	396	.calibrate_decr = generic_calibrate_decr,
	397	.progress = udbg_progress,
	398	#ifdef CONFIG_PCI
	399	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
	400	#endif
	401	};