[net-next-2.6.git] / arch / powerpc / platforms / 85xx / mpc85xx_mds.c

/*
 * Copyright (C) Freescale Semicondutor, Inc. 2006-2010. All rights reserved.
 *
 * Author: Andy Fleming <afleming@freescale.com>
 *
 * Based on 83xx/mpc8360e_pb.c by:
 *	   Li Yang <LeoLi@freescale.com>
 *	   Yin Olivia <Hong-hua.Yin@freescale.com>
 *
 * Description:
 * MPC85xx MDS board specific routines.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/major.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/initrd.h>
#include <linux/module.h>
#include <linux/fsl_devices.h>
#include <linux/of_platform.h>
#include <linux/of_device.h>
#include <linux/phy.h>
#include <linux/memblock.h>

#include <asm/system.h>
#include <asm/atomic.h>
#include <asm/time.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/irq.h>
#include <mm/mmu_decl.h>
#include <asm/prom.h>
#include <asm/udbg.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include <sysdev/simple_gpio.h>
#include <asm/qe.h>
#include <asm/qe_ic.h>
#include <asm/mpic.h>
#include <asm/swiotlb.h>

#undef DEBUG
#ifdef DEBUG
#define DBG(fmt...) udbg_printf(fmt)
#else
#define DBG(fmt...)
#endif

#define MV88E1111_SCR	0x10
#define MV88E1111_SCR_125CLK	0x0010
static int mpc8568_fixup_125_clock(struct phy_device *phydev)
{
	int scr;
	int err;

	/* Workaround for the 125 CLK Toggle */
	scr = phy_read(phydev, MV88E1111_SCR);

	if (scr < 0)
		return scr;

	err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));

	if (err)
		return err;

	err = phy_write(phydev, MII_BMCR, BMCR_RESET);

	if (err)
		return err;

	scr = phy_read(phydev, MV88E1111_SCR);

	if (scr < 0)
		return scr;

	err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);

	return err;
}

static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
{
	int temp;
	int err;

	/* Errata */
	err = phy_write(phydev,29, 0x0006);

	if (err)
		return err;

	temp = phy_read(phydev, 30);

	if (temp < 0)
		return temp;

	temp = (temp & (~0x8000)) | 0x4000;
	err = phy_write(phydev,30, temp);

	if (err)
		return err;

	err = phy_write(phydev,29, 0x000a);

	if (err)
		return err;

	temp = phy_read(phydev, 30);

	if (temp < 0)
		return temp;

	temp = phy_read(phydev, 30);

	if (temp < 0)
		return temp;

	temp &= ~0x0020;

	err = phy_write(phydev,30,temp);

	if (err)
		return err;

	/* Disable automatic MDI/MDIX selection */
	temp = phy_read(phydev, 16);

	if (temp < 0)
		return temp;

	temp &= ~0x0060;
	err = phy_write(phydev,16,temp);

	return err;
}

/* ************************************************************************
 *
 * Setup the architecture
 *
 */
#ifdef CONFIG_SMP
extern void __init mpc85xx_smp_init(void);
#endif

#ifdef CONFIG_QUICC_ENGINE
static struct of_device_id mpc85xx_qe_ids[] __initdata = {
	{ .type = "qe", },
	{ .compatible = "fsl,qe", },
	{ },
};

static void __init mpc85xx_publish_qe_devices(void)
{
	struct device_node *np;

	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
	if (!of_device_is_available(np)) {
		of_node_put(np);
		return;
	}

	of_platform_bus_probe(NULL, mpc85xx_qe_ids, NULL);
}

static void __init mpc85xx_mds_reset_ucc_phys(void)
{
	struct device_node *np;
	static u8 __iomem *bcsr_regs;

	/* Map BCSR area */
	np = of_find_node_by_name(NULL, "bcsr");
	if (!np)
		return;

	bcsr_regs = of_iomap(np, 0);
	of_node_put(np);
	if (!bcsr_regs)
		return;

	if (machine_is(mpc8568_mds)) {
#define BCSR_UCC1_GETH_EN	(0x1 << 7)
#define BCSR_UCC2_GETH_EN	(0x1 << 7)
#define BCSR_UCC1_MODE_MSK	(0x3 << 4)
#define BCSR_UCC2_MODE_MSK	(0x3 << 0)

		/* Turn off UCC1 & UCC2 */
		clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
		clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);

		/* Mode is RGMII, all bits clear */
		clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
					 BCSR_UCC2_MODE_MSK);

		/* Turn UCC1 & UCC2 on */
		setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
		setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
	} else if (machine_is(mpc8569_mds)) {
#define BCSR7_UCC12_GETHnRST	(0x1 << 2)
#define BCSR8_UEM_MARVELL_RST	(0x1 << 1)
#define BCSR_UCC_RGMII		(0x1 << 6)
#define BCSR_UCC_RTBI		(0x1 << 5)
		/*
		 * U-Boot mangles interrupt polarity for Marvell PHYs,
		 * so reset built-in and UEM Marvell PHYs, this puts
		 * the PHYs into their normal state.
		 */
		clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
		setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);

		setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
		clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);

		for (np = NULL; (np = of_find_compatible_node(np,
						"network",
						"ucc_geth")) != NULL;) {
			const unsigned int *prop;
			int ucc_num;

			prop = of_get_property(np, "cell-index", NULL);
			if (prop == NULL)
				continue;

			ucc_num = *prop - 1;

			prop = of_get_property(np, "phy-connection-type", NULL);
			if (prop == NULL)
				continue;

			if (strcmp("rtbi", (const char *)prop) == 0)
				clrsetbits_8(&bcsr_regs[7 + ucc_num],
					BCSR_UCC_RGMII, BCSR_UCC_RTBI);
		}
	} else if (machine_is(p1021_mds)) {
#define BCSR11_ENET_MICRST     (0x1 << 5)
		/* Reset Micrel PHY */
		clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
		setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
	}

	iounmap(bcsr_regs);
}

static void __init mpc85xx_mds_qe_init(void)
{
	struct device_node *np;

	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
	if (!np) {
		np = of_find_node_by_name(NULL, "qe");
		if (!np)
			return;
	}

	if (!of_device_is_available(np)) {
		of_node_put(np);
		return;
	}

	qe_reset();
	of_node_put(np);

	np = of_find_node_by_name(NULL, "par_io");
	if (np) {
		struct device_node *ucc;

		par_io_init(np);
		of_node_put(np);

		for_each_node_by_name(ucc, "ucc")
			par_io_of_config(ucc);
	}

	mpc85xx_mds_reset_ucc_phys();

	if (machine_is(p1021_mds)) {
#define MPC85xx_PMUXCR_OFFSET           0x60
#define MPC85xx_PMUXCR_QE0              0x00008000
#define MPC85xx_PMUXCR_QE3              0x00001000
#define MPC85xx_PMUXCR_QE9              0x00000040
#define MPC85xx_PMUXCR_QE12             0x00000008
		static __be32 __iomem *pmuxcr;

		np = of_find_node_by_name(NULL, "global-utilities");

		if (np) {
			pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;

			if (!pmuxcr)
				printk(KERN_EMERG "Error: Alternate function"
					" signal multiplex control register not"
					" mapped!\n");
			else
			/* P1021 has pins muxed for QE and other functions. To
			 * enable QE UEC mode, we need to set bit QE0 for UCC1
			 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
			 * and QE12 for QE MII management singals in PMUXCR
			 * register.
			 */
				setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
						  MPC85xx_PMUXCR_QE3 |
						  MPC85xx_PMUXCR_QE9 |
						  MPC85xx_PMUXCR_QE12);

			of_node_put(np);
		}

	}
}

static void __init mpc85xx_mds_qeic_init(void)
{
	struct device_node *np;

	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
	if (!of_device_is_available(np)) {
		of_node_put(np);
		return;
	}

	np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
	if (!np) {
		np = of_find_node_by_type(NULL, "qeic");
		if (!np)
			return;
	}

	if (machine_is(p1021_mds))
		qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
				qe_ic_cascade_high_mpic);
	else
		qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
	of_node_put(np);
}
#else
static void __init mpc85xx_publish_qe_devices(void) { }
static void __init mpc85xx_mds_qe_init(void) { }
static void __init mpc85xx_mds_qeic_init(void) { }
#endif	/* CONFIG_QUICC_ENGINE */

static void __init mpc85xx_mds_setup_arch(void)
{
#ifdef CONFIG_PCI
	struct pci_controller *hose;
	struct device_node *np;
#endif
	dma_addr_t max = 0xffffffff;

	if (ppc_md.progress)
		ppc_md.progress("mpc85xx_mds_setup_arch()", 0);

#ifdef CONFIG_PCI
	for_each_node_by_type(np, "pci") {
		if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
		    of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
			struct resource rsrc;
			of_address_to_resource(np, 0, &rsrc);
			if ((rsrc.start & 0xfffff) == 0x8000)
				fsl_add_bridge(np, 1);
			else
				fsl_add_bridge(np, 0);

			hose = pci_find_hose_for_OF_device(np);
			max = min(max, hose->dma_window_base_cur +
					hose->dma_window_size);
		}
	}
#endif

#ifdef CONFIG_SMP
	mpc85xx_smp_init();
#endif

	mpc85xx_mds_qe_init();

#ifdef CONFIG_SWIOTLB
	if (memblock_end_of_DRAM() > max) {
		ppc_swiotlb_enable = 1;
		set_pci_dma_ops(&swiotlb_dma_ops);
		ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
	}
#endif
}


static int __init board_fixups(void)
{
	char phy_id[20];
	char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
	struct device_node *mdio;
	struct resource res;
	int i;

	for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
		mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);

		of_address_to_resource(mdio, 0, &res);
		snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
			(unsigned long long)res.start, 1);

		phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
		phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);

		/* Register a workaround for errata */
		snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
			(unsigned long long)res.start, 7);
		phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);

		of_node_put(mdio);
	}

	return 0;
}
machine_arch_initcall(mpc8568_mds, board_fixups);
machine_arch_initcall(mpc8569_mds, board_fixups);

static struct of_device_id mpc85xx_ids[] = {
	{ .type = "soc", },
	{ .compatible = "soc", },
	{ .compatible = "simple-bus", },
	{ .compatible = "gianfar", },
	{ .compatible = "fsl,rapidio-delta", },
	{ .compatible = "fsl,mpc8548-guts", },
	{ .compatible = "gpio-leds", },
	{},
};

static struct of_device_id p1021_ids[] = {
	{ .type = "soc", },
	{ .compatible = "soc", },
	{ .compatible = "simple-bus", },
	{ .compatible = "gianfar", },
	{},
};

static int __init mpc85xx_publish_devices(void)
{
	if (machine_is(mpc8568_mds))
		simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio");
	if (machine_is(mpc8569_mds))
		simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");

	of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
	mpc85xx_publish_qe_devices();

	return 0;
}

static int __init p1021_publish_devices(void)
{
	of_platform_bus_probe(NULL, p1021_ids, NULL);
	mpc85xx_publish_qe_devices();

	return 0;
}

machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
machine_device_initcall(p1021_mds, p1021_publish_devices);

machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);

static void __init mpc85xx_mds_pic_init(void)
{
	struct mpic *mpic;
	struct resource r;
	struct device_node *np = NULL;

	np = of_find_node_by_type(NULL, "open-pic");
	if (!np)
		return;

	if (of_address_to_resource(np, 0, &r)) {
		printk(KERN_ERR "Failed to map mpic register space\n");
		of_node_put(np);
		return;
	}

	mpic = mpic_alloc(np, r.start,
			MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
			MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
			0, 256, " OpenPIC  ");
	BUG_ON(mpic == NULL);
	of_node_put(np);

	mpic_init(mpic);
	mpc85xx_mds_qeic_init();
}

static int __init mpc85xx_mds_probe(void)
{
        unsigned long root = of_get_flat_dt_root();

        return of_flat_dt_is_compatible(root, "MPC85xxMDS");
}

define_machine(mpc8568_mds) {
	.name		= "MPC8568 MDS",
	.probe		= mpc85xx_mds_probe,
	.setup_arch	= mpc85xx_mds_setup_arch,
	.init_IRQ	= mpc85xx_mds_pic_init,
	.get_irq	= mpic_get_irq,
	.restart	= fsl_rstcr_restart,
	.calibrate_decr	= generic_calibrate_decr,
	.progress	= udbg_progress,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
};

static int __init mpc8569_mds_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
}

define_machine(mpc8569_mds) {
	.name		= "MPC8569 MDS",
	.probe		= mpc8569_mds_probe,
	.setup_arch	= mpc85xx_mds_setup_arch,
	.init_IRQ	= mpc85xx_mds_pic_init,
	.get_irq	= mpic_get_irq,
	.restart	= fsl_rstcr_restart,
	.calibrate_decr	= generic_calibrate_decr,
	.progress	= udbg_progress,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
};

static int __init p1021_mds_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	return of_flat_dt_is_compatible(root, "fsl,P1021MDS");

}

define_machine(p1021_mds) {
	.name		= "P1021 MDS",
	.probe		= p1021_mds_probe,
	.setup_arch	= mpc85xx_mds_setup_arch,
	.init_IRQ	= mpc85xx_mds_pic_init,
	.get_irq	= mpic_get_irq,
	.restart	= fsl_rstcr_restart,
	.calibrate_decr	= generic_calibrate_decr,
	.progress	= udbg_progress,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
};
Commit	Line	Data
c2882bb1	1	/*
48936a08	2	* Copyright (C) Freescale Semicondutor, Inc. 2006-2010. All rights reserved.
c2882bb1 AF	3	*
	4	* Author: Andy Fleming <afleming@freescale.com>
	5	*
	6	* Based on 83xx/mpc8360e_pb.c by:
	7	* Li Yang <LeoLi@freescale.com>
	8	* Yin Olivia <Hong-hua.Yin@freescale.com>
	9	*
	10	* Description:
23f510bc	11	* MPC85xx MDS board specific routines.
c2882bb1 AF	12	*
	13	* This program is free software; you can redistribute it and/or modify it
	14	* under the terms of the GNU General Public License as published by the
	15	* Free Software Foundation; either version 2 of the License, or (at your
	16	* option) any later version.
	17	*/
	18
	19	#include <linux/stddef.h>
	20	#include <linux/kernel.h>
	21	#include <linux/init.h>
	22	#include <linux/errno.h>
	23	#include <linux/reboot.h>
	24	#include <linux/pci.h>
	25	#include <linux/kdev_t.h>
	26	#include <linux/major.h>
	27	#include <linux/console.h>
	28	#include <linux/delay.h>
	29	#include <linux/seq_file.h>
c2882bb1 AF	30	#include <linux/initrd.h>
	31	#include <linux/module.h>
	32	#include <linux/fsl_devices.h>
882407b9 JL	33	#include <linux/of_platform.h>
882407b9 JL	34	#include <linux/of_device.h>
94833a42	35	#include <linux/phy.h>
95f72d1e	36	#include <linux/memblock.h>
c2882bb1	37
c2882bb1 AF	38	#include <asm/system.h>
	39	#include <asm/atomic.h>
	40	#include <asm/time.h>
	41	#include <asm/io.h>
	42	#include <asm/machdep.h>
c2882bb1	43	#include <asm/pci-bridge.h>
c2882bb1 AF	44	#include <asm/irq.h>
	45	#include <mm/mmu_decl.h>
	46	#include <asm/prom.h>
	47	#include <asm/udbg.h>
	48	#include <sysdev/fsl_soc.h>
3f6c5dae	49	#include <sysdev/fsl_pci.h>
9b9d401b	50	#include <sysdev/simple_gpio.h>
c2882bb1 AF	51	#include <asm/qe.h>
	52	#include <asm/qe_ic.h>
	53	#include <asm/mpic.h>
152d0182	54	#include <asm/swiotlb.h>
c2882bb1	55
c2882bb1 AF	56	#undef DEBUG
	57	#ifdef DEBUG
	58	#define DBG(fmt...) udbg_printf(fmt)
	59	#else
	60	#define DBG(fmt...)
	61	#endif
	62
94833a42 AF	63	#define MV88E1111_SCR 0x10
	64	#define MV88E1111_SCR_125CLK 0x0010
	65	static int mpc8568_fixup_125_clock(struct phy_device *phydev)
	66	{
	67	int scr;
	68	int err;
	69
	70	/* Workaround for the 125 CLK Toggle */
	71	scr = phy_read(phydev, MV88E1111_SCR);
	72
	73	if (scr < 0)
	74	return scr;
	75
	76	err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
	77
	78	if (err)
	79	return err;
	80
	81	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	82
	83	if (err)
	84	return err;
	85
	86	scr = phy_read(phydev, MV88E1111_SCR);
	87
	88	if (scr < 0)
29827b02	89	return scr;
94833a42 AF	90
	91	err = phy_write(phydev, MV88E1111_SCR, scr \| 0x0008);
	92
	93	return err;
	94	}
	95
	96	static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
	97	{
	98	int temp;
	99	int err;
	100
	101	/* Errata */
	102	err = phy_write(phydev,29, 0x0006);
	103
	104	if (err)
	105	return err;
	106
	107	temp = phy_read(phydev, 30);
	108
	109	if (temp < 0)
	110	return temp;
	111
	112	temp = (temp & (~0x8000)) \| 0x4000;
	113	err = phy_write(phydev,30, temp);
	114
	115	if (err)
	116	return err;
	117
	118	err = phy_write(phydev,29, 0x000a);
	119
	120	if (err)
	121	return err;
	122
	123	temp = phy_read(phydev, 30);
	124
	125	if (temp < 0)
	126	return temp;
	127
	128	temp = phy_read(phydev, 30);
	129
	130	if (temp < 0)
	131	return temp;
	132
	133	temp &= ~0x0020;
	134
	135	err = phy_write(phydev,30,temp);
	136
	137	if (err)
	138	return err;
	139
	140	/* Disable automatic MDI/MDIX selection */
	141	temp = phy_read(phydev, 16);
	142
	143	if (temp < 0)
	144	return temp;
	145
	146	temp &= ~0x0060;
	147	err = phy_write(phydev,16,temp);
	148
	149	return err;
	150	}
	151
c2882bb1 AF	152	/* ************************************************************************
	153	*
	154	* Setup the architecture
	155	*
	156	*/
48936a08 HW	157	#ifdef CONFIG_SMP
	158	extern void __init mpc85xx_smp_init(void);
	159	#endif
	160
dee9ad71 AV	161	#ifdef CONFIG_QUICC_ENGINE
	162	static struct of_device_id mpc85xx_qe_ids[] __initdata = {
	163	{ .type = "qe", },
	164	{ .compatible = "fsl,qe", },
	165	{ },
	166	};
	167
	168	static void __init mpc85xx_publish_qe_devices(void)
c2882bb1 AF	169	{
c2882bb1 AF	170	struct device_node *np;
c2882bb1	171
dee9ad71 AV	172	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
	173	if (!of_device_is_available(np)) {
	174	of_node_put(np);
	175	return;
	176	}
	177
	178	of_platform_bus_probe(NULL, mpc85xx_qe_ids, NULL);
	179	}
dee9ad71	180
99d8238f	181	static void __init mpc85xx_mds_reset_ucc_phys(void)
c2882bb1 AF	182	{
c2882bb1 AF	183	struct device_node *np;
99d8238f	184	static u8 __iomem *bcsr_regs;
c2882bb1	185
c2882bb1 AF	186	/* Map BCSR area */
c2882bb1 AF	187	np = of_find_node_by_name(NULL, "bcsr");
99d8238f AV	188	if (!np)
99d8238f AV	189	return;
c2882bb1	190
99d8238f AV	191	bcsr_regs = of_iomap(np, 0);
	192	of_node_put(np);
	193	if (!bcsr_regs)
	194	return;
c2882bb1	195
99d8238f AV	196	if (machine_is(mpc8568_mds)) {
	197	#define BCSR_UCC1_GETH_EN (0x1 << 7)
	198	#define BCSR_UCC2_GETH_EN (0x1 << 7)
	199	#define BCSR_UCC1_MODE_MSK (0x3 << 4)
	200	#define BCSR_UCC2_MODE_MSK (0x3 << 0)
152d0182	201
99d8238f AV	202	/* Turn off UCC1 & UCC2 */
	203	clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
	204	clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
	205
	206	/* Mode is RGMII, all bits clear */
	207	clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK \|
	208	BCSR_UCC2_MODE_MSK);
	209
	210	/* Turn UCC1 & UCC2 on */
	211	setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
	212	setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
	213	} else if (machine_is(mpc8569_mds)) {
	214	#define BCSR7_UCC12_GETHnRST (0x1 << 2)
	215	#define BCSR8_UEM_MARVELL_RST (0x1 << 1)
	216	#define BCSR_UCC_RGMII (0x1 << 6)
	217	#define BCSR_UCC_RTBI (0x1 << 5)
	218	/*
	219	* U-Boot mangles interrupt polarity for Marvell PHYs,
	220	* so reset built-in and UEM Marvell PHYs, this puts
	221	* the PHYs into their normal state.
	222	*/
	223	clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
	224	setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
	225
	226	setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
	227	clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
	228
	229	for (np = NULL; (np = of_find_compatible_node(np,
	230	"network",
	231	"ucc_geth")) != NULL;) {
	232	const unsigned int *prop;
	233	int ucc_num;
	234
	235	prop = of_get_property(np, "cell-index", NULL);
	236	if (prop == NULL)
	237	continue;
	238
	239	ucc_num = *prop - 1;
	240
	241	prop = of_get_property(np, "phy-connection-type", NULL);
	242	if (prop == NULL)
	243	continue;
	244
	245	if (strcmp("rtbi", (const char *)prop) == 0)
	246	clrsetbits_8(&bcsr_regs[7 + ucc_num],
	247	BCSR_UCC_RGMII, BCSR_UCC_RTBI);
c9438aff	248	}
99d8238f AV	249	} else if (machine_is(p1021_mds)) {
	250	#define BCSR11_ENET_MICRST (0x1 << 5)
	251	/* Reset Micrel PHY */
	252	clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
	253	setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
c9438aff	254	}
c2882bb1	255
99d8238f AV	256	iounmap(bcsr_regs);
99d8238f AV	257	}
48936a08	258
99d8238f AV	259	static void __init mpc85xx_mds_qe_init(void)
	260	{
	261	struct device_node *np;
48936a08	262
a2dd70a1 AV	263	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
	264	if (!np) {
	265	np = of_find_node_by_name(NULL, "qe");
	266	if (!np)
	267	return;
c2882bb1 AF	268	}
c2882bb1 AF	269
dee9ad71 AV	270	if (!of_device_is_available(np)) {
	271	of_node_put(np);
	272	return;
	273	}
	274
a2dd70a1 AV	275	qe_reset();
	276	of_node_put(np);
	277
	278	np = of_find_node_by_name(NULL, "par_io");
	279	if (np) {
	280	struct device_node *ucc;
c2882bb1 AF	281
	282	par_io_init(np);
	283	of_node_put(np);
	284
a2dd70a1	285	for_each_node_by_name(ucc, "ucc")
c2882bb1	286	par_io_of_config(ucc);
c2882bb1 AF	287	}
c2882bb1 AF	288
99d8238f	289	mpc85xx_mds_reset_ucc_phys();
48936a08 HW	290
	291	if (machine_is(p1021_mds)) {
	292	#define MPC85xx_PMUXCR_OFFSET 0x60
	293	#define MPC85xx_PMUXCR_QE0 0x00008000
	294	#define MPC85xx_PMUXCR_QE3 0x00001000
	295	#define MPC85xx_PMUXCR_QE9 0x00000040
	296	#define MPC85xx_PMUXCR_QE12 0x00000008
	297	static __be32 __iomem *pmuxcr;
	298
	299	np = of_find_node_by_name(NULL, "global-utilities");
	300
	301	if (np) {
	302	pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
	303
	304	if (!pmuxcr)
	305	printk(KERN_EMERG "Error: Alternate function"
	306	" signal multiplex control register not"
	307	" mapped!\n");
	308	else
	309	/* P1021 has pins muxed for QE and other functions. To
	310	* enable QE UEC mode, we need to set bit QE0 for UCC1
	311	* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
	312	* and QE12 for QE MII management singals in PMUXCR
	313	* register.
	314	*/
	315	setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 \|
	316	MPC85xx_PMUXCR_QE3 \|
	317	MPC85xx_PMUXCR_QE9 \|
	318	MPC85xx_PMUXCR_QE12);
	319
	320	of_node_put(np);
	321	}
	322
	323	}
99d8238f AV	324	}
	325
	326	static void __init mpc85xx_mds_qeic_init(void)
	327	{
	328	struct device_node *np;
	329
	330	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
	331	if (!of_device_is_available(np)) {
	332	of_node_put(np);
	333	return;
	334	}
	335
	336	np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
	337	if (!np) {
	338	np = of_find_node_by_type(NULL, "qeic");
	339	if (!np)
	340	return;
	341	}
	342
	343	if (machine_is(p1021_mds))
	344	qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
	345	qe_ic_cascade_high_mpic);
	346	else
	347	qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
	348	of_node_put(np);
	349	}
	350	#else
	351	static void __init mpc85xx_publish_qe_devices(void) { }
	352	static void __init mpc85xx_mds_qe_init(void) { }
	353	static void __init mpc85xx_mds_qeic_init(void) { }
c2882bb1	354	#endif /* CONFIG_QUICC_ENGINE */
152d0182	355
99d8238f AV	356	static void __init mpc85xx_mds_setup_arch(void)
	357	{
	358	#ifdef CONFIG_PCI
	359	struct pci_controller *hose;
6d4f2fb0	360	struct device_node *np;
99d8238f AV	361	#endif
	362	dma_addr_t max = 0xffffffff;
	363
	364	if (ppc_md.progress)
	365	ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
	366
	367	#ifdef CONFIG_PCI
	368	for_each_node_by_type(np, "pci") {
	369	if (of_device_is_compatible(np, "fsl,mpc8540-pci") \|\|
	370	of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
	371	struct resource rsrc;
	372	of_address_to_resource(np, 0, &rsrc);
	373	if ((rsrc.start & 0xfffff) == 0x8000)
	374	fsl_add_bridge(np, 1);
	375	else
	376	fsl_add_bridge(np, 0);
	377
	378	hose = pci_find_hose_for_OF_device(np);
	379	max = min(max, hose->dma_window_base_cur +
	380	hose->dma_window_size);
	381	}
	382	}
	383	#endif
	384
	385	#ifdef CONFIG_SMP
	386	mpc85xx_smp_init();
	387	#endif
	388
	389	mpc85xx_mds_qe_init();
	390
152d0182	391	#ifdef CONFIG_SWIOTLB
95f72d1e	392	if (memblock_end_of_DRAM() > max) {
152d0182	393	ppc_swiotlb_enable = 1;
3702977f	394	set_pci_dma_ops(&swiotlb_dma_ops);
762afb73	395	ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
152d0182 KG	396	}
152d0182 KG	397	#endif
c2882bb1 AF	398	}
c2882bb1 AF	399
94833a42 AF	400
	401	static int __init board_fixups(void)
	402	{
aab0d375	403	char phy_id[20];
94833a42 AF	404	char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
	405	struct device_node *mdio;
	406	struct resource res;
	407	int i;
	408
	409	for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
	410	mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
	411
	412	of_address_to_resource(mdio, 0, &res);
aab0d375	413	snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
24a99596	414	(unsigned long long)res.start, 1);
94833a42 AF	415
	416	phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
	417	phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
	418
	419	/* Register a workaround for errata */
aab0d375	420	snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
24a99596	421	(unsigned long long)res.start, 7);
94833a42 AF	422	phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
	423
	424	of_node_put(mdio);
	425	}
	426
	427	return 0;
	428	}
ea5130dc	429	machine_arch_initcall(mpc8568_mds, board_fixups);
4b3b42b3	430	machine_arch_initcall(mpc8569_mds, board_fixups);
94833a42	431
23f510bc	432	static struct of_device_id mpc85xx_ids[] = {
c2882bb1 AF	433	{ .type = "soc", },
c2882bb1 AF	434	{ .compatible = "soc", },
cf0d19fb	435	{ .compatible = "simple-bus", },
84ba4a58	436	{ .compatible = "gianfar", },
fa874618	437	{ .compatible = "fsl,rapidio-delta", },
3cfee0aa	438	{ .compatible = "fsl,mpc8548-guts", },
e98efaf3	439	{ .compatible = "gpio-leds", },
c2882bb1 AF	440	{},
	441	};
	442
48936a08 HW	443	static struct of_device_id p1021_ids[] = {
	444	{ .type = "soc", },
	445	{ .compatible = "soc", },
	446	{ .compatible = "simple-bus", },
48936a08 HW	447	{ .compatible = "gianfar", },
	448	{},
	449	};
	450
23f510bc	451	static int __init mpc85xx_publish_devices(void)
c2882bb1	452	{
e98efaf3 AV	453	if (machine_is(mpc8568_mds))
e98efaf3 AV	454	simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio");
9b9d401b AV	455	if (machine_is(mpc8569_mds))
	456	simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
	457
277982e2	458	of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
dee9ad71	459	mpc85xx_publish_qe_devices();
c2882bb1 AF	460
	461	return 0;
	462	}
48936a08 HW	463
	464	static int __init p1021_publish_devices(void)
	465	{
48936a08	466	of_platform_bus_probe(NULL, p1021_ids, NULL);
dee9ad71	467	mpc85xx_publish_qe_devices();
48936a08 HW	468
	469	return 0;
	470	}
	471
ea5130dc	472	machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
4b3b42b3	473	machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
48936a08	474	machine_device_initcall(p1021_mds, p1021_publish_devices);
c2882bb1	475
152d0182 KG	476	machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
152d0182 KG	477	machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
48936a08	478	machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);
152d0182	479
23f510bc	480	static void __init mpc85xx_mds_pic_init(void)
c2882bb1 AF	481	{
	482	struct mpic *mpic;
	483	struct resource r;
	484	struct device_node *np = NULL;
	485
	486	np = of_find_node_by_type(NULL, "open-pic");
	487	if (!np)
	488	return;
	489
	490	if (of_address_to_resource(np, 0, &r)) {
	491	printk(KERN_ERR "Failed to map mpic register space\n");
	492	of_node_put(np);
	493	return;
	494	}
	495
	496	mpic = mpic_alloc(np, r.start,
fa644298	497	MPIC_PRIMARY \| MPIC_WANTS_RESET \| MPIC_BIG_ENDIAN \|
48936a08	498	MPIC_BROKEN_FRR_NIRQS \| MPIC_SINGLE_DEST_CPU,
b533f8ae	499	0, 256, " OpenPIC ");
c2882bb1 AF	500	BUG_ON(mpic == NULL);
	501	of_node_put(np);
	502
c2882bb1	503	mpic_init(mpic);
99d8238f	504	mpc85xx_mds_qeic_init();
c2882bb1 AF	505	}
c2882bb1 AF	506
23f510bc	507	static int __init mpc85xx_mds_probe(void)
c2882bb1	508	{
6936c625	509	unsigned long root = of_get_flat_dt_root();
c2882bb1	510
6936c625	511	return of_flat_dt_is_compatible(root, "MPC85xxMDS");
c2882bb1 AF	512	}
c2882bb1 AF	513
ea5130dc HW	514	define_machine(mpc8568_mds) {
ea5130dc HW	515	.name = "MPC8568 MDS",
23f510bc KG	516	.probe = mpc85xx_mds_probe,
	517	.setup_arch = mpc85xx_mds_setup_arch,
	518	.init_IRQ = mpc85xx_mds_pic_init,
c2882bb1	519	.get_irq = mpic_get_irq,
e1c1575f	520	.restart = fsl_rstcr_restart,
c2882bb1 AF	521	.calibrate_decr = generic_calibrate_decr,
c2882bb1 AF	522	.progress = udbg_progress,
2af8569d	523	#ifdef CONFIG_PCI
aa3c1121	524	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
2af8569d	525	#endif
c2882bb1	526	};
4b3b42b3 HW	527
	528	static int __init mpc8569_mds_probe(void)
	529	{
	530	unsigned long root = of_get_flat_dt_root();
	531
	532	return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
	533	}
	534
	535	define_machine(mpc8569_mds) {
	536	.name = "MPC8569 MDS",
	537	.probe = mpc8569_mds_probe,
	538	.setup_arch = mpc85xx_mds_setup_arch,
	539	.init_IRQ = mpc85xx_mds_pic_init,
	540	.get_irq = mpic_get_irq,
	541	.restart = fsl_rstcr_restart,
	542	.calibrate_decr = generic_calibrate_decr,
	543	.progress = udbg_progress,
	544	#ifdef CONFIG_PCI
	545	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
	546	#endif
	547	};
48936a08 HW	548
	549	static int __init p1021_mds_probe(void)
	550	{
	551	unsigned long root = of_get_flat_dt_root();
	552
	553	return of_flat_dt_is_compatible(root, "fsl,P1021MDS");
	554
	555	}
	556
	557	define_machine(p1021_mds) {
	558	.name = "P1021 MDS",
	559	.probe = p1021_mds_probe,
	560	.setup_arch = mpc85xx_mds_setup_arch,
	561	.init_IRQ = mpc85xx_mds_pic_init,
	562	.get_irq = mpic_get_irq,
	563	.restart = fsl_rstcr_restart,
	564	.calibrate_decr = generic_calibrate_decr,
	565	.progress = udbg_progress,
	566	#ifdef CONFIG_PCI
	567	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
	568	#endif
	569	};
	570