[net-next-2.6.git] / arch / powerpc / platforms / 52xx / mpc52xx_common.c

/*
 *
 * Utility functions for the Freescale MPC52xx.
 *
 * Copyright (C) 2006 Sylvain Munaut <tnt@246tNt.com>
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 *
 */

#undef DEBUG

#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/of_platform.h>
#include <linux/of_gpio.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/mpc52xx.h>

/* MPC5200 device tree match tables */
static struct of_device_id mpc52xx_xlb_ids[] __initdata = {
	{ .compatible = "fsl,mpc5200-xlb", },
	{ .compatible = "mpc5200-xlb", },
	{}
};
static struct of_device_id mpc52xx_bus_ids[] __initdata = {
	{ .compatible = "fsl,mpc5200-immr", },
	{ .compatible = "fsl,mpc5200b-immr", },
	{ .compatible = "simple-bus", },

	/* depreciated matches; shouldn't be used in new device trees */
	{ .compatible = "fsl,lpb", },
	{ .type = "builtin", .compatible = "mpc5200", }, /* efika */
	{ .type = "soc", .compatible = "mpc5200", }, /* lite5200 */
	{}
};

/*
 * This variable is mapped in mpc52xx_map_wdt() and used in mpc52xx_restart().
 * Permanent mapping is required because mpc52xx_restart() can be called
 * from interrupt context while node mapping (which calls ioremap())
 * cannot be used at such point.
 */
static DEFINE_SPINLOCK(mpc52xx_lock);
static struct mpc52xx_gpt __iomem *mpc52xx_wdt;
static struct mpc52xx_cdm __iomem *mpc52xx_cdm;

/*
 * Configure the XLB arbiter settings to match what Linux expects.
 */
void __init
mpc5200_setup_xlb_arbiter(void)
{
	struct device_node *np;
	struct mpc52xx_xlb  __iomem *xlb;

	np = of_find_matching_node(NULL, mpc52xx_xlb_ids);
	xlb = of_iomap(np, 0);
	of_node_put(np);
	if (!xlb) {
		printk(KERN_ERR __FILE__ ": "
			"Error mapping XLB in mpc52xx_setup_cpu(). "
			"Expect some abnormal behavior\n");
		return;
	}

	/* Configure the XLB Arbiter priorities */
	out_be32(&xlb->master_pri_enable, 0xff);
	out_be32(&xlb->master_priority, 0x11111111);

	/*
	 * Disable XLB pipelining
	 * (cfr errate 292. We could do this only just before ATA PIO
	 *  transaction and re-enable it afterwards ...)
	 * Not needed on MPC5200B.
	 */
	if ((mfspr(SPRN_SVR) & MPC5200_SVR_MASK) == MPC5200_SVR)
		out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_PLDIS);

	iounmap(xlb);
}

/*
 * This variable is mapped in mpc52xx_map_common_devices and
 * used in mpc5200_psc_ac97_gpio_reset().
 */
static DEFINE_SPINLOCK(gpio_lock);
struct mpc52xx_gpio __iomem *simple_gpio;
struct mpc52xx_gpio_wkup __iomem *wkup_gpio;

/**
 * mpc52xx_declare_of_platform_devices: register internal devices and children
 *					of the localplus bus to the of_platform
 *					bus.
 */
void __init
mpc52xx_declare_of_platform_devices(void)
{
	/* Find every child of the SOC node and add it to of_platform */
	if (of_platform_bus_probe(NULL, mpc52xx_bus_ids, NULL))
		printk(KERN_ERR __FILE__ ": "
			"Error while probing of_platform bus\n");
}

/*
 * match tables used by mpc52xx_map_common_devices()
 */
static struct of_device_id mpc52xx_gpt_ids[] __initdata = {
	{ .compatible = "fsl,mpc5200-gpt", },
	{ .compatible = "mpc5200-gpt", }, /* old */
	{}
};
static struct of_device_id mpc52xx_cdm_ids[] __initdata = {
	{ .compatible = "fsl,mpc5200-cdm", },
	{ .compatible = "mpc5200-cdm", }, /* old */
	{}
};
static const struct of_device_id mpc52xx_gpio_simple[] = {
	{ .compatible = "fsl,mpc5200-gpio", },
	{}
};
static const struct of_device_id mpc52xx_gpio_wkup[] = {
	{ .compatible = "fsl,mpc5200-gpio-wkup", },
	{}
};


/**
 * mpc52xx_map_common_devices: iomap devices required by common code
 */
void __init
mpc52xx_map_common_devices(void)
{
	struct device_node *np;

	/* mpc52xx_wdt is mapped here and used in mpc52xx_restart,
	 * possibly from a interrupt context. wdt is only implement
	 * on a gpt0, so check has-wdt property before mapping.
	 */
	for_each_matching_node(np, mpc52xx_gpt_ids) {
		if (of_get_property(np, "fsl,has-wdt", NULL) ||
		    of_get_property(np, "has-wdt", NULL)) {
			mpc52xx_wdt = of_iomap(np, 0);
			of_node_put(np);
			break;
		}
	}

	/* Clock Distribution Module, used by PSC clock setting function */
	np = of_find_matching_node(NULL, mpc52xx_cdm_ids);
	mpc52xx_cdm = of_iomap(np, 0);
	of_node_put(np);

	/* simple_gpio registers */
	np = of_find_matching_node(NULL, mpc52xx_gpio_simple);
	simple_gpio = of_iomap(np, 0);
	of_node_put(np);

	/* wkup_gpio registers */
	np = of_find_matching_node(NULL, mpc52xx_gpio_wkup);
	wkup_gpio = of_iomap(np, 0);
	of_node_put(np);
}

/**
 * mpc52xx_set_psc_clkdiv: Set clock divider in the CDM for PSC ports
 *
 * @psc_id: id of psc port; must be 1,2,3 or 6
 * @clkdiv: clock divider value to put into CDM PSC register.
 */
int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv)
{
	unsigned long flags;
	u16 __iomem *reg;
	u32 val;
	u32 mask;
	u32 mclken_div;

	if (!mpc52xx_cdm)
		return -ENODEV;

	mclken_div = 0x8000 | (clkdiv & 0x1FF);
	switch (psc_id) {
	case 1: reg = &mpc52xx_cdm->mclken_div_psc1; mask = 0x20; break;
	case 2: reg = &mpc52xx_cdm->mclken_div_psc2; mask = 0x40; break;
	case 3: reg = &mpc52xx_cdm->mclken_div_psc3; mask = 0x80; break;
	case 6: reg = &mpc52xx_cdm->mclken_div_psc6; mask = 0x10; break;
	default:
		return -ENODEV;
	}

	/* Set the rate and enable the clock */
	spin_lock_irqsave(&mpc52xx_lock, flags);
	out_be16(reg, mclken_div);
	val = in_be32(&mpc52xx_cdm->clk_enables);
	out_be32(&mpc52xx_cdm->clk_enables, val | mask);
	spin_unlock_irqrestore(&mpc52xx_lock, flags);

	return 0;
}
EXPORT_SYMBOL(mpc52xx_set_psc_clkdiv);

/**
 * mpc52xx_get_xtal_freq - Get SYS_XTAL_IN frequency for a device
 *
 * @node: device node
 *
 * Returns the frequency of the external oscillator clock connected
 * to the SYS_XTAL_IN pin, or 0 if it cannot be determined.
 */
unsigned int mpc52xx_get_xtal_freq(struct device_node *node)
{
	u32 val;
	unsigned int freq;

	if (!mpc52xx_cdm)
		return 0;

	freq = mpc5xxx_get_bus_frequency(node);
	if (!freq)
		return 0;

	if (in_8(&mpc52xx_cdm->ipb_clk_sel) & 0x1)
		freq *= 2;

	val  = in_be32(&mpc52xx_cdm->rstcfg);
	if (val & (1 << 5))
		freq *= 8;
	else
		freq *= 4;
	if (val & (1 << 6))
		freq /= 12;
	else
		freq /= 16;

	return freq;
}
EXPORT_SYMBOL(mpc52xx_get_xtal_freq);

/**
 * mpc52xx_restart: ppc_md->restart hook for mpc5200 using the watchdog timer
 */
void
mpc52xx_restart(char *cmd)
{
	local_irq_disable();

	/* Turn on the watchdog and wait for it to expire.
	 * It effectively does a reset. */
	if (mpc52xx_wdt) {
		out_be32(&mpc52xx_wdt->mode, 0x00000000);
		out_be32(&mpc52xx_wdt->count, 0x000000ff);
		out_be32(&mpc52xx_wdt->mode, 0x00009004);
	} else
		printk(KERN_ERR __FILE__ ": "
			"mpc52xx_restart: Can't access wdt. "
			"Restart impossible, system halted.\n");

	while (1);
}

#define PSC1_RESET     0x1
#define PSC1_SYNC      0x4
#define PSC1_SDATA_OUT 0x1
#define PSC2_RESET     0x2
#define PSC2_SYNC      (0x4<<4)
#define PSC2_SDATA_OUT (0x1<<4)
#define MPC52xx_GPIO_PSC1_MASK 0x7
#define MPC52xx_GPIO_PSC2_MASK (0x7<<4)

/**
 * mpc5200_psc_ac97_gpio_reset: Use gpio pins to reset the ac97 bus
 *
 * @psc: psc number to reset (only psc 1 and 2 support ac97)
 */
int mpc5200_psc_ac97_gpio_reset(int psc_number)
{
	unsigned long flags;
	u32 gpio;
	u32 mux;
	int out;
	int reset;
	int sync;

	if ((!simple_gpio) || (!wkup_gpio))
		return -ENODEV;

	switch (psc_number) {
	case 0:
		reset   = PSC1_RESET;           /* AC97_1_RES */
		sync    = PSC1_SYNC;            /* AC97_1_SYNC */
		out     = PSC1_SDATA_OUT;       /* AC97_1_SDATA_OUT */
		gpio    = MPC52xx_GPIO_PSC1_MASK;
		break;
	case 1:
		reset   = PSC2_RESET;           /* AC97_2_RES */
		sync    = PSC2_SYNC;            /* AC97_2_SYNC */
		out     = PSC2_SDATA_OUT;       /* AC97_2_SDATA_OUT */
		gpio    = MPC52xx_GPIO_PSC2_MASK;
		break;
	default:
		pr_err(__FILE__ ": Unable to determine PSC, no ac97 "
		       "cold-reset will be performed\n");
		return -ENODEV;
	}

	spin_lock_irqsave(&gpio_lock, flags);

	/* Reconfiure pin-muxing to gpio */
	mux = in_be32(&simple_gpio->port_config);
	out_be32(&simple_gpio->port_config, mux & (~gpio));

	/* enable gpio pins for output */
	setbits8(&wkup_gpio->wkup_gpioe, reset);
	setbits32(&simple_gpio->simple_gpioe, sync | out);

	setbits8(&wkup_gpio->wkup_ddr, reset);
	setbits32(&simple_gpio->simple_ddr, sync | out);

	/* Assert cold reset */
	clrbits32(&simple_gpio->simple_dvo, sync | out);
	clrbits8(&wkup_gpio->wkup_dvo, reset);

	/* wait for 1 us */
	udelay(1);

	/* Deassert reset */
	setbits8(&wkup_gpio->wkup_dvo, reset);

	/* wait at least 200ns */
	/* 7 ~= (200ns * timebase) / ns2sec */
	__delay(7);

	/* Restore pin-muxing */
	out_be32(&simple_gpio->port_config, mux);

	spin_unlock_irqrestore(&gpio_lock, flags);

	return 0;
}
EXPORT_SYMBOL(mpc5200_psc_ac97_gpio_reset);
Commit	Line	Data
6065170c GL	1	/*
	2	*
	3	* Utility functions for the Freescale MPC52xx.
	4	*
	5	* Copyright (C) 2006 Sylvain Munaut <tnt@246tNt.com>
	6	*
	7	* This file is licensed under the terms of the GNU General Public License
	8	* version 2. This program is licensed "as is" without any warranty of any
	9	* kind, whether express or implied.
	10	*
	11	*/
	12
	13	#undef DEBUG
	14
cfa6a88c	15	#include <linux/gpio.h>
6065170c	16	#include <linux/kernel.h>
c8004a28	17	#include <linux/spinlock.h>
9fe2e796	18	#include <linux/of_platform.h>
cfa6a88c	19	#include <linux/of_gpio.h>
6065170c GL	20	#include <asm/io.h>
6065170c GL	21	#include <asm/prom.h>
6065170c GL	22	#include <asm/mpc52xx.h>
6065170c GL	23
66ffbe49 GL	24	/* MPC5200 device tree match tables */
	25	static struct of_device_id mpc52xx_xlb_ids[] __initdata = {
	26	{ .compatible = "fsl,mpc5200-xlb", },
	27	{ .compatible = "mpc5200-xlb", },
	28	{}
	29	};
	30	static struct of_device_id mpc52xx_bus_ids[] __initdata = {
	31	{ .compatible = "fsl,mpc5200-immr", },
	32	{ .compatible = "fsl,mpc5200b-immr", },
aafbf16b	33	{ .compatible = "simple-bus", },
66ffbe49 GL	34
66ffbe49 GL	35	/* depreciated matches; shouldn't be used in new device trees */
aafbf16b	36	{ .compatible = "fsl,lpb", },
66ffbe49 GL	37	{ .type = "builtin", .compatible = "mpc5200", }, /* efika */
	38	{ .type = "soc", .compatible = "mpc5200", }, /* lite5200 */
	39	{}
	40	};
	41
86b92cdd MB	42	/*
	43	* This variable is mapped in mpc52xx_map_wdt() and used in mpc52xx_restart().
	44	* Permanent mapping is required because mpc52xx_restart() can be called
	45	* from interrupt context while node mapping (which calls ioremap())
	46	* cannot be used at such point.
	47	*/
2701a1ad	48	static DEFINE_SPINLOCK(mpc52xx_lock);
c8004a28 GL	49	static struct mpc52xx_gpt __iomem *mpc52xx_wdt;
c8004a28 GL	50	static struct mpc52xx_cdm __iomem *mpc52xx_cdm;
6065170c	51
4de3b992 GL	52	/*
	53	* Configure the XLB arbiter settings to match what Linux expects.
	54	*/
6065170c	55	void __init
4de3b992	56	mpc5200_setup_xlb_arbiter(void)
6065170c	57	{
75ca399e	58	struct device_node *np;
6065170c GL	59	struct mpc52xx_xlb __iomem *xlb;
6065170c GL	60
66ffbe49	61	np = of_find_matching_node(NULL, mpc52xx_xlb_ids);
75ca399e GL	62	xlb = of_iomap(np, 0);
75ca399e GL	63	of_node_put(np);
4de3b992	64	if (!xlb) {
6065170c	65	printk(KERN_ERR __FILE__ ": "
f43c32ef	66	"Error mapping XLB in mpc52xx_setup_cpu(). "
6065170c	67	"Expect some abnormal behavior\n");
4de3b992	68	return;
6065170c GL	69	}
6065170c GL	70
6065170c GL	71	/* Configure the XLB Arbiter priorities */
	72	out_be32(&xlb->master_pri_enable, 0xff);
	73	out_be32(&xlb->master_priority, 0x11111111);
	74
96290957 WS	75	/*
96290957 WS	76	* Disable XLB pipelining
4de3b992 GL	77	* (cfr errate 292. We could do this only just before ATA PIO
4de3b992 GL	78	* transaction and re-enable it afterwards ...)
96290957	79	* Not needed on MPC5200B.
4de3b992	80	*/
96290957 WS	81	if ((mfspr(SPRN_SVR) & MPC5200_SVR_MASK) == MPC5200_SVR)
96290957 WS	82	out_be32(&xlb->config, in_be32(&xlb->config) \| MPC52xx_XLB_CFG_PLDIS);
6065170c	83
4de3b992	84	iounmap(xlb);
6065170c GL	85	}
6065170c GL	86
cfa6a88c EM	87	/*
	88	* This variable is mapped in mpc52xx_map_common_devices and
	89	* used in mpc5200_psc_ac97_gpio_reset().
	90	*/
	91	static DEFINE_SPINLOCK(gpio_lock);
	92	struct mpc52xx_gpio __iomem *simple_gpio;
	93	struct mpc52xx_gpio_wkup __iomem *wkup_gpio;
	94
66ffbe49 GL	95	/**
	96	* mpc52xx_declare_of_platform_devices: register internal devices and children
	97	* of the localplus bus to the of_platform
	98	* bus.
	99	*/
5c334eed	100	void __init
6065170c GL	101	mpc52xx_declare_of_platform_devices(void)
	102	{
	103	/* Find every child of the SOC node and add it to of_platform */
a6f024bb	104	if (of_platform_bus_probe(NULL, mpc52xx_bus_ids, NULL))
5c334eed SM	105	printk(KERN_ERR __FILE__ ": "
5c334eed SM	106	"Error while probing of_platform bus\n");
6065170c GL	107	}
6065170c GL	108
66ffbe49	109	/*
c8004a28	110	* match tables used by mpc52xx_map_common_devices()
66ffbe49 GL	111	*/
	112	static struct of_device_id mpc52xx_gpt_ids[] __initdata = {
	113	{ .compatible = "fsl,mpc5200-gpt", },
	114	{ .compatible = "mpc5200-gpt", }, /* old */
	115	{}
	116	};
c8004a28 GL	117	static struct of_device_id mpc52xx_cdm_ids[] __initdata = {
	118	{ .compatible = "fsl,mpc5200-cdm", },
	119	{ .compatible = "mpc5200-cdm", }, /* old */
	120	{}
	121	};
cfa6a88c EM	122	static const struct of_device_id mpc52xx_gpio_simple[] = {
	123	{ .compatible = "fsl,mpc5200-gpio", },
	124	{}
	125	};
	126	static const struct of_device_id mpc52xx_gpio_wkup[] = {
	127	{ .compatible = "fsl,mpc5200-gpio-wkup", },
	128	{}
	129	};
	130
66ffbe49	131
c8004a28 GL	132	/**
	133	* mpc52xx_map_common_devices: iomap devices required by common code
	134	*/
86b92cdd	135	void __init
c8004a28	136	mpc52xx_map_common_devices(void)
86b92cdd	137	{
86b92cdd	138	struct device_node *np;
c8004a28	139
86b92cdd MB	140	/* mpc52xx_wdt is mapped here and used in mpc52xx_restart,
	141	* possibly from a interrupt context. wdt is only implement
	142	* on a gpt0, so check has-wdt property before mapping.
	143	*/
66ffbe49 GL	144	for_each_matching_node(np, mpc52xx_gpt_ids) {
	145	if (of_get_property(np, "fsl,has-wdt", NULL) \|\|
	146	of_get_property(np, "has-wdt", NULL)) {
75ca399e GL	147	mpc52xx_wdt = of_iomap(np, 0);
75ca399e GL	148	of_node_put(np);
c8004a28	149	break;
86b92cdd MB	150	}
86b92cdd MB	151	}
c8004a28 GL	152
	153	/* Clock Distribution Module, used by PSC clock setting function */
	154	np = of_find_matching_node(NULL, mpc52xx_cdm_ids);
	155	mpc52xx_cdm = of_iomap(np, 0);
	156	of_node_put(np);
cfa6a88c EM	157
	158	/* simple_gpio registers */
	159	np = of_find_matching_node(NULL, mpc52xx_gpio_simple);
	160	simple_gpio = of_iomap(np, 0);
	161	of_node_put(np);
	162
	163	/* wkup_gpio registers */
	164	np = of_find_matching_node(NULL, mpc52xx_gpio_wkup);
	165	wkup_gpio = of_iomap(np, 0);
	166	of_node_put(np);
86b92cdd MB	167	}
86b92cdd MB	168
c8004a28 GL	169	/**
	170	* mpc52xx_set_psc_clkdiv: Set clock divider in the CDM for PSC ports
	171	*
	172	* @psc_id: id of psc port; must be 1,2,3 or 6
	173	* @clkdiv: clock divider value to put into CDM PSC register.
	174	*/
	175	int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv)
	176	{
	177	unsigned long flags;
	178	u16 __iomem *reg;
	179	u32 val;
	180	u32 mask;
	181	u32 mclken_div;
	182
	183	if (!mpc52xx_cdm)
	184	return -ENODEV;
	185
	186	mclken_div = 0x8000 \| (clkdiv & 0x1FF);
	187	switch (psc_id) {
	188	case 1: reg = &mpc52xx_cdm->mclken_div_psc1; mask = 0x20; break;
	189	case 2: reg = &mpc52xx_cdm->mclken_div_psc2; mask = 0x40; break;
	190	case 3: reg = &mpc52xx_cdm->mclken_div_psc3; mask = 0x80; break;
	191	case 6: reg = &mpc52xx_cdm->mclken_div_psc6; mask = 0x10; break;
	192	default:
	193	return -ENODEV;
	194	}
	195
	196	/* Set the rate and enable the clock */
	197	spin_lock_irqsave(&mpc52xx_lock, flags);
	198	out_be16(reg, mclken_div);
	199	val = in_be32(&mpc52xx_cdm->clk_enables);
	200	out_be32(&mpc52xx_cdm->clk_enables, val \| mask);
	201	spin_unlock_irqrestore(&mpc52xx_lock, flags);
	202
	203	return 0;
	204	}
4187377b	205	EXPORT_SYMBOL(mpc52xx_set_psc_clkdiv);
c8004a28	206
df8a95f4 WG	207	/**
	208	* mpc52xx_get_xtal_freq - Get SYS_XTAL_IN frequency for a device
	209	*
	210	* @node: device node
	211	*
	212	* Returns the frequency of the external oscillator clock connected
	213	* to the SYS_XTAL_IN pin, or 0 if it cannot be determined.
	214	*/
	215	unsigned int mpc52xx_get_xtal_freq(struct device_node *node)
	216	{
	217	u32 val;
	218	unsigned int freq;
	219
	220	if (!mpc52xx_cdm)
	221	return 0;
	222
87c441e5	223	freq = mpc5xxx_get_bus_frequency(node);
df8a95f4 WG	224	if (!freq)
	225	return 0;
	226
	227	if (in_8(&mpc52xx_cdm->ipb_clk_sel) & 0x1)
	228	freq *= 2;
	229
	230	val = in_be32(&mpc52xx_cdm->rstcfg);
	231	if (val & (1 << 5))
	232	freq *= 8;
	233	else
	234	freq *= 4;
	235	if (val & (1 << 6))
	236	freq /= 12;
	237	else
	238	freq /= 16;
	239
	240	return freq;
	241	}
	242	EXPORT_SYMBOL(mpc52xx_get_xtal_freq);
	243
c8004a28 GL	244	/**
	245	* mpc52xx_restart: ppc_md->restart hook for mpc5200 using the watchdog timer
	246	*/
86b92cdd MB	247	void
	248	mpc52xx_restart(char *cmd)
	249	{
	250	local_irq_disable();
	251
	252	/* Turn on the watchdog and wait for it to expire.
	253	* It effectively does a reset. */
	254	if (mpc52xx_wdt) {
	255	out_be32(&mpc52xx_wdt->mode, 0x00000000);
	256	out_be32(&mpc52xx_wdt->count, 0x000000ff);
	257	out_be32(&mpc52xx_wdt->mode, 0x00009004);
	258	} else
f43c32ef WS	259	printk(KERN_ERR __FILE__ ": "
f43c32ef WS	260	"mpc52xx_restart: Can't access wdt. "
86b92cdd MB	261	"Restart impossible, system halted.\n");
	262
	263	while (1);
	264	}
cfa6a88c EM	265
	266	#define PSC1_RESET 0x1
	267	#define PSC1_SYNC 0x4
	268	#define PSC1_SDATA_OUT 0x1
	269	#define PSC2_RESET 0x2
	270	#define PSC2_SYNC (0x4<<4)
	271	#define PSC2_SDATA_OUT (0x1<<4)
	272	#define MPC52xx_GPIO_PSC1_MASK 0x7
	273	#define MPC52xx_GPIO_PSC2_MASK (0x7<<4)
	274
	275	/**
	276	* mpc5200_psc_ac97_gpio_reset: Use gpio pins to reset the ac97 bus
	277	*
	278	* @psc: psc number to reset (only psc 1 and 2 support ac97)
	279	*/
	280	int mpc5200_psc_ac97_gpio_reset(int psc_number)
	281	{
	282	unsigned long flags;
	283	u32 gpio;
	284	u32 mux;
	285	int out;
	286	int reset;
	287	int sync;
	288
	289	if ((!simple_gpio) \|\| (!wkup_gpio))
	290	return -ENODEV;
	291
	292	switch (psc_number) {
	293	case 0:
	294	reset = PSC1_RESET; /* AC97_1_RES */
	295	sync = PSC1_SYNC; /* AC97_1_SYNC */
	296	out = PSC1_SDATA_OUT; /* AC97_1_SDATA_OUT */
	297	gpio = MPC52xx_GPIO_PSC1_MASK;
	298	break;
	299	case 1:
	300	reset = PSC2_RESET; /* AC97_2_RES */
	301	sync = PSC2_SYNC; /* AC97_2_SYNC */
	302	out = PSC2_SDATA_OUT; /* AC97_2_SDATA_OUT */
	303	gpio = MPC52xx_GPIO_PSC2_MASK;
	304	break;
	305	default:
	306	pr_err(__FILE__ ": Unable to determine PSC, no ac97 "
	307	"cold-reset will be performed\n");
	308	return -ENODEV;
	309	}
	310
	311	spin_lock_irqsave(&gpio_lock, flags);
	312
	313	/* Reconfiure pin-muxing to gpio */
	314	mux = in_be32(&simple_gpio->port_config);
	315	out_be32(&simple_gpio->port_config, mux & (~gpio));
	316
	317	/* enable gpio pins for output */
	318	setbits8(&wkup_gpio->wkup_gpioe, reset);
	319	setbits32(&simple_gpio->simple_gpioe, sync \| out);
	320
	321	setbits8(&wkup_gpio->wkup_ddr, reset);
	322	setbits32(&simple_gpio->simple_ddr, sync \| out);
	323
	324	/* Assert cold reset */
	325	clrbits32(&simple_gpio->simple_dvo, sync \| out);
	326	clrbits8(&wkup_gpio->wkup_dvo, reset);
	327
fa32154e EM	328	/* wait for 1 us */
fa32154e EM	329	udelay(1);
cfa6a88c EM	330
	331	/* Deassert reset */
	332	setbits8(&wkup_gpio->wkup_dvo, reset);
	333
fa32154e EM	334	/* wait at least 200ns */
	335	/* 7 ~= (200ns * timebase) / ns2sec */
	336	__delay(7);
	337
cfa6a88c EM	338	/* Restore pin-muxing */
	339	out_be32(&simple_gpio->port_config, mux);
	340
	341	spin_unlock_irqrestore(&gpio_lock, flags);
	342
	343	return 0;
	344	}
	345	EXPORT_SYMBOL(mpc5200_psc_ac97_gpio_reset);