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26ef5c09 DG |
1 | #ifndef _ASM_POWERPC_CACHE_H |
2 | #define _ASM_POWERPC_CACHE_H | |
3 | ||
4 | #ifdef __KERNEL__ | |
5 | ||
26ef5c09 DG |
6 | |
7 | /* bytes per L1 cache line */ | |
8 | #if defined(CONFIG_8xx) || defined(CONFIG_403GCX) | |
9 | #define L1_CACHE_SHIFT 4 | |
10 | #define MAX_COPY_PREFETCH 1 | |
3dfa8773 KG |
11 | #elif defined(CONFIG_PPC_E500MC) |
12 | #define L1_CACHE_SHIFT 6 | |
13 | #define MAX_COPY_PREFETCH 4 | |
26ef5c09 | 14 | #elif defined(CONFIG_PPC32) |
26ef5c09 | 15 | #define MAX_COPY_PREFETCH 4 |
e7f75ad0 DK |
16 | #if defined(CONFIG_PPC_47x) |
17 | #define L1_CACHE_SHIFT 7 | |
18 | #else | |
19 | #define L1_CACHE_SHIFT 5 | |
20 | #endif | |
26ef5c09 DG |
21 | #else /* CONFIG_PPC64 */ |
22 | #define L1_CACHE_SHIFT 7 | |
23 | #endif | |
24 | ||
25 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) | |
26 | ||
27 | #define SMP_CACHE_BYTES L1_CACHE_BYTES | |
26ef5c09 DG |
28 | |
29 | #if defined(__powerpc64__) && !defined(__ASSEMBLY__) | |
30 | struct ppc64_caches { | |
31 | u32 dsize; /* L1 d-cache size */ | |
32 | u32 dline_size; /* L1 d-cache line size */ | |
33 | u32 log_dline_size; | |
34 | u32 dlines_per_page; | |
35 | u32 isize; /* L1 i-cache size */ | |
36 | u32 iline_size; /* L1 i-cache line size */ | |
37 | u32 log_iline_size; | |
38 | u32 ilines_per_page; | |
39 | }; | |
40 | ||
41 | extern struct ppc64_caches ppc64_caches; | |
42 | #endif /* __powerpc64__ && ! __ASSEMBLY__ */ | |
43 | ||
bd67fcf9 | 44 | #if !defined(__ASSEMBLY__) |
54cb27a7 | 45 | #define __read_mostly __attribute__((__section__(".data..read_mostly"))) |
bd67fcf9 TB |
46 | #endif |
47 | ||
26ef5c09 DG |
48 | #endif /* __KERNEL__ */ |
49 | #endif /* _ASM_POWERPC_CACHE_H */ |