[net-next-2.6.git] / arch / mn10300 / proc-mn103e010 / include / proc / cache.h

/* MN103E010 Cache specification
 *
 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
 * Written by David Howells (dhowells@redhat.com)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public Licence
 * as published by the Free Software Foundation; either version
 * 2 of the Licence, or (at your option) any later version.
 */
#ifndef _ASM_PROC_CACHE_H
#define _ASM_PROC_CACHE_H

/* L1 cache */

#define L1_CACHE_NWAYS		4	/* number of ways in caches */
#define L1_CACHE_NENTRIES	256	/* number of entries in each way */
#define L1_CACHE_BYTES		16	/* bytes per entry */
#define L1_CACHE_SHIFT		4	/* shift for bytes per entry */
#define L1_CACHE_WAYDISP	0x1000	/* displacement of one way from the next */

#define L1_CACHE_TAG_VALID	0x00000001	/* cache tag valid bit */
#define L1_CACHE_TAG_DIRTY	0x00000008	/* data cache tag dirty bit */
#define L1_CACHE_TAG_ENTRY	0x00000ff0	/* cache tag entry address mask */
#define L1_CACHE_TAG_ADDRESS	0xfffff000	/* cache tag line address mask */

/*
 * specification of the interval between interrupt checking intervals whilst
 * managing the cache with the interrupts disabled
 */
#define MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL	4

/*
 * The size of range at which it becomes more economical to just flush the
 * whole cache rather than trying to flush the specified range.
 */
#define MN10300_DCACHE_FLUSH_BORDER	\
	+(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES)
#define MN10300_DCACHE_FLUSH_INV_BORDER	\
	+(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES)

#endif /* _ASM_PROC_CACHE_H */
Commit	Line	Data
b920de1b DH	1	/* MN103E010 Cache specification
	2	*
	3	* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
	4	* Written by David Howells (dhowells@redhat.com)
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public Licence
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the Licence, or (at your option) any later version.
	10	*/
	11	#ifndef _ASM_PROC_CACHE_H
	12	#define _ASM_PROC_CACHE_H
	13
	14	/* L1 cache */
	15
	16	#define L1_CACHE_NWAYS 4 /* number of ways in caches */
	17	#define L1_CACHE_NENTRIES 256 /* number of entries in each way */
	18	#define L1_CACHE_BYTES 16 /* bytes per entry */
	19	#define L1_CACHE_SHIFT 4 /* shift for bytes per entry */
	20	#define L1_CACHE_WAYDISP 0x1000 /* displacement of one way from the next */
	21
	22	#define L1_CACHE_TAG_VALID 0x00000001 /* cache tag valid bit */
	23	#define L1_CACHE_TAG_DIRTY 0x00000008 /* data cache tag dirty bit */
	24	#define L1_CACHE_TAG_ENTRY 0x00000ff0 /* cache tag entry address mask */
	25	#define L1_CACHE_TAG_ADDRESS 0xfffff000 /* cache tag line address mask */
	26
	27	/*
	28	* specification of the interval between interrupt checking intervals whilst
	29	* managing the cache with the interrupts disabled
	30	*/
	31	#define MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL 4
	32
0bd3eb6c AT	33	/*
	34	* The size of range at which it becomes more economical to just flush the
	35	* whole cache rather than trying to flush the specified range.
	36	*/
	37	#define MN10300_DCACHE_FLUSH_BORDER \
	38	+(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES)
	39	#define MN10300_DCACHE_FLUSH_INV_BORDER \
	40	+(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES)
	41
b920de1b	42	#endif /* _ASM_PROC_CACHE_H */