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MIPS: TXx9: Add TX4939 ATA support (v2)
[net-next-2.6.git] / arch / mips / txx9 / generic / setup_tx4939.c
CommitLineData
0dcdbe6a
AN		 1/*
2 * TX4939 setup routines
3 * Based on linux/arch/mips/txx9/generic/setup_tx4938.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * 2003-2005 (c) MontaVista Software, Inc.
7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/delay.h>
16#include <linux/netdevice.h>
17#include <linux/notifier.h>
18#include <linux/sysdev.h>
19#include <linux/ethtool.h>
20#include <linux/param.h>
21#include <linux/ptrace.h>
22#include <linux/mtd/physmap.h>
4bacc687 23#include <linux/platform_device.h>
0dcdbe6a
AN		 24#include <asm/bootinfo.h>
25#include <asm/reboot.h>
26#include <asm/traps.h>
27#include <asm/txx9irq.h>
28#include <asm/txx9tmr.h>
29#include <asm/txx9/generic.h>
30#include <asm/txx9/tx4939.h>
31
32static void __init tx4939_wdr_init(void)
33{
34 /* report watchdog reset status */
35 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST)
36 pr_warning("Watchdog reset detected at 0x%lx\n",
37 read_c0_errorepc());
38 /* clear WatchDogReset (W1C) */
39 tx4939_ccfg_set(TX4939_CCFG_WDRST);
40 /* do reset on watchdog */
41 tx4939_ccfg_set(TX4939_CCFG_WR);
42}
43
44void __init tx4939_wdt_init(void)
45{
46 txx9_wdt_init(TX4939_TMR_REG(2) & 0xfffffffffULL);
47}
48
49static void tx4939_machine_restart(char *command)
50{
51 local_irq_disable();
52 pr_emerg("Rebooting (with %s watchdog reset)...\n",
53 (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) ?
54 "external" : "internal");
55 /* clear watchdog status */
56 tx4939_ccfg_set(TX4939_CCFG_WDRST); /* W1C */
57 txx9_wdt_now(TX4939_TMR_REG(2) & 0xfffffffffULL);
58 while (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST))
59 ;
60 mdelay(10);
61 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) {
62 pr_emerg("Rebooting (with internal watchdog reset)...\n");
63 /* External WDRST failed. Do internal watchdog reset */
64 tx4939_ccfg_clear(TX4939_CCFG_WDREXEN);
65 }
66 /* fallback */
67 (*_machine_halt)();
68}
69
70void show_registers(struct pt_regs *regs);
71static int tx4939_be_handler(struct pt_regs *regs, int is_fixup)
72{
73 int data = regs->cp0_cause & 4;
74 console_verbose();
75 pr_err("%cBE exception at %#lx\n",
76 data ? 'D' : 'I', regs->cp0_epc);
77 pr_err("ccfg:%llx, toea:%llx\n",
78 (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
79 (unsigned long long)____raw_readq(&tx4939_ccfgptr->toea));
80#ifdef CONFIG_PCI
81 tx4927_report_pcic_status();
82#endif
83 show_registers(regs);
84 panic("BusError!");
85}
86static void __init tx4939_be_init(void)
87{
88 board_be_handler = tx4939_be_handler;
89}
90
91static struct resource tx4939_sdram_resource[4];
92static struct resource tx4939_sram_resource;
93#define TX4939_SRAM_SIZE 0x800
94
95void __init tx4939_add_memory_regions(void)
96{
97 int i;
98 unsigned long start, size;
99 u64 win;
100
101 for (i = 0; i < 4; i++) {
102 if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
103 continue;
104 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
105 start = (unsigned long)(win >> 48);
106 size = (((unsigned long)(win >> 32) & 0xffff) + 1) - start;
107 add_memory_region(start << 20, size << 20, BOOT_MEM_RAM);
108 }
109}
110
111void __init tx4939_setup(void)
112{
113 int i;
114 __u32 divmode;
115 __u64 pcfg;
116 int cpuclk = 0;
117
118 txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE,
119 TX4939_REG_SIZE);
120 set_c0_config(TX49_CONF_CWFON);
121
122 /* SDRAMC,EBUSC are configured by PROM */
123 for (i = 0; i < 4; i++) {
124 if (!(TX4939_EBUSC_CR(i) & 0x8))
125 continue; /* disabled */
126 txx9_ce_res[i].start = (unsigned long)TX4939_EBUSC_BA(i);
127 txx9_ce_res[i].end =
128 txx9_ce_res[i].start + TX4939_EBUSC_SIZE(i) - 1;
129 request_resource(&iomem_resource, &txx9_ce_res[i]);
130 }
131
132 /* clocks */
133 if (txx9_master_clock) {
134 /* calculate cpu_clock from master_clock */
135 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
136 TX4939_CCFG_MULCLK_MASK;
137 cpuclk = txx9_master_clock * 20 / 2;
138 switch (divmode) {
139 case TX4939_CCFG_MULCLK_8:
140 cpuclk = cpuclk / 3 * 4 /* / 6 * 8 */; break;
141 case TX4939_CCFG_MULCLK_9:
142 cpuclk = cpuclk / 2 * 3 /* / 6 * 9 */; break;
143 case TX4939_CCFG_MULCLK_10:
144 cpuclk = cpuclk / 3 * 5 /* / 6 * 10 */; break;
145 case TX4939_CCFG_MULCLK_11:
146 cpuclk = cpuclk / 6 * 11; break;
147 case TX4939_CCFG_MULCLK_12:
148 cpuclk = cpuclk * 2 /* / 6 * 12 */; break;
149 case TX4939_CCFG_MULCLK_13:
150 cpuclk = cpuclk / 6 * 13; break;
151 case TX4939_CCFG_MULCLK_14:
152 cpuclk = cpuclk / 3 * 7 /* / 6 * 14 */; break;
153 case TX4939_CCFG_MULCLK_15:
154 cpuclk = cpuclk / 2 * 5 /* / 6 * 15 */; break;
155 }
156 txx9_cpu_clock = cpuclk;
157 } else {
158 if (txx9_cpu_clock == 0)
159 txx9_cpu_clock = 400000000; /* 400MHz */
160 /* calculate master_clock from cpu_clock */
161 cpuclk = txx9_cpu_clock;
162 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
163 TX4939_CCFG_MULCLK_MASK;
164 switch (divmode) {
165 case TX4939_CCFG_MULCLK_8:
166 txx9_master_clock = cpuclk * 6 / 8; break;
167 case TX4939_CCFG_MULCLK_9:
168 txx9_master_clock = cpuclk * 6 / 9; break;
169 case TX4939_CCFG_MULCLK_10:
170 txx9_master_clock = cpuclk * 6 / 10; break;
171 case TX4939_CCFG_MULCLK_11:
172 txx9_master_clock = cpuclk * 6 / 11; break;
173 case TX4939_CCFG_MULCLK_12:
174 txx9_master_clock = cpuclk * 6 / 12; break;
175 case TX4939_CCFG_MULCLK_13:
176 txx9_master_clock = cpuclk * 6 / 13; break;
177 case TX4939_CCFG_MULCLK_14:
178 txx9_master_clock = cpuclk * 6 / 14; break;
179 case TX4939_CCFG_MULCLK_15:
180 txx9_master_clock = cpuclk * 6 / 15; break;
181 }
182 txx9_master_clock /= 10; /* * 2 / 20 */
183 }
184 /* calculate gbus_clock from cpu_clock */
185 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
186 TX4939_CCFG_YDIVMODE_MASK;
187 txx9_gbus_clock = txx9_cpu_clock;
188 switch (divmode) {
189 case TX4939_CCFG_YDIVMODE_2:
190 txx9_gbus_clock /= 2; break;
191 case TX4939_CCFG_YDIVMODE_3:
192 txx9_gbus_clock /= 3; break;
193 case TX4939_CCFG_YDIVMODE_5:
194 txx9_gbus_clock /= 5; break;
195 case TX4939_CCFG_YDIVMODE_6:
196 txx9_gbus_clock /= 6; break;
197 }
198 /* change default value to udelay/mdelay take reasonable time */
199 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
200
201 /* CCFG */
202 tx4939_wdr_init();
203 /* clear BusErrorOnWrite flag (W1C) */
204 tx4939_ccfg_set(TX4939_CCFG_WDRST | TX4939_CCFG_BEOW);
205 /* enable Timeout BusError */
206 if (txx9_ccfg_toeon)
207 tx4939_ccfg_set(TX4939_CCFG_TOE);
208
209 /* DMA selection */
210 txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_DMASEL_ALL);
211
212 /* Use external clock for external arbiter */
213 if (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB))
214 txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_PCICLKEN_ALL);
215
216 pr_info("%s -- %dMHz(M%dMHz,G%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
217 txx9_pcode_str,
218 (cpuclk + 500000) / 1000000,
219 (txx9_master_clock + 500000) / 1000000,
220 (txx9_gbus_clock + 500000) / 1000000,
221 (__u32)____raw_readq(&tx4939_ccfgptr->crir),
222 (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
223 (unsigned long long)____raw_readq(&tx4939_ccfgptr->pcfg));
224
225 pr_info("%s DDRC -- EN:%08x", txx9_pcode_str,
226 (__u32)____raw_readq(&tx4939_ddrcptr->winen));
227 for (i = 0; i < 4; i++) {
228 __u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
229 if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
230 continue; /* disabled */
231 printk(KERN_CONT " #%d:%016llx", i, (unsigned long long)win);
232 tx4939_sdram_resource[i].name = "DDR SDRAM";
233 tx4939_sdram_resource[i].start =
234 (unsigned long)(win >> 48) << 20;
235 tx4939_sdram_resource[i].end =
236 ((((unsigned long)(win >> 32) & 0xffff) + 1) <<
237 20) - 1;
238 tx4939_sdram_resource[i].flags = IORESOURCE_MEM;
239 request_resource(&iomem_resource, &tx4939_sdram_resource[i]);
240 }
241 printk(KERN_CONT "\n");
242
243 /* SRAM */
244 if (____raw_readq(&tx4939_sramcptr->cr) & 1) {
245 unsigned int size = TX4939_SRAM_SIZE;
246 tx4939_sram_resource.name = "SRAM";
247 tx4939_sram_resource.start =
248 (____raw_readq(&tx4939_sramcptr->cr) >> (39-11))
249 & ~(size - 1);
250 tx4939_sram_resource.end =
251 tx4939_sram_resource.start + TX4939_SRAM_SIZE - 1;
252 tx4939_sram_resource.flags = IORESOURCE_MEM;
253 request_resource(&iomem_resource, &tx4939_sram_resource);
254 }
255
256 /* TMR */
257 /* disable all timers */
258 for (i = 0; i < TX4939_NR_TMR; i++)
259 txx9_tmr_init(TX4939_TMR_REG(i) & 0xfffffffffULL);
260
261 /* DMA */
262 for (i = 0; i < 2; i++)
263 ____raw_writeq(TX4938_DMA_MCR_MSTEN,
264 (void __iomem *)(TX4939_DMA_REG(i) + 0x50));
265
266 /* set PCIC1 reset (required to prevent hangup on BIST) */
267 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
268 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
269 if (pcfg & (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE)) {
270 mdelay(1); /* at least 128 cpu clock */
271 /* clear PCIC1 reset */
272 txx9_clear64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
273 } else {
274 pr_info("%s: stop PCIC1\n", txx9_pcode_str);
275 /* stop PCIC1 */
276 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1CKD);
277 }
278 if (!(pcfg & TX4939_PCFG_ET0MODE)) {
279 pr_info("%s: stop ETH0\n", txx9_pcode_str);
280 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0RST);
281 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0CKD);
282 }
283 if (!(pcfg & TX4939_PCFG_ET1MODE)) {
284 pr_info("%s: stop ETH1\n", txx9_pcode_str);
285 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1RST);
286 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1CKD);
287 }
288
289 _machine_restart = tx4939_machine_restart;
290 board_be_init = tx4939_be_init;
291}
292
293void __init tx4939_time_init(unsigned int tmrnr)
294{
295 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_TINTDIS)
296 txx9_clockevent_init(TX4939_TMR_REG(tmrnr) & 0xfffffffffULL,
297 TXX9_IRQ_BASE + TX4939_IR_TMR(tmrnr),
298 TXX9_IMCLK);
299}
300
301void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask)
302{
303 int i;
304 unsigned int ch_mask = 0;
305 __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
306
307 cts_mask |= ~1; /* only SIO0 have RTS/CTS */
308 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO0)
309 cts_mask |= 1 << 0; /* disable SIO0 RTS/CTS by PCFG setting */
310 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2)
311 ch_mask |= 1 << 2; /* disable SIO2 by PCFG setting */
312 if (pcfg & TX4939_PCFG_SIO3MODE)
313 ch_mask |= 1 << 3; /* disable SIO3 by PCFG setting */
314 for (i = 0; i < 4; i++) {
315 if ((1 << i) & ch_mask)
316 continue;
317 txx9_sio_init(TX4939_SIO_REG(i) & 0xfffffffffULL,
318 TXX9_IRQ_BASE + TX4939_IR_SIO(i),
319 i, sclk, (1 << i) & cts_mask);
320 }
321}
322
323#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
324static int tx4939_get_eth_speed(struct net_device *dev)
325{
326 struct ethtool_cmd cmd = { ETHTOOL_GSET };
327 int speed = 100; /* default 100Mbps */
328 int err;
329 if (!dev->ethtool_ops || !dev->ethtool_ops->get_settings)
330 return speed;
331 err = dev->ethtool_ops->get_settings(dev, &cmd);
332 if (err < 0)
333 return speed;
334 speed = cmd.speed == SPEED_100 ? 100 : 10;
335 return speed;
336}
337static int tx4939_netdev_event(struct notifier_block *this,
338 unsigned long event,
339 void *ptr)
340{
341 struct net_device *dev = ptr;
342 if (event == NETDEV_CHANGE && netif_carrier_ok(dev)) {
343 __u64 bit = 0;
344 if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(0))
345 bit = TX4939_PCFG_SPEED0;
346 else if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(1))
347 bit = TX4939_PCFG_SPEED1;
348 if (bit) {
349 int speed = tx4939_get_eth_speed(dev);
350 if (speed == 100)
351 txx9_set64(&tx4939_ccfgptr->pcfg, bit);
352 else
353 txx9_clear64(&tx4939_ccfgptr->pcfg, bit);
354 }
355 }
356 return NOTIFY_DONE;
357}
358
359static struct notifier_block tx4939_netdev_notifier = {
360 .notifier_call = tx4939_netdev_event,
361 .priority = 1,
362};
363
364void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
365{
366 u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
367
368 if (addr0 && (pcfg & TX4939_PCFG_ET0MODE))
369 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(0), addr0);
370 if (addr1 && (pcfg & TX4939_PCFG_ET1MODE))
371 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(1), addr1);
372 register_netdevice_notifier(&tx4939_netdev_notifier);
373}
374#else
375void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
376{
377}
378#endif
379
380void __init tx4939_mtd_init(int ch)
381{
382 struct physmap_flash_data pdata = {
383 .width = TX4939_EBUSC_WIDTH(ch) / 8,
384 };
385 unsigned long start = txx9_ce_res[ch].start;
386 unsigned long size = txx9_ce_res[ch].end - start + 1;
387
388 if (!(TX4939_EBUSC_CR(ch) & 0x8))
389 return; /* disabled */
390 txx9_physmap_flash_init(ch, start, size, &pdata);
391}
392
4bacc687
AN		 393#define TX4939_ATA_REG_PHYS(ch) (TX4939_ATA_REG(ch) & 0xfffffffffULL)
394void __init tx4939_ata_init(void)
395{
396 static struct resource ata0_res[] = {
397 {
398 .start = TX4939_ATA_REG_PHYS(0),
399 .end = TX4939_ATA_REG_PHYS(0) + 0x1000 - 1,
400 .flags = IORESOURCE_MEM,
401 }, {
402 .start = TXX9_IRQ_BASE + TX4939_IR_ATA(0),
403 .flags = IORESOURCE_IRQ,
404 },
405 };
406 static struct resource ata1_res[] = {
407 {
408 .start = TX4939_ATA_REG_PHYS(1),
409 .end = TX4939_ATA_REG_PHYS(1) + 0x1000 - 1,
410 .flags = IORESOURCE_MEM,
411 }, {
412 .start = TXX9_IRQ_BASE + TX4939_IR_ATA(1),
413 .flags = IORESOURCE_IRQ,
414 },
415 };
416 static struct platform_device ata0_dev = {
417 .name = "tx4939ide",
418 .id = 0,
419 .num_resources = ARRAY_SIZE(ata0_res),
420 .resource = ata0_res,
421 };
422 static struct platform_device ata1_dev = {
423 .name = "tx4939ide",
424 .id = 1,
425 .num_resources = ARRAY_SIZE(ata1_res),
426 .resource = ata1_res,
427 };
428 __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
429
430 if (pcfg & TX4939_PCFG_ATA0MODE)
431 platform_device_register(&ata0_dev);
432 if ((pcfg & (TX4939_PCFG_ATA1MODE |
433 TX4939_PCFG_ET1MODE |
434 TX4939_PCFG_ET0MODE)) == TX4939_PCFG_ATA1MODE)
435 platform_device_register(&ata1_dev);
436}
437
0dcdbe6a
AN		 438static void __init tx4939_stop_unused_modules(void)
439{
440 __u64 pcfg, rst = 0, ckd = 0;
441 char buf[128];
442
443 buf[0] = '\0';
444 local_irq_disable();
445 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
446 if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
447 TX4939_PCFG_I2SMODE_ACLC) {
448 rst |= TX4939_CLKCTR_ACLRST;
449 ckd |= TX4939_CLKCTR_ACLCKD;
450 strcat(buf, " ACLC");
451 }
452 if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
453 TX4939_PCFG_I2SMODE_I2S &&
454 (pcfg & TX4939_PCFG_I2SMODE_MASK) !=
455 TX4939_PCFG_I2SMODE_I2S_ALT) {
456 rst |= TX4939_CLKCTR_I2SRST;
457 ckd |= TX4939_CLKCTR_I2SCKD;
458 strcat(buf, " I2S");
459 }
460 if (!(pcfg & TX4939_PCFG_ATA0MODE)) {
461 rst |= TX4939_CLKCTR_ATA0RST;
462 ckd |= TX4939_CLKCTR_ATA0CKD;
463 strcat(buf, " ATA0");
464 }
465 if (!(pcfg & TX4939_PCFG_ATA1MODE)) {
466 rst |= TX4939_CLKCTR_ATA1RST;
467 ckd |= TX4939_CLKCTR_ATA1CKD;
468 strcat(buf, " ATA1");
469 }
470 if (pcfg & TX4939_PCFG_SPIMODE) {
471 rst |= TX4939_CLKCTR_SPIRST;
472 ckd |= TX4939_CLKCTR_SPICKD;
473 strcat(buf, " SPI");
474 }
475 if (!(pcfg & (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE))) {
476 rst |= TX4939_CLKCTR_VPCRST;
477 ckd |= TX4939_CLKCTR_VPCCKD;
478 strcat(buf, " VPC");
479 }
480 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2) {
481 rst |= TX4939_CLKCTR_SIO2RST;
482 ckd |= TX4939_CLKCTR_SIO2CKD;
483 strcat(buf, " SIO2");
484 }
485 if (pcfg & TX4939_PCFG_SIO3MODE) {
486 rst |= TX4939_CLKCTR_SIO3RST;
487 ckd |= TX4939_CLKCTR_SIO3CKD;
488 strcat(buf, " SIO3");
489 }
490 if (rst | ckd) {
491 txx9_set64(&tx4939_ccfgptr->clkctr, rst);
492 txx9_set64(&tx4939_ccfgptr->clkctr, ckd);
493 }
494 local_irq_enable();
495 if (buf[0])
496 pr_info("%s: stop%s\n", txx9_pcode_str, buf);
497}
498
499static int __init tx4939_late_init(void)
500{
501 if (txx9_pcode != 0x4939)
502 return -ENODEV;
503 tx4939_stop_unused_modules();
504 return 0;
505}
506late_initcall(tx4939_late_init);
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