[net-next-2.6.git] / arch / mips / sibyte / sb1250 / irq.c

/*
 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/linkage.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/smp.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/kernel_stat.h>

#include <asm/errno.h>
#include <asm/signal.h>
#include <asm/system.h>
#include <asm/ptrace.h>
#include <asm/io.h>

#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_int.h>
#include <asm/sibyte/sb1250_uart.h>
#include <asm/sibyte/sb1250_scd.h>
#include <asm/sibyte/sb1250.h>

/*
 * These are the routines that handle all the low level interrupt stuff.
 * Actions handled here are: initialization of the interrupt map, requesting of
 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
 * for interrupt lines
 */


#define shutdown_sb1250_irq	disable_sb1250_irq
static void end_sb1250_irq(unsigned int irq);
static void enable_sb1250_irq(unsigned int irq);
static void disable_sb1250_irq(unsigned int irq);
static unsigned int startup_sb1250_irq(unsigned int irq);
static void ack_sb1250_irq(unsigned int irq);
#ifdef CONFIG_SMP
static void sb1250_set_affinity(unsigned int irq, cpumask_t mask);
#endif

#ifdef CONFIG_SIBYTE_HAS_LDT
extern unsigned long ldt_eoi_space;
#endif

#ifdef CONFIG_KGDB
static int kgdb_irq;

/* Default to UART1 */
int kgdb_port = 1;
#ifdef CONFIG_SIBYTE_SB1250_DUART
extern char sb1250_duart_present[];
#endif
#endif

static struct hw_interrupt_type sb1250_irq_type = {
	.typename = "SB1250-IMR",
	.startup = startup_sb1250_irq,
	.shutdown = shutdown_sb1250_irq,
	.enable = enable_sb1250_irq,
	.disable = disable_sb1250_irq,
	.ack = ack_sb1250_irq,
	.end = end_sb1250_irq,
#ifdef CONFIG_SMP
	.set_affinity = sb1250_set_affinity
#endif
};

/* Store the CPU id (not the logical number) */
int sb1250_irq_owner[SB1250_NR_IRQS];

DEFINE_SPINLOCK(sb1250_imr_lock);

void sb1250_mask_irq(int cpu, int irq)
{
	unsigned long flags;
	u64 cur_ints;

	spin_lock_irqsave(&sb1250_imr_lock, flags);
	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
	cur_ints |= (((u64) 1) << irq);
	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
	spin_unlock_irqrestore(&sb1250_imr_lock, flags);
}

void sb1250_unmask_irq(int cpu, int irq)
{
	unsigned long flags;
	u64 cur_ints;

	spin_lock_irqsave(&sb1250_imr_lock, flags);
	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
	cur_ints &= ~(((u64) 1) << irq);
	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
	spin_unlock_irqrestore(&sb1250_imr_lock, flags);
}

#ifdef CONFIG_SMP
static void sb1250_set_affinity(unsigned int irq, cpumask_t mask)
{
	int i = 0, old_cpu, cpu, int_on;
	u64 cur_ints;
	irq_desc_t *desc = irq_desc + irq;
	unsigned long flags;

	i = first_cpu(mask);

	if (cpus_weight(mask) > 1) {
		printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
		return;
	}

	/* Convert logical CPU to physical CPU */
	cpu = cpu_logical_map(i);

	/* Protect against other affinity changers and IMR manipulation */
	spin_lock_irqsave(&desc->lock, flags);
	spin_lock(&sb1250_imr_lock);

	/* Swizzle each CPU's IMR (but leave the IP selection alone) */
	old_cpu = sb1250_irq_owner[irq];
	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
					R_IMR_INTERRUPT_MASK));
	int_on = !(cur_ints & (((u64) 1) << irq));
	if (int_on) {
		/* If it was on, mask it */
		cur_ints |= (((u64) 1) << irq);
		____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
					R_IMR_INTERRUPT_MASK));
	}
	sb1250_irq_owner[irq] = cpu;
	if (int_on) {
		/* unmask for the new CPU */
		cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
		cur_ints &= ~(((u64) 1) << irq);
		____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
	}
	spin_unlock(&sb1250_imr_lock);
	spin_unlock_irqrestore(&desc->lock, flags);
}
#endif

/*****************************************************************************/

static unsigned int startup_sb1250_irq(unsigned int irq)
{
	sb1250_unmask_irq(sb1250_irq_owner[irq], irq);

	return 0;		/* never anything pending */
}


static void disable_sb1250_irq(unsigned int irq)
{
	sb1250_mask_irq(sb1250_irq_owner[irq], irq);
}

static void enable_sb1250_irq(unsigned int irq)
{
	sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
}


static void ack_sb1250_irq(unsigned int irq)
{
#ifdef CONFIG_SIBYTE_HAS_LDT
	u64 pending;

	/*
	 * If the interrupt was an HT interrupt, now is the time to
	 * clear it.  NOTE: we assume the HT bridge was set up to
	 * deliver the interrupts to all CPUs (which makes affinity
	 * changing easier for us)
	 */
	pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
						    R_IMR_LDT_INTERRUPT)));
	pending &= ((u64)1 << (irq));
	if (pending) {
		int i;
		for (i=0; i<NR_CPUS; i++) {
			int cpu;
#ifdef CONFIG_SMP
			cpu = cpu_logical_map(i);
#else
			cpu = i;
#endif
			/*
			 * Clear for all CPUs so an affinity switch
			 * doesn't find an old status
			 */
			__raw_writeq(pending,
				     IOADDR(A_IMR_REGISTER(cpu,
						R_IMR_LDT_INTERRUPT_CLR)));
		}

		/*
		 * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
		 * Pass 2, the LDT world may be edge-triggered, but
		 * this EOI shouldn't hurt.  If they are
		 * level-sensitive, the EOI is required.
		 */
		*(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
	}
#endif
	sb1250_mask_irq(sb1250_irq_owner[irq], irq);
}


static void end_sb1250_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
		sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
	}
}


void __init init_sb1250_irqs(void)
{
	int i;

	for (i = 0; i < NR_IRQS; i++) {
		irq_desc[i].status = IRQ_DISABLED;
		irq_desc[i].action = 0;
		irq_desc[i].depth = 1;
		if (i < SB1250_NR_IRQS) {
			irq_desc[i].handler = &sb1250_irq_type;
			sb1250_irq_owner[i] = 0;
		} else {
			irq_desc[i].handler = &no_irq_type;
		}
	}
}


static irqreturn_t  sb1250_dummy_handler(int irq, void *dev_id,
	struct pt_regs *regs)
{
	return IRQ_NONE;
}

static struct irqaction sb1250_dummy_action = {
	.handler = sb1250_dummy_handler,
	.flags   = 0,
	.mask    = CPU_MASK_NONE,
	.name    = "sb1250-private",
	.next    = NULL,
	.dev_id  = 0
};

int sb1250_steal_irq(int irq)
{
	irq_desc_t *desc = irq_desc + irq;
	unsigned long flags;
	int retval = 0;

	if (irq >= SB1250_NR_IRQS)
		return -EINVAL;

	spin_lock_irqsave(&desc->lock,flags);
	/* Don't allow sharing at all for these */
	if (desc->action != NULL)
		retval = -EBUSY;
	else {
		desc->action = &sb1250_dummy_action;
		desc->depth = 0;
	}
	spin_unlock_irqrestore(&desc->lock,flags);
	return 0;
}

/*
 *  arch_init_irq is called early in the boot sequence from init/main.c via
 *  init_IRQ.  It is responsible for setting up the interrupt mapper and
 *  installing the handler that will be responsible for dispatching interrupts
 *  to the "right" place.
 */
/*
 * For now, map all interrupts to IP[2].  We could save
 * some cycles by parceling out system interrupts to different
 * IP lines, but keep it simple for bringup.  We'll also direct
 * all interrupts to a single CPU; we should probably route
 * PCI and LDT to one cpu and everything else to the other
 * to balance the load a bit.
 *
 * On the second cpu, everything is set to IP5, which is
 * ignored, EXCEPT the mailbox interrupt.  That one is
 * set to IP[2] so it is handled.  This is needed so we
 * can do cross-cpu function calls, as requred by SMP
 */

#define IMR_IP2_VAL	K_INT_MAP_I0
#define IMR_IP3_VAL	K_INT_MAP_I1
#define IMR_IP4_VAL	K_INT_MAP_I2
#define IMR_IP5_VAL	K_INT_MAP_I3
#define IMR_IP6_VAL	K_INT_MAP_I4

void __init arch_init_irq(void)
{

	unsigned int i;
	u64 tmp;
	unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
		STATUSF_IP1 | STATUSF_IP0;

	/* Default everything to IP2 */
	for (i = 0; i < SB1250_NR_IRQS; i++) {	/* was I0 */
		__raw_writeq(IMR_IP2_VAL,
			     IOADDR(A_IMR_REGISTER(0,
						   R_IMR_INTERRUPT_MAP_BASE) +
				    (i << 3)));
		__raw_writeq(IMR_IP2_VAL,
			     IOADDR(A_IMR_REGISTER(1,
						   R_IMR_INTERRUPT_MAP_BASE) +
				    (i << 3)));
	}

	init_sb1250_irqs();

	/*
	 * Map the high 16 bits of the mailbox registers to IP[3], for
	 * inter-cpu messages
	 */
	/* Was I1 */
	__raw_writeq(IMR_IP3_VAL,
		     IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
			    (K_INT_MBOX_0 << 3)));
	__raw_writeq(IMR_IP3_VAL,
		     IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
			    (K_INT_MBOX_0 << 3)));

	/* Clear the mailboxes.  The firmware may leave them dirty */
	__raw_writeq(0xffffffffffffffffULL,
		     IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
	__raw_writeq(0xffffffffffffffffULL,
		     IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));

	/* Mask everything except the mailbox registers for both cpus */
	tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
	__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
	__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));

	sb1250_steal_irq(K_INT_MBOX_0);

	/*
	 * Note that the timer interrupts are also mapped, but this is
	 * done in sb1250_time_init().  Also, the profiling driver
	 * does its own management of IP7.
	 */

#ifdef CONFIG_KGDB
	imask |= STATUSF_IP6;
#endif
	/* Enable necessary IPs, disable the rest */
	change_c0_status(ST0_IM, imask);

#ifdef CONFIG_KGDB
	if (kgdb_flag) {
		kgdb_irq = K_INT_UART_0 + kgdb_port;

#ifdef CONFIG_SIBYTE_SB1250_DUART
		sb1250_duart_present[kgdb_port] = 0;
#endif
		/* Setup uart 1 settings, mapper */
		__raw_writeq(M_DUART_IMR_BRK,
			     IOADDR(A_DUART_IMRREG(kgdb_port)));

		sb1250_steal_irq(kgdb_irq);
		__raw_writeq(IMR_IP6_VAL,
			     IOADDR(A_IMR_REGISTER(0,
						   R_IMR_INTERRUPT_MAP_BASE) +
				    (kgdb_irq << 3)));
		sb1250_unmask_irq(0, kgdb_irq);
	}
#endif
}

#ifdef CONFIG_KGDB

#include <linux/delay.h>

#define duart_out(reg, val)     csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
#define duart_in(reg)           csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))

static void sb1250_kgdb_interrupt(struct pt_regs *regs)
{
	/*
	 * Clear break-change status (allow some time for the remote
	 * host to stop the break, since we would see another
	 * interrupt on the end-of-break too)
	 */
	kstat_this_cpu.irqs[kgdb_irq]++;
	mdelay(500);
	duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
				M_DUART_RX_EN | M_DUART_TX_EN);
	set_async_breakpoint(&regs->cp0_epc);
}

#endif 	/* CONFIG_KGDB */

static inline int dclz(unsigned long long x)
{
	int lz;

	__asm__ (
	"	.set	push						\n"
	"	.set	mips64						\n"
	"	dclz	%0, %1						\n"
	"	.set	pop						\n"
	: "=r" (lz)
	: "r" (x));

	return lz;
}

asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
{
	unsigned int pending;

#ifdef CONFIG_SIBYTE_SB1250_PROF
	/* Set compare to count to silence count/compare timer interrupts */
	write_c0_count(read_c0_count());
#endif

	/*
	 * What a pain. We have to be really careful saving the upper 32 bits
	 * of any * register across function calls if we don't want them
	 * trashed--since were running in -o32, the calling routing never saves
	 * the full 64 bits of a register across a function call.  Being the
	 * interrupt handler, we're guaranteed that interrupts are disabled
	 * during this code so we don't have to worry about random interrupts
	 * blasting the high 32 bits.
	 */

	pending = read_c0_cause();

#ifdef CONFIG_SIBYTE_SB1250_PROF
	if (pending & CAUSEF_IP7) { /* Cpu performance counter interrupt */
		sbprof_cpu_intr(exception_epc(regs));
	}
#endif

	if (pending & CAUSEF_IP4)
		sb1250_timer_interrupt(regs);

#ifdef CONFIG_SMP
	if (pending & CAUSEF_IP3)
		sb1250_mailbox_interrupt(regs);
#endif

#ifdef CONFIG_KGDB
	if (pending & CAUSEF_IP6)			/* KGDB (uart 1) */
		sb1250_kgdb_interrupt(regs);
#endif

	if (pending & CAUSEF_IP2) {
		unsigned long long mask;

		/*
		 * Default...we've hit an IP[2] interrupt, which means we've
		 * got to check the 1250 interrupt registers to figure out what
		 * to do.  Need to detect which CPU we're on, now that
		 ~ smp_affinity is supported.
		 */
		mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(),
		                              R_IMR_INTERRUPT_STATUS_BASE)));
		if (mask)
			do_IRQ(63 - dclz(mask), regs);
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version 2
	7	* of the License, or (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	17	*/
	18	#include <linux/config.h>
	19	#include <linux/kernel.h>
	20	#include <linux/init.h>
	21	#include <linux/linkage.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/spinlock.h>
	24	#include <linux/smp.h>
	25	#include <linux/mm.h>
	26	#include <linux/slab.h>
	27	#include <linux/kernel_stat.h>
	28
	29	#include <asm/errno.h>
	30	#include <asm/signal.h>
	31	#include <asm/system.h>
	32	#include <asm/ptrace.h>
	33	#include <asm/io.h>
	34
	35	#include <asm/sibyte/sb1250_regs.h>
	36	#include <asm/sibyte/sb1250_int.h>
	37	#include <asm/sibyte/sb1250_uart.h>
	38	#include <asm/sibyte/sb1250_scd.h>
	39	#include <asm/sibyte/sb1250.h>
	40
	41	/*
	42	* These are the routines that handle all the low level interrupt stuff.
	43	* Actions handled here are: initialization of the interrupt map, requesting of
	44	* interrupt lines by handlers, dispatching if interrupts to handlers, probing
	45	* for interrupt lines
	46	*/
	47
	48
	49	#define shutdown_sb1250_irq disable_sb1250_irq
	50	static void end_sb1250_irq(unsigned int irq);
	51	static void enable_sb1250_irq(unsigned int irq);
	52	static void disable_sb1250_irq(unsigned int irq);
	53	static unsigned int startup_sb1250_irq(unsigned int irq);
	54	static void ack_sb1250_irq(unsigned int irq);
	55	#ifdef CONFIG_SMP
942d042d	56	static void sb1250_set_affinity(unsigned int irq, cpumask_t mask);
1da177e4 LT	57	#endif
	58
	59	#ifdef CONFIG_SIBYTE_HAS_LDT
	60	extern unsigned long ldt_eoi_space;
	61	#endif
	62
	63	#ifdef CONFIG_KGDB
	64	static int kgdb_irq;
	65
	66	/* Default to UART1 */
	67	int kgdb_port = 1;
	68	#ifdef CONFIG_SIBYTE_SB1250_DUART
	69	extern char sb1250_duart_present[];
	70	#endif
	71	#endif
	72
	73	static struct hw_interrupt_type sb1250_irq_type = {
8ab00b9a RB	74	.typename = "SB1250-IMR",
	75	.startup = startup_sb1250_irq,
	76	.shutdown = shutdown_sb1250_irq,
	77	.enable = enable_sb1250_irq,
	78	.disable = disable_sb1250_irq,
	79	.ack = ack_sb1250_irq,
	80	.end = end_sb1250_irq,
1da177e4	81	#ifdef CONFIG_SMP
8ab00b9a	82	.set_affinity = sb1250_set_affinity
1da177e4 LT	83	#endif
	84	};
	85
	86	/* Store the CPU id (not the logical number) */
	87	int sb1250_irq_owner[SB1250_NR_IRQS];
	88
	89	DEFINE_SPINLOCK(sb1250_imr_lock);
	90
	91	void sb1250_mask_irq(int cpu, int irq)
	92	{
	93	unsigned long flags;
	94	u64 cur_ints;
	95
	96	spin_lock_irqsave(&sb1250_imr_lock, flags);
65bda1a9 MR	97	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	98	R_IMR_INTERRUPT_MASK));
1da177e4	99	cur_ints \|= (((u64) 1) << irq);
65bda1a9 MR	100	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	101	R_IMR_INTERRUPT_MASK));
1da177e4 LT	102	spin_unlock_irqrestore(&sb1250_imr_lock, flags);
	103	}
	104
	105	void sb1250_unmask_irq(int cpu, int irq)
	106	{
	107	unsigned long flags;
	108	u64 cur_ints;
	109
	110	spin_lock_irqsave(&sb1250_imr_lock, flags);
65bda1a9 MR	111	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	112	R_IMR_INTERRUPT_MASK));
1da177e4	113	cur_ints &= ~(((u64) 1) << irq);
65bda1a9 MR	114	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	115	R_IMR_INTERRUPT_MASK));
1da177e4 LT	116	spin_unlock_irqrestore(&sb1250_imr_lock, flags);
	117	}
	118
	119	#ifdef CONFIG_SMP
942d042d	120	static void sb1250_set_affinity(unsigned int irq, cpumask_t mask)
1da177e4 LT	121	{
	122	int i = 0, old_cpu, cpu, int_on;
	123	u64 cur_ints;
	124	irq_desc_t *desc = irq_desc + irq;
	125	unsigned long flags;
	126
942d042d	127	i = first_cpu(mask);
1da177e4	128
942d042d	129	if (cpus_weight(mask) > 1) {
1da177e4 LT	130	printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
	131	return;
	132	}
	133
	134	/* Convert logical CPU to physical CPU */
	135	cpu = cpu_logical_map(i);
	136
	137	/* Protect against other affinity changers and IMR manipulation */
	138	spin_lock_irqsave(&desc->lock, flags);
	139	spin_lock(&sb1250_imr_lock);
	140
	141	/* Swizzle each CPU's IMR (but leave the IP selection alone) */
	142	old_cpu = sb1250_irq_owner[irq];
65bda1a9 MR	143	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
65bda1a9 MR	144	R_IMR_INTERRUPT_MASK));
1da177e4 LT	145	int_on = !(cur_ints & (((u64) 1) << irq));
	146	if (int_on) {
	147	/* If it was on, mask it */
	148	cur_ints \|= (((u64) 1) << irq);
65bda1a9 MR	149	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
65bda1a9 MR	150	R_IMR_INTERRUPT_MASK));
1da177e4 LT	151	}
	152	sb1250_irq_owner[irq] = cpu;
	153	if (int_on) {
	154	/* unmask for the new CPU */
65bda1a9 MR	155	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	156	R_IMR_INTERRUPT_MASK));
1da177e4	157	cur_ints &= ~(((u64) 1) << irq);
65bda1a9 MR	158	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	159	R_IMR_INTERRUPT_MASK));
1da177e4 LT	160	}
	161	spin_unlock(&sb1250_imr_lock);
	162	spin_unlock_irqrestore(&desc->lock, flags);
	163	}
	164	#endif
	165
1da177e4 LT	166	/*****************************************************************************/
	167
	168	static unsigned int startup_sb1250_irq(unsigned int irq)
	169	{
	170	sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
	171
	172	return 0; /* never anything pending */
	173	}
	174
	175
	176	static void disable_sb1250_irq(unsigned int irq)
	177	{
	178	sb1250_mask_irq(sb1250_irq_owner[irq], irq);
	179	}
	180
	181	static void enable_sb1250_irq(unsigned int irq)
	182	{
	183	sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
	184	}
	185
	186
	187	static void ack_sb1250_irq(unsigned int irq)
	188	{
	189	#ifdef CONFIG_SIBYTE_HAS_LDT
	190	u64 pending;
	191
	192	/*
	193	* If the interrupt was an HT interrupt, now is the time to
	194	* clear it. NOTE: we assume the HT bridge was set up to
	195	* deliver the interrupts to all CPUs (which makes affinity
	196	* changing easier for us)
	197	*/
65bda1a9 MR	198	pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
65bda1a9 MR	199	R_IMR_LDT_INTERRUPT)));
1da177e4 LT	200	pending &= ((u64)1 << (irq));
	201	if (pending) {
	202	int i;
	203	for (i=0; i<NR_CPUS; i++) {
	204	int cpu;
	205	#ifdef CONFIG_SMP
	206	cpu = cpu_logical_map(i);
	207	#else
	208	cpu = i;
	209	#endif
	210	/*
	211	* Clear for all CPUs so an affinity switch
	212	* doesn't find an old status
	213	*/
65bda1a9 MR	214	__raw_writeq(pending,
65bda1a9 MR	215	IOADDR(A_IMR_REGISTER(cpu,
1da177e4 LT	216	R_IMR_LDT_INTERRUPT_CLR)));
	217	}
	218
	219	/*
	220	* Generate EOI. For Pass 1 parts, EOI is a nop. For
	221	* Pass 2, the LDT world may be edge-triggered, but
	222	* this EOI shouldn't hurt. If they are
	223	* level-sensitive, the EOI is required.
	224	*/
	225	(uint32_t )(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
	226	}
	227	#endif
	228	sb1250_mask_irq(sb1250_irq_owner[irq], irq);
	229	}
	230
	231
	232	static void end_sb1250_irq(unsigned int irq)
	233	{
	234	if (!(irq_desc[irq].status & (IRQ_DISABLED \| IRQ_INPROGRESS))) {
	235	sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
	236	}
	237	}
	238
	239
	240	void __init init_sb1250_irqs(void)
	241	{
	242	int i;
	243
	244	for (i = 0; i < NR_IRQS; i++) {
	245	irq_desc[i].status = IRQ_DISABLED;
	246	irq_desc[i].action = 0;
	247	irq_desc[i].depth = 1;
	248	if (i < SB1250_NR_IRQS) {
	249	irq_desc[i].handler = &sb1250_irq_type;
	250	sb1250_irq_owner[i] = 0;
	251	} else {
	252	irq_desc[i].handler = &no_irq_type;
	253	}
	254	}
	255	}
	256
	257
	258	static irqreturn_t sb1250_dummy_handler(int irq, void *dev_id,
	259	struct pt_regs *regs)
	260	{
	261	return IRQ_NONE;
	262	}
	263
	264	static struct irqaction sb1250_dummy_action = {
	265	.handler = sb1250_dummy_handler,
	266	.flags = 0,
	267	.mask = CPU_MASK_NONE,
	268	.name = "sb1250-private",
	269	.next = NULL,
	270	.dev_id = 0
	271	};
	272
	273	int sb1250_steal_irq(int irq)
	274	{
	275	irq_desc_t *desc = irq_desc + irq;
	276	unsigned long flags;
	277	int retval = 0;
	278
	279	if (irq >= SB1250_NR_IRQS)
280	return -EINVAL;
281
282	spin_lock_irqsave(&desc->lock,flags);
283	/* Don't allow sharing at all for these */
284	if (desc->action != NULL)
285	retval = -EBUSY;
286	else {
287	desc->action = &sb1250_dummy_action;
288	desc->depth = 0;
289	}
290	spin_unlock_irqrestore(&desc->lock,flags);
291	return 0;
292	}
293
294	/*
295	* arch_init_irq is called early in the boot sequence from init/main.c via
296	* init_IRQ. It is responsible for setting up the interrupt mapper and
297	* installing the handler that will be responsible for dispatching interrupts
298	* to the "right" place.
299	*/
300	/*
301	* For now, map all interrupts to IP[2]. We could save
302	* some cycles by parceling out system interrupts to different
303	* IP lines, but keep it simple for bringup. We'll also direct
304	* all interrupts to a single CPU; we should probably route
305	* PCI and LDT to one cpu and everything else to the other
306	* to balance the load a bit.
307	*
308	* On the second cpu, everything is set to IP5, which is
309	* ignored, EXCEPT the mailbox interrupt. That one is
310	* set to IP[2] so it is handled. This is needed so we
311	* can do cross-cpu function calls, as requred by SMP
312	*/
313
314	#define IMR_IP2_VAL K_INT_MAP_I0
315	#define IMR_IP3_VAL K_INT_MAP_I1
316	#define IMR_IP4_VAL K_INT_MAP_I2
317	#define IMR_IP5_VAL K_INT_MAP_I3
318	#define IMR_IP6_VAL K_INT_MAP_I4
319
320	void __init arch_init_irq(void)
321	{
322
323	unsigned int i;
324	u64 tmp;
325	unsigned int imask = STATUSF_IP4 \| STATUSF_IP3 \| STATUSF_IP2 \|
326	STATUSF_IP1 \| STATUSF_IP0;
327
328	/* Default everything to IP2 */
329	for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
65bda1a9 MR	330	__raw_writeq(IMR_IP2_VAL,
	331	IOADDR(A_IMR_REGISTER(0,
	332	R_IMR_INTERRUPT_MAP_BASE) +
	333	(i << 3)));
	334	__raw_writeq(IMR_IP2_VAL,
	335	IOADDR(A_IMR_REGISTER(1,
	336	R_IMR_INTERRUPT_MAP_BASE) +
	337	(i << 3)));
1da177e4 LT	338	}
	339
	340	init_sb1250_irqs();
	341
	342	/*
	343	* Map the high 16 bits of the mailbox registers to IP[3], for
	344	* inter-cpu messages
	345	*/
	346	/* Was I1 */
65bda1a9 MR	347	__raw_writeq(IMR_IP3_VAL,
	348	IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
	349	(K_INT_MBOX_0 << 3)));
	350	__raw_writeq(IMR_IP3_VAL,
	351	IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
	352	(K_INT_MBOX_0 << 3)));
1da177e4 LT	353
1da177e4 LT	354	/* Clear the mailboxes. The firmware may leave them dirty */
65bda1a9 MR	355	__raw_writeq(0xffffffffffffffffULL,
	356	IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
	357	__raw_writeq(0xffffffffffffffffULL,
	358	IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
1da177e4 LT	359
	360	/* Mask everything except the mailbox registers for both cpus */
	361	tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
65bda1a9 MR	362	__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
65bda1a9 MR	363	__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
1da177e4 LT	364
	365	sb1250_steal_irq(K_INT_MBOX_0);
	366
	367	/*
	368	* Note that the timer interrupts are also mapped, but this is
42a3b4f2	369	* done in sb1250_time_init(). Also, the profiling driver
1da177e4 LT	370	* does its own management of IP7.
	371	*/
	372
	373	#ifdef CONFIG_KGDB
	374	imask \|= STATUSF_IP6;
	375	#endif
	376	/* Enable necessary IPs, disable the rest */
	377	change_c0_status(ST0_IM, imask);
1da177e4 LT	378
	379	#ifdef CONFIG_KGDB
	380	if (kgdb_flag) {
	381	kgdb_irq = K_INT_UART_0 + kgdb_port;
	382
42a3b4f2	383	#ifdef CONFIG_SIBYTE_SB1250_DUART
1da177e4 LT	384	sb1250_duart_present[kgdb_port] = 0;
	385	#endif
	386	/* Setup uart 1 settings, mapper */
65bda1a9 MR	387	__raw_writeq(M_DUART_IMR_BRK,
65bda1a9 MR	388	IOADDR(A_DUART_IMRREG(kgdb_port)));
1da177e4 LT	389
1da177e4 LT	390	sb1250_steal_irq(kgdb_irq);
65bda1a9 MR	391	__raw_writeq(IMR_IP6_VAL,
	392	IOADDR(A_IMR_REGISTER(0,
	393	R_IMR_INTERRUPT_MAP_BASE) +
	394	(kgdb_irq << 3)));
1da177e4 LT	395	sb1250_unmask_irq(0, kgdb_irq);
	396	}
	397	#endif
	398	}
	399
	400	#ifdef CONFIG_KGDB
	401
	402	#include <linux/delay.h>
	403
	404	#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
	405	#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
	406
e4ac58af	407	static void sb1250_kgdb_interrupt(struct pt_regs *regs)
1da177e4 LT	408	{
	409	/*
	410	* Clear break-change status (allow some time for the remote
	411	* host to stop the break, since we would see another
	412	* interrupt on the end-of-break too)
	413	*/
	414	kstat_this_cpu.irqs[kgdb_irq]++;
	415	mdelay(500);
	416	duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT \|
	417	M_DUART_RX_EN \| M_DUART_TX_EN);
	418	set_async_breakpoint(&regs->cp0_epc);
	419	}
	420
	421	#endif /* CONFIG_KGDB */
e4ac58af RB	422
	423	static inline int dclz(unsigned long long x)
	424	{
	425	int lz;
	426
	427	__asm__ (
	428	" .set push \n"
	429	" .set mips64 \n"
	430	" dclz %0, %1 \n"
	431	" .set pop \n"
	432	: "=r" (lz)
	433	: "r" (x));
	434
	435	return lz;
	436	}
	437
	438	asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
	439	{
	440	unsigned int pending;
	441
	442	#ifdef CONFIG_SIBYTE_SB1250_PROF
	443	/* Set compare to count to silence count/compare timer interrupts */
	444	write_c0_count(read_c0_count());
	445	#endif
	446
	447	/*
	448	* What a pain. We have to be really careful saving the upper 32 bits
	449	* of any * register across function calls if we don't want them
	450	* trashed--since were running in -o32, the calling routing never saves
	451	* the full 64 bits of a register across a function call. Being the
	452	* interrupt handler, we're guaranteed that interrupts are disabled
	453	* during this code so we don't have to worry about random interrupts
	454	* blasting the high 32 bits.
	455	*/
	456
	457	pending = read_c0_cause();
	458
	459	#ifdef CONFIG_SIBYTE_SB1250_PROF
	460	if (pending & CAUSEF_IP7) { /* Cpu performance counter interrupt */
	461	sbprof_cpu_intr(exception_epc(regs));
	462	}
	463	#endif
	464
	465	if (pending & CAUSEF_IP4)
	466	sb1250_timer_interrupt(regs);
	467
	468	#ifdef CONFIG_SMP
	469	if (pending & CAUSEF_IP3)
	470	sb1250_mailbox_interrupt(regs);
	471	#endif
	472
	473	#ifdef CONFIG_KGDB
	474	if (pending & CAUSEF_IP6) /* KGDB (uart 1) */
	475	sb1250_kgdb_interrupt(regs);
	476	#endif
	477
	478	if (pending & CAUSEF_IP2) {
	479	unsigned long long mask;
	480
	481	/*
	482	* Default...we've hit an IP[2] interrupt, which means we've
	483	* got to check the 1250 interrupt registers to figure out what
	484	* to do. Need to detect which CPU we're on, now that
	485	~ smp_affinity is supported.
486	*/
487	mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(),
488	R_IMR_INTERRUPT_STATUS_BASE)));
489	if (mask)
490	do_IRQ(63 - dclz(mask), regs);
491	}
492	}