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Merge branches 'irq-core-for-linus' and 'core-locking-for-linus' of git://git.kernel...
[net-next-2.6.git] / arch / mips / pci / pcie-octeon.c
CommitLineData
e8635b48
DD		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007, 2008 Cavium Networks
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/interrupt.h>
12#include <linux/time.h>
13#include <linux/delay.h>
14
15#include <asm/octeon/octeon.h>
16#include <asm/octeon/cvmx-npei-defs.h>
17#include <asm/octeon/cvmx-pciercx-defs.h>
18#include <asm/octeon/cvmx-pescx-defs.h>
19#include <asm/octeon/cvmx-pexp-defs.h>
20#include <asm/octeon/cvmx-helper-errata.h>
01a6221a 21#include <asm/octeon/pci-octeon.h>
e8635b48
DD		 22
23union cvmx_pcie_address {
24 uint64_t u64;
25 struct {
26 uint64_t upper:2; /* Normally 2 for XKPHYS */
27 uint64_t reserved_49_61:13; /* Must be zero */
28 uint64_t io:1; /* 1 for IO space access */
29 uint64_t did:5; /* PCIe DID = 3 */
30 uint64_t subdid:3; /* PCIe SubDID = 1 */
31 uint64_t reserved_36_39:4; /* Must be zero */
32 uint64_t es:2; /* Endian swap = 1 */
33 uint64_t port:2; /* PCIe port 0,1 */
34 uint64_t reserved_29_31:3; /* Must be zero */
35 /*
36 * Selects the type of the configuration request (0 = type 0,
37 * 1 = type 1).
38 */
39 uint64_t ty:1;
40 /* Target bus number sent in the ID in the request. */
41 uint64_t bus:8;
42 /*
43 * Target device number sent in the ID in the
44 * request. Note that Dev must be zero for type 0
45 * configuration requests.
46 */
47 uint64_t dev:5;
48 /* Target function number sent in the ID in the request. */
49 uint64_t func:3;
50 /*
51 * Selects a register in the configuration space of
52 * the target.
53 */
54 uint64_t reg:12;
55 } config;
56 struct {
57 uint64_t upper:2; /* Normally 2 for XKPHYS */
58 uint64_t reserved_49_61:13; /* Must be zero */
59 uint64_t io:1; /* 1 for IO space access */
60 uint64_t did:5; /* PCIe DID = 3 */
61 uint64_t subdid:3; /* PCIe SubDID = 2 */
62 uint64_t reserved_36_39:4; /* Must be zero */
63 uint64_t es:2; /* Endian swap = 1 */
64 uint64_t port:2; /* PCIe port 0,1 */
65 uint64_t address:32; /* PCIe IO address */
66 } io;
67 struct {
68 uint64_t upper:2; /* Normally 2 for XKPHYS */
69 uint64_t reserved_49_61:13; /* Must be zero */
70 uint64_t io:1; /* 1 for IO space access */
71 uint64_t did:5; /* PCIe DID = 3 */
72 uint64_t subdid:3; /* PCIe SubDID = 3-6 */
73 uint64_t reserved_36_39:4; /* Must be zero */
74 uint64_t address:36; /* PCIe Mem address */
75 } mem;
76};
77
b93b2abc
DD		 78#include <dma-coherence.h>
79
e8635b48
DD		 80/**
81 * Return the Core virtual base address for PCIe IO access. IOs are
82 * read/written as an offset from this address.
83 *
84 * @pcie_port: PCIe port the IO is for
85 *
86 * Returns 64bit Octeon IO base address for read/write
87 */
88static inline uint64_t cvmx_pcie_get_io_base_address(int pcie_port)
89{
90 union cvmx_pcie_address pcie_addr;
91 pcie_addr.u64 = 0;
92 pcie_addr.io.upper = 0;
93 pcie_addr.io.io = 1;
94 pcie_addr.io.did = 3;
95 pcie_addr.io.subdid = 2;
96 pcie_addr.io.es = 1;
97 pcie_addr.io.port = pcie_port;
98 return pcie_addr.u64;
99}
100
101/**
102 * Size of the IO address region returned at address
103 * cvmx_pcie_get_io_base_address()
104 *
105 * @pcie_port: PCIe port the IO is for
106 *
107 * Returns Size of the IO window
108 */
109static inline uint64_t cvmx_pcie_get_io_size(int pcie_port)
110{
111 return 1ull << 32;
112}
113
114/**
115 * Return the Core virtual base address for PCIe MEM access. Memory is
116 * read/written as an offset from this address.
117 *
118 * @pcie_port: PCIe port the IO is for
119 *
120 * Returns 64bit Octeon IO base address for read/write
121 */
122static inline uint64_t cvmx_pcie_get_mem_base_address(int pcie_port)
123{
124 union cvmx_pcie_address pcie_addr;
125 pcie_addr.u64 = 0;
126 pcie_addr.mem.upper = 0;
127 pcie_addr.mem.io = 1;
128 pcie_addr.mem.did = 3;
129 pcie_addr.mem.subdid = 3 + pcie_port;
130 return pcie_addr.u64;
131}
132
133/**
134 * Size of the Mem address region returned at address
135 * cvmx_pcie_get_mem_base_address()
136 *
137 * @pcie_port: PCIe port the IO is for
138 *
139 * Returns Size of the Mem window
140 */
141static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port)
142{
143 return 1ull << 36;
144}
145
146/**
147 * Read a PCIe config space register indirectly. This is used for
148 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
149 *
150 * @pcie_port: PCIe port to read from
151 * @cfg_offset: Address to read
152 *
153 * Returns Value read
154 */
155static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
156{
157 union cvmx_pescx_cfg_rd pescx_cfg_rd;
158 pescx_cfg_rd.u64 = 0;
159 pescx_cfg_rd.s.addr = cfg_offset;
160 cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
161 pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
162 return pescx_cfg_rd.s.data;
163}
164
165/**
166 * Write a PCIe config space register indirectly. This is used for
167 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
168 *
169 * @pcie_port: PCIe port to write to
170 * @cfg_offset: Address to write
171 * @val: Value to write
172 */
173static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
174 uint32_t val)
175{
176 union cvmx_pescx_cfg_wr pescx_cfg_wr;
177 pescx_cfg_wr.u64 = 0;
178 pescx_cfg_wr.s.addr = cfg_offset;
179 pescx_cfg_wr.s.data = val;
180 cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
181}
182
183/**
184 * Build a PCIe config space request address for a device
185 *
186 * @pcie_port: PCIe port to access
187 * @bus: Sub bus
188 * @dev: Device ID
189 * @fn: Device sub function
190 * @reg: Register to access
191 *
192 * Returns 64bit Octeon IO address
193 */
194static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus,
195 int dev, int fn, int reg)
196{
197 union cvmx_pcie_address pcie_addr;
198 union cvmx_pciercx_cfg006 pciercx_cfg006;
199
200 pciercx_cfg006.u32 =
201 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port));
202 if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0))
203 return 0;
204
205 pcie_addr.u64 = 0;
206 pcie_addr.config.upper = 2;
207 pcie_addr.config.io = 1;
208 pcie_addr.config.did = 3;
209 pcie_addr.config.subdid = 1;
210 pcie_addr.config.es = 1;
211 pcie_addr.config.port = pcie_port;
212 pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum);
213 pcie_addr.config.bus = bus;
214 pcie_addr.config.dev = dev;
215 pcie_addr.config.func = fn;
216 pcie_addr.config.reg = reg;
217 return pcie_addr.u64;
218}
219
220/**
221 * Read 8bits from a Device's config space
222 *
223 * @pcie_port: PCIe port the device is on
224 * @bus: Sub bus
225 * @dev: Device ID
226 * @fn: Device sub function
227 * @reg: Register to access
228 *
229 * Returns Result of the read
230 */
231static uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev,
232 int fn, int reg)
233{
234 uint64_t address =
235 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
236 if (address)
237 return cvmx_read64_uint8(address);
238 else
239 return 0xff;
240}
241
242/**
243 * Read 16bits from a Device's config space
244 *
245 * @pcie_port: PCIe port the device is on
246 * @bus: Sub bus
247 * @dev: Device ID
248 * @fn: Device sub function
249 * @reg: Register to access
250 *
251 * Returns Result of the read
252 */
253static uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev,
254 int fn, int reg)
255{
256 uint64_t address =
257 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
258 if (address)
259 return le16_to_cpu(cvmx_read64_uint16(address));
260 else
261 return 0xffff;
262}
263
264/**
265 * Read 32bits from a Device's config space
266 *
267 * @pcie_port: PCIe port the device is on
268 * @bus: Sub bus
269 * @dev: Device ID
270 * @fn: Device sub function
271 * @reg: Register to access
272 *
273 * Returns Result of the read
274 */
275static uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev,
276 int fn, int reg)
277{
278 uint64_t address =
279 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
280 if (address)
281 return le32_to_cpu(cvmx_read64_uint32(address));
282 else
283 return 0xffffffff;
284}
285
286/**
287 * Write 8bits to a Device's config space
288 *
289 * @pcie_port: PCIe port the device is on
290 * @bus: Sub bus
291 * @dev: Device ID
292 * @fn: Device sub function
293 * @reg: Register to access
294 * @val: Value to write
295 */
296static void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn,
297 int reg, uint8_t val)
298{
299 uint64_t address =
300 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
301 if (address)
302 cvmx_write64_uint8(address, val);
303}
304
305/**
306 * Write 16bits to a Device's config space
307 *
308 * @pcie_port: PCIe port the device is on
309 * @bus: Sub bus
310 * @dev: Device ID
311 * @fn: Device sub function
312 * @reg: Register to access
313 * @val: Value to write
314 */
315static void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn,
316 int reg, uint16_t val)
317{
318 uint64_t address =
319 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
320 if (address)
321 cvmx_write64_uint16(address, cpu_to_le16(val));
322}
323
324/**
325 * Write 32bits to a Device's config space
326 *
327 * @pcie_port: PCIe port the device is on
328 * @bus: Sub bus
329 * @dev: Device ID
330 * @fn: Device sub function
331 * @reg: Register to access
332 * @val: Value to write
333 */
334static void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn,
335 int reg, uint32_t val)
336{
337 uint64_t address =
338 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
339 if (address)
340 cvmx_write64_uint32(address, cpu_to_le32(val));
341}
342
343/**
344 * Initialize the RC config space CSRs
345 *
346 * @pcie_port: PCIe port to initialize
347 */
348static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
349{
350 union cvmx_pciercx_cfg030 pciercx_cfg030;
351 union cvmx_npei_ctl_status2 npei_ctl_status2;
352 union cvmx_pciercx_cfg070 pciercx_cfg070;
353 union cvmx_pciercx_cfg001 pciercx_cfg001;
354 union cvmx_pciercx_cfg032 pciercx_cfg032;
355 union cvmx_pciercx_cfg006 pciercx_cfg006;
356 union cvmx_pciercx_cfg008 pciercx_cfg008;
357 union cvmx_pciercx_cfg009 pciercx_cfg009;
358 union cvmx_pciercx_cfg010 pciercx_cfg010;
359 union cvmx_pciercx_cfg011 pciercx_cfg011;
360 union cvmx_pciercx_cfg035 pciercx_cfg035;
361 union cvmx_pciercx_cfg075 pciercx_cfg075;
362 union cvmx_pciercx_cfg034 pciercx_cfg034;
363
364 /* Max Payload Size (PCIE*_CFG030[MPS]) */
365 /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
366 /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
367 /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
368 pciercx_cfg030.u32 =
369 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
370 /*
371 * Max payload size = 128 bytes for best Octeon DMA
372 * performance.
373 */
374 pciercx_cfg030.s.mps = 0;
375 /*
376 * Max read request size = 128 bytes for best Octeon DMA
377 * performance.
378 */
379 pciercx_cfg030.s.mrrs = 0;
380 /* Enable relaxed ordering. */
381 pciercx_cfg030.s.ro_en = 1;
382 /* Enable no snoop. */
383 pciercx_cfg030.s.ns_en = 1;
384 /* Correctable error reporting enable. */
385 pciercx_cfg030.s.ce_en = 1;
386 /* Non-fatal error reporting enable. */
387 pciercx_cfg030.s.nfe_en = 1;
388 /* Fatal error reporting enable. */
389 pciercx_cfg030.s.fe_en = 1;
390 /* Unsupported request reporting enable. */
391 pciercx_cfg030.s.ur_en = 1;
392 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port),
393 pciercx_cfg030.u32);
394
395 /*
396 * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
397 * PCIE*_CFG030[MPS]
398 *
399 * Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not
400 * exceed PCIE*_CFG030[MRRS].
401 */
402 npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
403 /* Max payload size = 128 bytes for best Octeon DMA performance */
404 npei_ctl_status2.s.mps = 0;
405 /* Max read request size = 128 bytes for best Octeon DMA performance */
406 npei_ctl_status2.s.mrrs = 0;
2b5987ab
DD		 407 if (pcie_port)
408 npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */
409 else
410 npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */
e8635b48
DD		 411 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
412
413 /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
414 pciercx_cfg070.u32 =
415 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
416 pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */
417 pciercx_cfg070.s.ce = 1; /* ECRC check enable. */
418 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port),
419 pciercx_cfg070.u32);
420
421 /*
422 * Access Enables (PCIE*_CFG001[MSAE,ME]) ME and MSAE should
423 * always be set.
424 *
425 * Interrupt Disable (PCIE*_CFG001[I_DIS]) System Error
426 * Message Enable (PCIE*_CFG001[SEE])
427 */
428 pciercx_cfg001.u32 =
429 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
430 pciercx_cfg001.s.msae = 1; /* Memory space enable. */
431 pciercx_cfg001.s.me = 1; /* Bus master enable. */
432 pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */
433 pciercx_cfg001.s.see = 1; /* SERR# enable */
434 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port),
435 pciercx_cfg001.u32);
436
437 /* Advanced Error Recovery Message Enables */
438 /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
439 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG066(pcie_port), 0);
440 /* Use CVMX_PCIERCX_CFG067 hardware default */
441 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);
442
443 /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
444 pciercx_cfg032.u32 =
445 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
446 pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
447 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port),
448 pciercx_cfg032.u32);
449
450 /* Entrance Latencies (PCIE*_CFG451[L0EL,L1EL]) */
451
452 /*
453 * Link Width Mode (PCIERCn_CFG452[LME]) - Set during
454 * cvmx_pcie_rc_initialize_link()
455 *
456 * Primary Bus Number (PCIERCn_CFG006[PBNUM])
457 *
458 * We set the primary bus number to 1 so IDT bridges are
459 * happy. They don't like zero.
460 */
461 pciercx_cfg006.u32 = 0;
462 pciercx_cfg006.s.pbnum = 1;
463 pciercx_cfg006.s.sbnum = 1;
464 pciercx_cfg006.s.subbnum = 1;
465 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port),
466 pciercx_cfg006.u32);
467
468 /*
469 * Memory-mapped I/O BAR (PCIERCn_CFG008)
470 * Most applications should disable the memory-mapped I/O BAR by
471 * setting PCIERCn_CFG008[ML_ADDR] < PCIERCn_CFG008[MB_ADDR]
472 */
473 pciercx_cfg008.u32 = 0;
474 pciercx_cfg008.s.mb_addr = 0x100;
475 pciercx_cfg008.s.ml_addr = 0;
476 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port),
477 pciercx_cfg008.u32);
478
479 /*
480 * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011)
481 * Most applications should disable the prefetchable BAR by setting
482 * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] <
483 * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE]
484 */
485 pciercx_cfg009.u32 =
486 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
487 pciercx_cfg010.u32 =
488 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
489 pciercx_cfg011.u32 =
490 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
491 pciercx_cfg009.s.lmem_base = 0x100;
492 pciercx_cfg009.s.lmem_limit = 0;
493 pciercx_cfg010.s.umem_base = 0x100;
494 pciercx_cfg011.s.umem_limit = 0;
495 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port),
496 pciercx_cfg009.u32);
497 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port),
498 pciercx_cfg010.u32);
499 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port),
500 pciercx_cfg011.u32);
501
502 /*
503 * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE])
504 * PME Interrupt Enables (PCIERCn_CFG035[PMEIE])
505 */
506 pciercx_cfg035.u32 =
507 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
508 /* System error on correctable error enable. */
509 pciercx_cfg035.s.secee = 1;
510 /* System error on fatal error enable. */
511 pciercx_cfg035.s.sefee = 1;
512 /* System error on non-fatal error enable. */
513 pciercx_cfg035.s.senfee = 1;
514 /* PME interrupt enable. */
515 pciercx_cfg035.s.pmeie = 1;
516 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port),
517 pciercx_cfg035.u32);
518
519 /*
520 * Advanced Error Recovery Interrupt Enables
521 * (PCIERCn_CFG075[CERE,NFERE,FERE])
522 */
523 pciercx_cfg075.u32 =
524 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
525 /* Correctable error reporting enable. */
526 pciercx_cfg075.s.cere = 1;
527 /* Non-fatal error reporting enable. */
528 pciercx_cfg075.s.nfere = 1;
529 /* Fatal error reporting enable. */
530 pciercx_cfg075.s.fere = 1;
531 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port),
532 pciercx_cfg075.u32);
533
534 /* HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
535 * PCIERCn_CFG034[DLLS_EN,CCINT_EN])
536 */
537 pciercx_cfg034.u32 =
538 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
539 /* Hot-plug interrupt enable. */
540 pciercx_cfg034.s.hpint_en = 1;
541 /* Data Link Layer state changed enable */
542 pciercx_cfg034.s.dlls_en = 1;
543 /* Command completed interrupt enable. */
544 pciercx_cfg034.s.ccint_en = 1;
545 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port),
546 pciercx_cfg034.u32);
547}
548
549/**
550 * Initialize a host mode PCIe link. This function takes a PCIe
551 * port from reset to a link up state. Software can then begin
552 * configuring the rest of the link.
553 *
554 * @pcie_port: PCIe port to initialize
555 *
556 * Returns Zero on success
557 */
558static int __cvmx_pcie_rc_initialize_link(int pcie_port)
559{
560 uint64_t start_cycle;
561 union cvmx_pescx_ctl_status pescx_ctl_status;
562 union cvmx_pciercx_cfg452 pciercx_cfg452;
563 union cvmx_pciercx_cfg032 pciercx_cfg032;
564 union cvmx_pciercx_cfg448 pciercx_cfg448;
565
566 /* Set the lane width */
567 pciercx_cfg452.u32 =
568 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
569 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
570 if (pescx_ctl_status.s.qlm_cfg == 0) {
571 /* We're in 8 lane (56XX) or 4 lane (54XX) mode */
572 pciercx_cfg452.s.lme = 0xf;
573 } else {
574 /* We're in 4 lane (56XX) or 2 lane (52XX) mode */
575 pciercx_cfg452.s.lme = 0x7;
576 }
577 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port),
578 pciercx_cfg452.u32);
579
580 /*
581 * CN52XX pass 1.x has an errata where length mismatches on UR
582 * responses can cause bus errors on 64bit memory
583 * reads. Turning off length error checking fixes this.
584 */
585 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
586 union cvmx_pciercx_cfg455 pciercx_cfg455;
587 pciercx_cfg455.u32 =
588 cvmx_pcie_cfgx_read(pcie_port,
589 CVMX_PCIERCX_CFG455(pcie_port));
590 pciercx_cfg455.s.m_cpl_len_err = 1;
591 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port),
592 pciercx_cfg455.u32);
593 }
594
595 /* Lane swap needs to be manually enabled for CN52XX */
596 if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) {
597 pescx_ctl_status.s.lane_swp = 1;
598 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port),
599 pescx_ctl_status.u64);
600 }
601
602 /* Bring up the link */
603 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
604 pescx_ctl_status.s.lnk_enb = 1;
605 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
606
607 /*
608 * CN52XX pass 1.0: Due to a bug in 2nd order CDR, it needs to
609 * be disabled.
610 */
611 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0))
612 __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0);
613
614 /* Wait for the link to come up */
615 cvmx_dprintf("PCIe: Waiting for port %d link\n", pcie_port);
616 start_cycle = cvmx_get_cycle();
617 do {
618 if (cvmx_get_cycle() - start_cycle >
619 2 * cvmx_sysinfo_get()->cpu_clock_hz) {
620 cvmx_dprintf("PCIe: Port %d link timeout\n",
621 pcie_port);
622 return -1;
623 }
624 cvmx_wait(10000);
625 pciercx_cfg032.u32 =
626 cvmx_pcie_cfgx_read(pcie_port,
627 CVMX_PCIERCX_CFG032(pcie_port));
628 } while (pciercx_cfg032.s.dlla == 0);
629
630 /* Display the link status */
631 cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port,
632 pciercx_cfg032.s.nlw);
633
634 /*
635 * Update the Replay Time Limit. Empirically, some PCIe
636 * devices take a little longer to respond than expected under
637 * load. As a workaround for this we configure the Replay Time
638 * Limit to the value expected for a 512 byte MPS instead of
639 * our actual 256 byte MPS. The numbers below are directly
640 * from the PCIe spec table 3-4.
641 */
642 pciercx_cfg448.u32 =
643 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
644 switch (pciercx_cfg032.s.nlw) {
645 case 1: /* 1 lane */
646 pciercx_cfg448.s.rtl = 1677;
647 break;
648 case 2: /* 2 lanes */
649 pciercx_cfg448.s.rtl = 867;
650 break;
651 case 4: /* 4 lanes */
652 pciercx_cfg448.s.rtl = 462;
653 break;
654 case 8: /* 8 lanes */
655 pciercx_cfg448.s.rtl = 258;
656 break;
657 }
658 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port),
659 pciercx_cfg448.u32);
660
661 return 0;
662}
663
664/**
665 * Initialize a PCIe port for use in host(RC) mode. It doesn't
666 * enumerate the bus.
667 *
668 * @pcie_port: PCIe port to initialize
669 *
670 * Returns Zero on success
671 */
672static int cvmx_pcie_rc_initialize(int pcie_port)
673{
674 int i;
2b5987ab
DD		 675 int base;
676 u64 addr_swizzle;
e8635b48
DD		 677 union cvmx_ciu_soft_prst ciu_soft_prst;
678 union cvmx_pescx_bist_status pescx_bist_status;
679 union cvmx_pescx_bist_status2 pescx_bist_status2;
680 union cvmx_npei_ctl_status npei_ctl_status;
681 union cvmx_npei_mem_access_ctl npei_mem_access_ctl;
682 union cvmx_npei_mem_access_subidx mem_access_subid;
683 union cvmx_npei_dbg_data npei_dbg_data;
684 union cvmx_pescx_ctl_status2 pescx_ctl_status2;
2b5987ab 685 union cvmx_npei_bar1_indexx bar1_index;
e8635b48
DD		 686
687 /*
688 * Make sure we aren't trying to setup a target mode interface
689 * in host mode.
690 */
691 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
692 if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) {
693 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called "
694 "on port0, but port0 is not in host mode\n");
695 return -1;
696 }
697
698 /*
699 * Make sure a CN52XX isn't trying to bring up port 1 when it
700 * is disabled.
701 */
702 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
703 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
704 if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) {
705 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() "
706 "called on port1, but port1 is "
707 "disabled\n");
708 return -1;
709 }
710 }
711
712 /*
713 * PCIe switch arbitration mode. '0' == fixed priority NPEI,
714 * PCIe0, then PCIe1. '1' == round robin.
715 */
716 npei_ctl_status.s.arb = 1;
717 /* Allow up to 0x20 config retries */
718 npei_ctl_status.s.cfg_rtry = 0x20;
719 /*
720 * CN52XX pass1.x has an errata where P0_NTAGS and P1_NTAGS
721 * don't reset.
722 */
723 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
724 npei_ctl_status.s.p0_ntags = 0x20;
725 npei_ctl_status.s.p1_ntags = 0x20;
726 }
727 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS, npei_ctl_status.u64);
728
729 /* Bring the PCIe out of reset */
730 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) {
731 /*
732 * The EBH5200 board swapped the PCIe reset lines on
733 * the board. As a workaround for this bug, we bring
734 * both PCIe ports out of reset at the same time
735 * instead of on separate calls. So for port 0, we
736 * bring both out of reset and do nothing on port 1.
737 */
738 if (pcie_port == 0) {
739 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
740 /*
741 * After a chip reset the PCIe will also be in
742 * reset. If it isn't, most likely someone is
743 * trying to init it again without a proper
744 * PCIe reset.
745 */
746 if (ciu_soft_prst.s.soft_prst == 0) {
747 /* Reset the ports */
748 ciu_soft_prst.s.soft_prst = 1;
749 cvmx_write_csr(CVMX_CIU_SOFT_PRST,
750 ciu_soft_prst.u64);
751 ciu_soft_prst.u64 =
752 cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
753 ciu_soft_prst.s.soft_prst = 1;
754 cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
755 ciu_soft_prst.u64);
756 /* Wait until pcie resets the ports. */
757 udelay(2000);
758 }
759 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
760 ciu_soft_prst.s.soft_prst = 0;
761 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
762 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
763 ciu_soft_prst.s.soft_prst = 0;
764 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
765 }
766 } else {
767 /*
768 * The normal case: The PCIe ports are completely
769 * separate and can be brought out of reset
770 * independently.
771 */
772 if (pcie_port)
773 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
774 else
775 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
776 /*
777 * After a chip reset the PCIe will also be in
778 * reset. If it isn't, most likely someone is trying
779 * to init it again without a proper PCIe reset.
780 */
781 if (ciu_soft_prst.s.soft_prst == 0) {
782 /* Reset the port */
783 ciu_soft_prst.s.soft_prst = 1;
784 if (pcie_port)
785 cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
786 ciu_soft_prst.u64);
787 else
788 cvmx_write_csr(CVMX_CIU_SOFT_PRST,
789 ciu_soft_prst.u64);
790 /* Wait until pcie resets the ports. */
791 udelay(2000);
792 }
793 if (pcie_port) {
794 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
795 ciu_soft_prst.s.soft_prst = 0;
796 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
797 } else {
798 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
799 ciu_soft_prst.s.soft_prst = 0;
800 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
801 }
802 }
803
804 /*
805 * Wait for PCIe reset to complete. Due to errata PCIE-700, we
806 * don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a
807 * fixed number of cycles.
808 */
809 cvmx_wait(400000);
810
811 /* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of CN56XX and
812 CN52XX, so we only probe it on newer chips */
813 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
814 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
815 /* Clear PCLK_RUN so we can check if the clock is running */
816 pescx_ctl_status2.u64 =
817 cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
818 pescx_ctl_status2.s.pclk_run = 1;
819 cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port),
820 pescx_ctl_status2.u64);
821 /*
822 * Now that we cleared PCLK_RUN, wait for it to be set
823 * again telling us the clock is running.
824 */
825 if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port),
826 union cvmx_pescx_ctl_status2,
827 pclk_run, ==, 1, 10000)) {
828 cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n",
829 pcie_port);
830 return -1;
831 }
832 }
833
834 /*
835 * Check and make sure PCIe came out of reset. If it doesn't
836 * the board probably hasn't wired the clocks up and the
837 * interface should be skipped.
838 */
839 pescx_ctl_status2.u64 =
840 cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
841 if (pescx_ctl_status2.s.pcierst) {
842 cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n",
843 pcie_port);
844 return -1;
845 }
846
847 /*
848 * Check BIST2 status. If any bits are set skip this interface. This
849 * is an attempt to catch PCIE-813 on pass 1 parts.
850 */
851 pescx_bist_status2.u64 =
852 cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
853 if (pescx_bist_status2.u64) {
854 cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this "
855 "port isn't hooked up, skipping.\n",
856 pcie_port);
857 return -1;
858 }
859
860 /* Check BIST status */
861 pescx_bist_status.u64 =
862 cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
863 if (pescx_bist_status.u64)
864 cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n",
865 pcie_port, CAST64(pescx_bist_status.u64));
866
867 /* Initialize the config space CSRs */
868 __cvmx_pcie_rc_initialize_config_space(pcie_port);
869
870 /* Bring the link up */
871 if (__cvmx_pcie_rc_initialize_link(pcie_port)) {
872 cvmx_dprintf
873 ("PCIe: ERROR: cvmx_pcie_rc_initialize_link() failed\n");
874 return -1;
875 }
876
877 /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
878 npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
879 /* Allow 16 words to combine */
880 npei_mem_access_ctl.s.max_word = 0;
881 /* Wait up to 127 cycles for more data */
882 npei_mem_access_ctl.s.timer = 127;
883 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
884
885 /* Setup Mem access SubDIDs */
886 mem_access_subid.u64 = 0;
887 /* Port the request is sent to. */
888 mem_access_subid.s.port = pcie_port;
889 /* Due to an errata on pass 1 chips, no merging is allowed. */
890 mem_access_subid.s.nmerge = 1;
891 /* Endian-swap for Reads. */
892 mem_access_subid.s.esr = 1;
893 /* Endian-swap for Writes. */
894 mem_access_subid.s.esw = 1;
895 /* No Snoop for Reads. */
896 mem_access_subid.s.nsr = 1;
897 /* No Snoop for Writes. */
898 mem_access_subid.s.nsw = 1;
899 /* Disable Relaxed Ordering for Reads. */
900 mem_access_subid.s.ror = 0;
901 /* Disable Relaxed Ordering for Writes. */
902 mem_access_subid.s.row = 0;
903 /* PCIe Adddress Bits <63:34>. */
904 mem_access_subid.s.ba = 0;
905
906 /*
907 * Setup mem access 12-15 for port 0, 16-19 for port 1,
908 * supplying 36 bits of address space.
909 */
910 for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
911 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i),
912 mem_access_subid.u64);
913 /* Set each SUBID to extend the addressable range */
914 mem_access_subid.s.ba += 1;
915 }
916
917 /*
918 * Disable the peer to peer forwarding register. This must be
919 * setup by the OS after it enumerates the bus and assigns
920 * addresses to the PCIe busses.
921 */
922 for (i = 0; i < 4; i++) {
923 cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1);
924 cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1);
925 }
926
927 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
928 cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
929
2b5987ab
DD		 930 /* BAR1 follows BAR2 with a gap. */
931 cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
932
933 bar1_index.u32 = 0;
934 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
935 bar1_index.s.ca = 1; /* Not Cached */
936 bar1_index.s.end_swp = 1; /* Endian Swap mode */
937 bar1_index.s.addr_v = 1; /* Valid entry */
938
939 base = pcie_port ? 16 : 0;
940
941 /* Big endian swizzle for 32-bit PEXP_NCB register. */
942#ifdef __MIPSEB__
943 addr_swizzle = 4;
944#else
945 addr_swizzle = 0;
946#endif
947 for (i = 0; i < 16; i++) {
948 cvmx_write64_uint32((CVMX_PEXP_NPEI_BAR1_INDEXX(base) ^ addr_swizzle),
949 bar1_index.u32);
950 base++;
951 /* 256MB / 16 >> 22 == 4 */
952 bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
953 }
e8635b48
DD		 954
955 /*
956 * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take
957 * precedence where they overlap. It also overlaps with the
958 * device addresses, so make sure the peer to peer forwarding
959 * is set right.
960 */
961 cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port), 0);
962
963 /*
964 * Setup BAR2 attributes
965 *
966 * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
967 * - PTLP_RO,CTLP_RO should normally be set (except for debug).
968 * - WAIT_COM=0 will likely work for all applications.
969 *
970 * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]).
971 */
972 if (pcie_port) {
973 union cvmx_npei_ctl_port1 npei_ctl_port;
974 npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT1);
975 npei_ctl_port.s.bar2_enb = 1;
976 npei_ctl_port.s.bar2_esx = 1;
977 npei_ctl_port.s.bar2_cax = 0;
978 npei_ctl_port.s.ptlp_ro = 1;
979 npei_ctl_port.s.ctlp_ro = 1;
980 npei_ctl_port.s.wait_com = 0;
981 npei_ctl_port.s.waitl_com = 0;
982 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT1, npei_ctl_port.u64);
983 } else {
984 union cvmx_npei_ctl_port0 npei_ctl_port;
985 npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT0);
986 npei_ctl_port.s.bar2_enb = 1;
987 npei_ctl_port.s.bar2_esx = 1;
988 npei_ctl_port.s.bar2_cax = 0;
989 npei_ctl_port.s.ptlp_ro = 1;
990 npei_ctl_port.s.ctlp_ro = 1;
991 npei_ctl_port.s.wait_com = 0;
992 npei_ctl_port.s.waitl_com = 0;
993 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64);
994 }
995 return 0;
996}
997
998
999/* Above was cvmx-pcie.c, below original pcie.c */
1000
1001
1002/**
1003 * Map a PCI device to the appropriate interrupt line
1004 *
01a6221a
DD		 1005 * @dev: The Linux PCI device structure for the device to map
1006 * @slot: The slot number for this device on __BUS 0__. Linux
e8635b48
DD		 1007 * enumerates through all the bridges and figures out the
1008 * slot on Bus 0 where this device eventually hooks to.
01a6221a 1009 * @pin: The PCI interrupt pin read from the device, then swizzled
e8635b48 1010 * as it goes through each bridge.
01a6221a 1011 * Returns Interrupt number for the device
e8635b48
DD		 1012 */
1013int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
1014 u8 slot, u8 pin)
1015{
1016 /*
1017 * The EBH5600 board with the PCI to PCIe bridge mistakenly
1018 * wires the first slot for both device id 2 and interrupt
1019 * A. According to the PCI spec, device id 2 should be C. The
1020 * following kludge attempts to fix this.
1021 */
1022 if (strstr(octeon_board_type_string(), "EBH5600") &&
1023 dev->bus && dev->bus->parent) {
1024 /*
1025 * Iterate all the way up the device chain and find
1026 * the root bus.
1027 */
1028 while (dev->bus && dev->bus->parent)
1029 dev = to_pci_dev(dev->bus->bridge);
1030 /* If the root bus is number 0 and the PEX 8114 is the
1031 * root, assume we are behind the miswired bus. We
1032 * need to correct the swizzle level by two. Yuck.
1033 */
1034 if ((dev->bus->number == 0) &&
1035 (dev->vendor == 0x10b5) && (dev->device == 0x8114)) {
1036 /*
1037 * The pin field is one based, not zero. We
1038 * need to swizzle it by minus two.
1039 */
1040 pin = ((pin - 3) & 3) + 1;
1041 }
1042 }
1043 /*
1044 * The -1 is because pin starts with one, not zero. It might
1045 * be that this equation needs to include the slot number, but
1046 * I don't have hardware to check that against.
1047 */
1048 return pin - 1 + OCTEON_IRQ_PCI_INT0;
1049}
1050
1051/**
1052 * Read a value from configuration space
1053 *
01a6221a
DD		 1054 * @bus:
1055 * @devfn:
1056 * @reg:
1057 * @size:
1058 * @val:
1059 * Returns
e8635b48
DD		 1060 */
1061static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
1062 unsigned int devfn, int reg, int size,
1063 u32 *val)
1064{
1065 union octeon_cvmemctl cvmmemctl;
1066 union octeon_cvmemctl cvmmemctl_save;
1067 int bus_number = bus->number;
1068
1069 /*
838c0570
DD		 1070 * For the top level bus make sure our hardware bus number
1071 * matches the software one.
e8635b48 1072 */
838c0570
DD		 1073 if (bus->parent == NULL) {
1074 union cvmx_pciercx_cfg006 pciercx_cfg006;
1075 pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port,
1076 CVMX_PCIERCX_CFG006(pcie_port));
1077 if (pciercx_cfg006.s.pbnum != bus_number) {
1078 pciercx_cfg006.s.pbnum = bus_number;
1079 pciercx_cfg006.s.sbnum = bus_number;
1080 pciercx_cfg006.s.subbnum = bus_number;
1081 cvmx_pcie_cfgx_write(pcie_port,
1082 CVMX_PCIERCX_CFG006(pcie_port),
1083 pciercx_cfg006.u32);
1084 }
1085 }
e8635b48
DD		 1086
1087 /*
1088 * PCIe only has a single device connected to Octeon. It is
1089 * always device ID 0. Don't bother doing reads for other
1090 * device IDs on the first segment.
1091 */
838c0570 1092 if ((bus->parent == NULL) && (devfn >> 3 != 0))
e8635b48
DD		 1093 return PCIBIOS_FUNC_NOT_SUPPORTED;
1094
1095 /*
1096 * The following is a workaround for the CN57XX, CN56XX,
1097 * CN55XX, and CN54XX errata with PCIe config reads from non
1098 * existent devices. These chips will hang the PCIe link if a
1099 * config read is performed that causes a UR response.
1100 */
1101 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
1102 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1)) {
1103 /*
1104 * For our EBH5600 board, port 0 has a bridge with two
1105 * PCI-X slots. We need a new special checks to make
1106 * sure we only probe valid stuff. The PCIe->PCI-X
1107 * bridge only respondes to device ID 0, function
1108 * 0-1
1109 */
838c0570 1110 if ((bus->parent == NULL) && (devfn >= 2))
e8635b48
DD		 1111 return PCIBIOS_FUNC_NOT_SUPPORTED;
1112 /*
1113 * The PCI-X slots are device ID 2,3. Choose one of
1114 * the below "if" blocks based on what is plugged into
1115 * the board.
1116 */
1117#if 1
1118 /* Use this option if you aren't using either slot */
1119 if (bus_number == 1)
1120 return PCIBIOS_FUNC_NOT_SUPPORTED;
1121#elif 0
1122 /*
1123 * Use this option if you are using the first slot but
1124 * not the second.
1125 */
1126 if ((bus_number == 1) && (devfn >> 3 != 2))
1127 return PCIBIOS_FUNC_NOT_SUPPORTED;
1128#elif 0
1129 /*
1130 * Use this option if you are using the second slot
1131 * but not the first.
1132 */
1133 if ((bus_number == 1) && (devfn >> 3 != 3))
1134 return PCIBIOS_FUNC_NOT_SUPPORTED;
1135#elif 0
1136 /* Use this opion if you are using both slots */
1137 if ((bus_number == 1) &&
1138 !((devfn == (2 << 3)) || (devfn == (3 << 3))))
1139 return PCIBIOS_FUNC_NOT_SUPPORTED;
1140#endif
1141
1142 /*
1143 * Shorten the DID timeout so bus errors for PCIe
1144 * config reads from non existent devices happen
1145 * faster. This allows us to continue booting even if
1146 * the above "if" checks are wrong. Once one of these
1147 * errors happens, the PCIe port is dead.
1148 */
1149 cvmmemctl_save.u64 = __read_64bit_c0_register($11, 7);
1150 cvmmemctl.u64 = cvmmemctl_save.u64;
1151 cvmmemctl.s.didtto = 2;
1152 __write_64bit_c0_register($11, 7, cvmmemctl.u64);
1153 }
1154
1155 switch (size) {
1156 case 4:
1157 *val = cvmx_pcie_config_read32(pcie_port, bus_number,
1158 devfn >> 3, devfn & 0x7, reg);
1159 break;
1160 case 2:
1161 *val = cvmx_pcie_config_read16(pcie_port, bus_number,
1162 devfn >> 3, devfn & 0x7, reg);
1163 break;
1164 case 1:
1165 *val = cvmx_pcie_config_read8(pcie_port, bus_number, devfn >> 3,
1166 devfn & 0x7, reg);
1167 break;
1168 default:
1169 return PCIBIOS_FUNC_NOT_SUPPORTED;
1170 }
1171
1172 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
1173 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1))
1174 __write_64bit_c0_register($11, 7, cvmmemctl_save.u64);
1175 return PCIBIOS_SUCCESSFUL;
1176}
1177
1178static int octeon_pcie0_read_config(struct pci_bus *bus, unsigned int devfn,
1179 int reg, int size, u32 *val)
1180{
1181 return octeon_pcie_read_config(0, bus, devfn, reg, size, val);
1182}
1183
1184static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn,
1185 int reg, int size, u32 *val)
1186{
1187 return octeon_pcie_read_config(1, bus, devfn, reg, size, val);
1188}
1189
1190
1191
1192/**
1193 * Write a value to PCI configuration space
1194 *
01a6221a
DD		 1195 * @bus:
1196 * @devfn:
1197 * @reg:
1198 * @size:
1199 * @val:
1200 * Returns
e8635b48
DD		 1201 */
1202static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus,
1203 unsigned int devfn, int reg,
1204 int size, u32 val)
1205{
1206 int bus_number = bus->number;
e8635b48
DD		 1207
1208 switch (size) {
1209 case 4:
1210 cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3,
1211 devfn & 0x7, reg, val);
1212 return PCIBIOS_SUCCESSFUL;
1213 case 2:
1214 cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3,
1215 devfn & 0x7, reg, val);
1216 return PCIBIOS_SUCCESSFUL;
1217 case 1:
1218 cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3,
1219 devfn & 0x7, reg, val);
1220 return PCIBIOS_SUCCESSFUL;
1221 }
1222#if PCI_CONFIG_SPACE_DELAY
1223 udelay(PCI_CONFIG_SPACE_DELAY);
1224#endif
1225 return PCIBIOS_FUNC_NOT_SUPPORTED;
1226}
1227
1228static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn,
1229 int reg, int size, u32 val)
1230{
1231 return octeon_pcie_write_config(0, bus, devfn, reg, size, val);
1232}
1233
1234static int octeon_pcie1_write_config(struct pci_bus *bus, unsigned int devfn,
1235 int reg, int size, u32 val)
1236{
1237 return octeon_pcie_write_config(1, bus, devfn, reg, size, val);
1238}
1239
1240static struct pci_ops octeon_pcie0_ops = {
1241 octeon_pcie0_read_config,
1242 octeon_pcie0_write_config,
1243};
1244
1245static struct resource octeon_pcie0_mem_resource = {
1246 .name = "Octeon PCIe0 MEM",
1247 .flags = IORESOURCE_MEM,
1248};
1249
1250static struct resource octeon_pcie0_io_resource = {
1251 .name = "Octeon PCIe0 IO",
1252 .flags = IORESOURCE_IO,
1253};
1254
1255static struct pci_controller octeon_pcie0_controller = {
1256 .pci_ops = &octeon_pcie0_ops,
1257 .mem_resource = &octeon_pcie0_mem_resource,
1258 .io_resource = &octeon_pcie0_io_resource,
1259};
1260
1261static struct pci_ops octeon_pcie1_ops = {
1262 octeon_pcie1_read_config,
1263 octeon_pcie1_write_config,
1264};
1265
1266static struct resource octeon_pcie1_mem_resource = {
1267 .name = "Octeon PCIe1 MEM",
1268 .flags = IORESOURCE_MEM,
1269};
1270
1271static struct resource octeon_pcie1_io_resource = {
1272 .name = "Octeon PCIe1 IO",
1273 .flags = IORESOURCE_IO,
1274};
1275
1276static struct pci_controller octeon_pcie1_controller = {
1277 .pci_ops = &octeon_pcie1_ops,
1278 .mem_resource = &octeon_pcie1_mem_resource,
1279 .io_resource = &octeon_pcie1_io_resource,
1280};
1281
1282
1283/**
1284 * Initialize the Octeon PCIe controllers
1285 *
01a6221a 1286 * Returns
e8635b48
DD		 1287 */
1288static int __init octeon_pcie_setup(void)
1289{
1290 union cvmx_npei_ctl_status npei_ctl_status;
1291 int result;
1292
1293 /* These chips don't have PCIe */
1294 if (!octeon_has_feature(OCTEON_FEATURE_PCIE))
1295 return 0;
1296
1297 /* Point pcibios_map_irq() to the PCIe version of it */
1298 octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq;
1299
1300 /* Use the PCIe based DMA mappings */
1301 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
1302
1303 /*
1304 * PCIe I/O range. It is based on port 0 but includes up until
1305 * port 1's end.
1306 */
1307 set_io_port_base(CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0)));
1308 ioport_resource.start = 0;
1309 ioport_resource.end =
1310 cvmx_pcie_get_io_base_address(1) -
1311 cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1;
1312
1313 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
1314 if (npei_ctl_status.s.host_mode) {
1315 pr_notice("PCIe: Initializing port 0\n");
1316 result = cvmx_pcie_rc_initialize(0);
1317 if (result == 0) {
1318 /* Memory offsets are physical addresses */
1319 octeon_pcie0_controller.mem_offset =
1320 cvmx_pcie_get_mem_base_address(0);
1321 /* IO offsets are Mips virtual addresses */
1322 octeon_pcie0_controller.io_map_base =
1323 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address
1324 (0));
1325 octeon_pcie0_controller.io_offset = 0;
1326 /*
1327 * To keep things similar to PCI, we start
1328 * device addresses at the same place as PCI
1329 * uisng big bar support. This normally
1330 * translates to 4GB-256MB, which is the same
1331 * as most x86 PCs.
1332 */
1333 octeon_pcie0_controller.mem_resource->start =
1334 cvmx_pcie_get_mem_base_address(0) +
1335 (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
1336 octeon_pcie0_controller.mem_resource->end =
1337 cvmx_pcie_get_mem_base_address(0) +
1338 cvmx_pcie_get_mem_size(0) - 1;
1339 /*
1340 * Ports must be above 16KB for the ISA bus
1341 * filtering in the PCI-X to PCI bridge.
1342 */
1343 octeon_pcie0_controller.io_resource->start = 4 << 10;
1344 octeon_pcie0_controller.io_resource->end =
1345 cvmx_pcie_get_io_size(0) - 1;
1346 register_pci_controller(&octeon_pcie0_controller);
1347 }
1348 } else {
1349 pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n");
1350 }
1351
1352 /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
1353 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
1354 union cvmx_npei_dbg_data npei_dbg_data;
1355 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1356 if (npei_dbg_data.cn52xx.qlm0_link_width)
1357 return 0;
1358 }
1359
1360 pr_notice("PCIe: Initializing port 1\n");
1361 result = cvmx_pcie_rc_initialize(1);
1362 if (result == 0) {
1363 /* Memory offsets are physical addresses */
1364 octeon_pcie1_controller.mem_offset =
1365 cvmx_pcie_get_mem_base_address(1);
1366 /* IO offsets are Mips virtual addresses */
1367 octeon_pcie1_controller.io_map_base =
1368 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(1));
1369 octeon_pcie1_controller.io_offset =
1370 cvmx_pcie_get_io_base_address(1) -
1371 cvmx_pcie_get_io_base_address(0);
1372 /*
1373 * To keep things similar to PCI, we start device
1374 * addresses at the same place as PCI uisng big bar
1375 * support. This normally translates to 4GB-256MB,
1376 * which is the same as most x86 PCs.
1377 */
1378 octeon_pcie1_controller.mem_resource->start =
1379 cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
1380 (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
1381 octeon_pcie1_controller.mem_resource->end =
1382 cvmx_pcie_get_mem_base_address(1) +
1383 cvmx_pcie_get_mem_size(1) - 1;
1384 /*
1385 * Ports must be above 16KB for the ISA bus filtering
1386 * in the PCI-X to PCI bridge.
1387 */
1388 octeon_pcie1_controller.io_resource->start =
1389 cvmx_pcie_get_io_base_address(1) -
1390 cvmx_pcie_get_io_base_address(0);
1391 octeon_pcie1_controller.io_resource->end =
1392 octeon_pcie1_controller.io_resource->start +
1393 cvmx_pcie_get_io_size(1) - 1;
1394 register_pci_controller(&octeon_pcie1_controller);
1395 }
b93b2abc
DD		 1396
1397 octeon_pci_dma_init();
1398
e8635b48
DD		 1399 return 0;
1400}
1401
1402arch_initcall(octeon_pcie_setup);
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