[net-next-2.6.git] / arch / mips / pci / pci-yosemite.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <asm/titan_dep.h>

extern struct pci_ops titan_pci_ops;

static struct resource py_mem_resource = {
	.start	= 0xe0000000UL,
	.end	= 0xe3ffffffUL,
	.name	= "Titan PCI MEM",
	.flags	= IORESOURCE_MEM
};

/*
 * PMON really reserves 16MB of I/O port space but that's stupid, nothing
 * needs that much since allocations are limited to 256 bytes per device
 * anyway.  So we just claim 64kB here.
 */
#define TITAN_IO_SIZE	0x0000ffffUL
#define TITAN_IO_BASE	0xe8000000UL

static struct resource py_io_resource = {
	.start	= 0x00001000UL,
	.end	= TITAN_IO_SIZE - 1,
	.name	= "Titan IO MEM",
	.flags	= IORESOURCE_IO,
};

static struct pci_controller py_controller = {
	.pci_ops	= &titan_pci_ops,
	.mem_resource	= &py_mem_resource,
	.mem_offset	= 0x00000000UL,
	.io_resource	= &py_io_resource,
	.io_offset	= 0x00000000UL
};

static char ioremap_failed[] __initdata = "Could not ioremap I/O port range";

static int __init pmc_yosemite_setup(void)
{
	unsigned long io_v_base;

	io_v_base = (unsigned long) ioremap(TITAN_IO_BASE, TITAN_IO_SIZE);
	if (!io_v_base)
		panic(ioremap_failed);

	set_io_port_base(io_v_base);
	py_controller.io_map_base = io_v_base;
	TITAN_WRITE(RM9000x2_OCD_LKM7, TITAN_READ(RM9000x2_OCD_LKM7) | 1);

	ioport_resource.end = TITAN_IO_SIZE - 1;

	register_pci_controller(&py_controller);

	return 0;
}

arch_initcall(pmc_yosemite_setup);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
	7	*/
	8	#include <linux/init.h>
	9	#include <linux/kernel.h>
	10	#include <linux/types.h>
	11	#include <linux/pci.h>
	12	#include <asm/titan_dep.h>
	13
	14	extern struct pci_ops titan_pci_ops;
	15
	16	static struct resource py_mem_resource = {
5e46c3ae RB	17	.start = 0xe0000000UL,
	18	.end = 0xe3ffffffUL,
	19	.name = "Titan PCI MEM",
	20	.flags = IORESOURCE_MEM
1da177e4 LT	21	};
	22
	23	/*
	24	* PMON really reserves 16MB of I/O port space but that's stupid, nothing
	25	* needs that much since allocations are limited to 256 bytes per device
	26	* anyway. So we just claim 64kB here.
	27	*/
	28	#define TITAN_IO_SIZE 0x0000ffffUL
	29	#define TITAN_IO_BASE 0xe8000000UL
	30
	31	static struct resource py_io_resource = {
5e46c3ae RB	32	.start = 0x00001000UL,
	33	.end = TITAN_IO_SIZE - 1,
	34	.name = "Titan IO MEM",
	35	.flags = IORESOURCE_IO,
1da177e4 LT	36	};
	37
	38	static struct pci_controller py_controller = {
	39	.pci_ops = &titan_pci_ops,
	40	.mem_resource = &py_mem_resource,
	41	.mem_offset = 0x00000000UL,
	42	.io_resource = &py_io_resource,
	43	.io_offset = 0x00000000UL
	44	};
	45
	46	static char ioremap_failed[] __initdata = "Could not ioremap I/O port range";
	47
	48	static int __init pmc_yosemite_setup(void)
	49	{
	50	unsigned long io_v_base;
	51
	52	io_v_base = (unsigned long) ioremap(TITAN_IO_BASE, TITAN_IO_SIZE);
	53	if (!io_v_base)
	54	panic(ioremap_failed);
	55
	56	set_io_port_base(io_v_base);
8faf2e6c	57	py_controller.io_map_base = io_v_base;
1da177e4 LT	58	TITAN_WRITE(RM9000x2_OCD_LKM7, TITAN_READ(RM9000x2_OCD_LKM7) \| 1);
	59
	60	ioport_resource.end = TITAN_IO_SIZE - 1;
	61
	62	register_pci_controller(&py_controller);
	63
	64	return 0;
	65	}
	66
	67	arch_initcall(pmc_yosemite_setup);