[net-next-2.6.git] / arch / mips / oprofile / op_model_loongson2.c

/*
 * Loongson2 performance counter driver for oprofile
 *
 * Copyright (C) 2009 Lemote Inc.
 * Author: Yanhua <yanh@lemote.com>
 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 */
#include <linux/init.h>
#include <linux/oprofile.h>
#include <linux/interrupt.h>

#include <loongson.h>			/* LOONGSON2_PERFCNT_IRQ */
#include "op_impl.h"

/*
 * a patch should be sent to oprofile with the loongson-specific support.
 * otherwise, the oprofile tool will not recognize this and complain about
 * "cpu_type 'unset' is not valid".
 */
#define LOONGSON2_CPU_TYPE	"mips/loongson2"

#define LOONGSON2_PERFCTRL_EVENT(idx, event) \
	(((event) & 0x0f) << ((idx) ? 9 : 5))

#define LOONGSON2_PERFCNT_EXL			(1UL	<<  0)
#define LOONGSON2_PERFCNT_KERNEL		(1UL    <<  1)
#define LOONGSON2_PERFCNT_SUPERVISOR	(1UL    <<  2)
#define LOONGSON2_PERFCNT_USER			(1UL    <<  3)
#define LOONGSON2_PERFCNT_INT_EN		(1UL    <<  4)
#define LOONGSON2_PERFCNT_OVERFLOW		(1ULL   << 31)

/* Loongson2 performance counter register */
#define read_c0_perfctrl() __read_64bit_c0_register($24, 0)
#define write_c0_perfctrl(val) __write_64bit_c0_register($24, 0, val)
#define read_c0_perfcnt() __read_64bit_c0_register($25, 0)
#define write_c0_perfcnt(val) __write_64bit_c0_register($25, 0, val)

static struct loongson2_register_config {
	unsigned int ctrl;
	unsigned long long reset_counter1;
	unsigned long long reset_counter2;
	int cnt1_enabled, cnt2_enabled;
} reg;

static char *oprofid = "LoongsonPerf";
static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id);
/* Compute all of the registers in preparation for enabling profiling.  */

static void loongson2_reg_setup(struct op_counter_config *cfg)
{
	unsigned int ctrl = 0;

	reg.reset_counter1 = 0;
	reg.reset_counter2 = 0;
	/* Compute the performance counter ctrl word.  */
	/* For now count kernel and user mode */
	if (cfg[0].enabled) {
		ctrl |= LOONGSON2_PERFCTRL_EVENT(0, cfg[0].event);
		reg.reset_counter1 = 0x80000000ULL - cfg[0].count;
	}

	if (cfg[1].enabled) {
		ctrl |= LOONGSON2_PERFCTRL_EVENT(1, cfg[1].event);
		reg.reset_counter2 = 0x80000000ULL - cfg[1].count;
	}

	if (cfg[0].enabled || cfg[1].enabled) {
		ctrl |= LOONGSON2_PERFCNT_EXL | LOONGSON2_PERFCNT_INT_EN;
		if (cfg[0].kernel || cfg[1].kernel)
			ctrl |= LOONGSON2_PERFCNT_KERNEL;
		if (cfg[0].user || cfg[1].user)
			ctrl |= LOONGSON2_PERFCNT_USER;
	}

	reg.ctrl = ctrl;

	reg.cnt1_enabled = cfg[0].enabled;
	reg.cnt2_enabled = cfg[1].enabled;

}

/* Program all of the registers in preparation for enabling profiling.  */

static void loongson2_cpu_setup(void *args)
{
	uint64_t perfcount;

	perfcount = (reg.reset_counter2 << 32) | reg.reset_counter1;
	write_c0_perfcnt(perfcount);
}

static void loongson2_cpu_start(void *args)
{
	/* Start all counters on current CPU */
	if (reg.cnt1_enabled || reg.cnt2_enabled)
		write_c0_perfctrl(reg.ctrl);
}

static void loongson2_cpu_stop(void *args)
{
	/* Stop all counters on current CPU */
	write_c0_perfctrl(0);
	memset(&reg, 0, sizeof(reg));
}

static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
{
	uint64_t counter, counter1, counter2;
	struct pt_regs *regs = get_irq_regs();
	int enabled;

	/*
	 * LOONGSON2 defines two 32-bit performance counters.
	 * To avoid a race updating the registers we need to stop the counters
	 * while we're messing with
	 * them ...
	 */

	/* Check whether the irq belongs to me */
	enabled = read_c0_perfctrl() & LOONGSON2_PERFCNT_INT_EN;
	if (!enabled)
		return IRQ_NONE;
	enabled = reg.cnt1_enabled | reg.cnt2_enabled;
	if (!enabled)
		return IRQ_NONE;

	counter = read_c0_perfcnt();
	counter1 = counter & 0xffffffff;
	counter2 = counter >> 32;

	if (counter1 & LOONGSON2_PERFCNT_OVERFLOW) {
		if (reg.cnt1_enabled)
			oprofile_add_sample(regs, 0);
		counter1 = reg.reset_counter1;
	}
	if (counter2 & LOONGSON2_PERFCNT_OVERFLOW) {
		if (reg.cnt2_enabled)
			oprofile_add_sample(regs, 1);
		counter2 = reg.reset_counter2;
	}

	write_c0_perfcnt((counter2 << 32) | counter1);

	return IRQ_HANDLED;
}

static int __init loongson2_init(void)
{
	return request_irq(LOONGSON2_PERFCNT_IRQ, loongson2_perfcount_handler,
			   IRQF_SHARED, "Perfcounter", oprofid);
}

static void loongson2_exit(void)
{
	write_c0_perfctrl(0);
	free_irq(LOONGSON2_PERFCNT_IRQ, oprofid);
}

struct op_mips_model op_model_loongson2_ops = {
	.reg_setup = loongson2_reg_setup,
	.cpu_setup = loongson2_cpu_setup,
	.init = loongson2_init,
	.exit = loongson2_exit,
	.cpu_start = loongson2_cpu_start,
	.cpu_stop = loongson2_cpu_stop,
	.cpu_type = LOONGSON2_CPU_TYPE,
	.num_counters = 2
};
Commit	Line	Data
67b35e5d WZ	1	/*
	2	* Loongson2 performance counter driver for oprofile
	3	*
937893cf	4	* Copyright (C) 2009 Lemote Inc.
67b35e5d	5	* Author: Yanhua <yanh@lemote.com>
f7a904df	6	* Author: Wu Zhangjin <wuzhangjin@gmail.com>
67b35e5d WZ	7	*
	8	* This file is subject to the terms and conditions of the GNU General Public
	9	* License. See the file "COPYING" in the main directory of this archive
	10	* for more details.
	11	*
	12	*/
	13	#include <linux/init.h>
	14	#include <linux/oprofile.h>
	15	#include <linux/interrupt.h>
	16
	17	#include <loongson.h> /* LOONGSON2_PERFCNT_IRQ */
	18	#include "op_impl.h"
	19
	20	/*
	21	* a patch should be sent to oprofile with the loongson-specific support.
	22	* otherwise, the oprofile tool will not recognize this and complain about
	23	* "cpu_type 'unset' is not valid".
	24	*/
55f4e1d4	25	#define LOONGSON2_CPU_TYPE "mips/loongson2"
67b35e5d	26
86e5a520 WZ	27	#define LOONGSON2_PERFCTRL_EVENT(idx, event) \
86e5a520 WZ	28	(((event) & 0x0f) << ((idx) ? 9 : 5))
67b35e5d WZ	29
	30	#define LOONGSON2_PERFCNT_EXL (1UL << 0)
	31	#define LOONGSON2_PERFCNT_KERNEL (1UL << 1)
	32	#define LOONGSON2_PERFCNT_SUPERVISOR (1UL << 2)
	33	#define LOONGSON2_PERFCNT_USER (1UL << 3)
	34	#define LOONGSON2_PERFCNT_INT_EN (1UL << 4)
	35	#define LOONGSON2_PERFCNT_OVERFLOW (1ULL << 31)
	36
	37	/* Loongson2 performance counter register */
	38	#define read_c0_perfctrl() __read_64bit_c0_register($24, 0)
	39	#define write_c0_perfctrl(val) __write_64bit_c0_register($24, 0, val)
	40	#define read_c0_perfcnt() __read_64bit_c0_register($25, 0)
	41	#define write_c0_perfcnt(val) __write_64bit_c0_register($25, 0, val)
	42
	43	static struct loongson2_register_config {
	44	unsigned int ctrl;
	45	unsigned long long reset_counter1;
	46	unsigned long long reset_counter2;
8813d33e	47	int cnt1_enabled, cnt2_enabled;
67b35e5d WZ	48	} reg;
67b35e5d WZ	49
67b35e5d WZ	50	static char *oprofid = "LoongsonPerf";
	51	static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id);
	52	/* Compute all of the registers in preparation for enabling profiling. */
	53
	54	static void loongson2_reg_setup(struct op_counter_config *cfg)
	55	{
	56	unsigned int ctrl = 0;
	57
	58	reg.reset_counter1 = 0;
	59	reg.reset_counter2 = 0;
	60	/* Compute the performance counter ctrl word. */
	61	/* For now count kernel and user mode */
	62	if (cfg[0].enabled) {
86e5a520	63	ctrl \|= LOONGSON2_PERFCTRL_EVENT(0, cfg[0].event);
67b35e5d WZ	64	reg.reset_counter1 = 0x80000000ULL - cfg[0].count;
	65	}
	66
	67	if (cfg[1].enabled) {
86e5a520	68	ctrl \|= LOONGSON2_PERFCTRL_EVENT(1, cfg[1].event);
c838abc5	69	reg.reset_counter2 = 0x80000000ULL - cfg[1].count;
67b35e5d WZ	70	}
	71
	72	if (cfg[0].enabled \|\| cfg[1].enabled) {
	73	ctrl \|= LOONGSON2_PERFCNT_EXL \| LOONGSON2_PERFCNT_INT_EN;
	74	if (cfg[0].kernel \|\| cfg[1].kernel)
	75	ctrl \|= LOONGSON2_PERFCNT_KERNEL;
	76	if (cfg[0].user \|\| cfg[1].user)
	77	ctrl \|= LOONGSON2_PERFCNT_USER;
	78	}
	79
	80	reg.ctrl = ctrl;
	81
8813d33e UKK	82	reg.cnt1_enabled = cfg[0].enabled;
8813d33e UKK	83	reg.cnt2_enabled = cfg[1].enabled;
67b35e5d WZ	84
	85	}
	86
	87	/* Program all of the registers in preparation for enabling profiling. */
	88
	89	static void loongson2_cpu_setup(void *args)
	90	{
	91	uint64_t perfcount;
	92
	93	perfcount = (reg.reset_counter2 << 32) \| reg.reset_counter1;
	94	write_c0_perfcnt(perfcount);
	95	}
	96
	97	static void loongson2_cpu_start(void *args)
	98	{
	99	/* Start all counters on current CPU */
8813d33e	100	if (reg.cnt1_enabled \|\| reg.cnt2_enabled)
67b35e5d WZ	101	write_c0_perfctrl(reg.ctrl);
	102	}
	103
	104	static void loongson2_cpu_stop(void *args)
	105	{
	106	/* Stop all counters on current CPU */
	107	write_c0_perfctrl(0);
	108	memset(&reg, 0, sizeof(reg));
	109	}
	110
	111	static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
	112	{
	113	uint64_t counter, counter1, counter2;
	114	struct pt_regs *regs = get_irq_regs();
	115	int enabled;
67b35e5d WZ	116
	117	/*
	118	* LOONGSON2 defines two 32-bit performance counters.
	119	* To avoid a race updating the registers we need to stop the counters
	120	* while we're messing with
	121	* them ...
	122	*/
	123
	124	/* Check whether the irq belongs to me */
4e73238d	125	enabled = read_c0_perfctrl() & LOONGSON2_PERFCNT_INT_EN;
937893cf WZ	126	if (!enabled)
937893cf WZ	127	return IRQ_NONE;
8813d33e	128	enabled = reg.cnt1_enabled \| reg.cnt2_enabled;
67b35e5d WZ	129	if (!enabled)
	130	return IRQ_NONE;
	131
	132	counter = read_c0_perfcnt();
	133	counter1 = counter & 0xffffffff;
	134	counter2 = counter >> 32;
	135
67b35e5d	136	if (counter1 & LOONGSON2_PERFCNT_OVERFLOW) {
8813d33e	137	if (reg.cnt1_enabled)
67b35e5d WZ	138	oprofile_add_sample(regs, 0);
	139	counter1 = reg.reset_counter1;
	140	}
	141	if (counter2 & LOONGSON2_PERFCNT_OVERFLOW) {
8813d33e	142	if (reg.cnt2_enabled)
67b35e5d WZ	143	oprofile_add_sample(regs, 1);
	144	counter2 = reg.reset_counter2;
	145	}
	146
67b35e5d WZ	147	write_c0_perfcnt((counter2 << 32) \| counter1);
	148
	149	return IRQ_HANDLED;
	150	}
	151
	152	static int __init loongson2_init(void)
	153	{
	154	return request_irq(LOONGSON2_PERFCNT_IRQ, loongson2_perfcount_handler,
	155	IRQF_SHARED, "Perfcounter", oprofid);
	156	}
	157
	158	static void loongson2_exit(void)
	159	{
	160	write_c0_perfctrl(0);
	161	free_irq(LOONGSON2_PERFCNT_IRQ, oprofid);
	162	}
	163
	164	struct op_mips_model op_model_loongson2_ops = {
	165	.reg_setup = loongson2_reg_setup,
	166	.cpu_setup = loongson2_cpu_setup,
	167	.init = loongson2_init,
	168	.exit = loongson2_exit,
	169	.cpu_start = loongson2_cpu_start,
	170	.cpu_stop = loongson2_cpu_stop,
	171	.cpu_type = LOONGSON2_CPU_TYPE,
	172	.num_counters = 2
	173	};