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Merge branch 'for-linus' of git://git.infradead.org/users/eparis/notify
[net-next-2.6.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
4194318c 7 * Copyright (C) 2001, 2004 MIPS Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
f8ede0f7 19#include <linux/module.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4
LT		 22#include <asm/cpu.h>
23#include <asm/fpu.h>
24#include <asm/mipsregs.h>
25#include <asm/system.h>
654f57bf 26#include <asm/watch.h>
a074f0e8 27#include <asm/spram.h>
949e51be
DD		 28#include <asm/uaccess.h>
29
1da177e4
LT		 30/*
31 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
32 * the implementation of the "wait" feature differs between CPU families. This
33 * points to the function that implements CPU specific wait.
34 * The wait instruction stops the pipeline and reduces the power consumption of
35 * the CPU very much.
36 */
982f6ffe 37void (*cpu_wait)(void);
f8ede0f7 38EXPORT_SYMBOL(cpu_wait);
1da177e4
LT		 39
40static void r3081_wait(void)
41{
42 unsigned long cfg = read_c0_conf();
43 write_c0_conf(cfg | R30XX_CONF_HALT);
44}
45
46static void r39xx_wait(void)
47{
60a6c377
AN		 48 local_irq_disable();
49 if (!need_resched())
50 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
51 local_irq_enable();
1da177e4
LT		 52}
53
c65a5480 54extern void r4k_wait(void);
60a6c377
AN		 55
56/*
57 * This variant is preferable as it allows testing need_resched and going to
58 * sleep depending on the outcome atomically. Unfortunately the "It is
59 * implementation-dependent whether the pipeline restarts when a non-enabled
60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
61 * using this version a gamble.
62 */
8531a35e 63void r4k_wait_irqoff(void)
60a6c377
AN		 64{
65 local_irq_disable();
66 if (!need_resched())
8531a35e
KK		 67 __asm__(" .set push \n"
68 " .set mips3 \n"
60a6c377 69 " wait \n"
8531a35e 70 " .set pop \n");
60a6c377 71 local_irq_enable();
8531a35e
KK		 72 __asm__(" .globl __pastwait \n"
73 "__pastwait: \n");
74 return;
1da177e4
LT		 75}
76
5a812999
RB		 77/*
78 * The RM7000 variant has to handle erratum 38. The workaround is to not
79 * have any pending stores when the WAIT instruction is executed.
80 */
81static void rm7k_wait_irqoff(void)
82{
83 local_irq_disable();
84 if (!need_resched())
85 __asm__(
86 " .set push \n"
87 " .set mips3 \n"
88 " .set noat \n"
89 " mfc0 $1, $12 \n"
90 " sync \n"
91 " mtc0 $1, $12 # stalls until W stage \n"
92 " wait \n"
93 " mtc0 $1, $12 # stalls until W stage \n"
94 " .set pop \n");
95 local_irq_enable();
96}
97
2882b0c6
ML		 98/*
99 * The Au1xxx wait is available only if using 32khz counter or
100 * external timer source, but specifically not CP0 Counter.
101 * alchemy/common/time.c may override cpu_wait!
102 */
494900af 103static void au1k_wait(void)
1da177e4 104{
60a6c377
AN		 105 __asm__(" .set mips3 \n"
106 " cache 0x14, 0(%0) \n"
107 " cache 0x14, 32(%0) \n"
108 " sync \n"
109 " nop \n"
110 " wait \n"
111 " nop \n"
112 " nop \n"
113 " nop \n"
114 " nop \n"
115 " .set mips0 \n"
10f650db 116 : : "r" (au1k_wait));
1da177e4
LT		 117}
118
982f6ffe 119static int __initdata nowait;
55d04dff 120
f49a747c 121static int __init wait_disable(char *s)
55d04dff
RB		 122{
123 nowait = 1;
124
125 return 1;
126}
127
128__setup("nowait", wait_disable);
129
0103d23f
KC		 130static int __cpuinitdata mips_fpu_disabled;
131
132static int __init fpu_disable(char *s)
133{
134 cpu_data[0].options &= ~MIPS_CPU_FPU;
135 mips_fpu_disabled = 1;
136
137 return 1;
138}
139
140__setup("nofpu", fpu_disable);
141
142int __cpuinitdata mips_dsp_disabled;
143
144static int __init dsp_disable(char *s)
145{
146 cpu_data[0].ases &= ~MIPS_ASE_DSP;
147 mips_dsp_disabled = 1;
148
149 return 1;
150}
151
152__setup("nodsp", dsp_disable);
153
c65a5480 154void __init check_wait(void)
1da177e4
LT		 155{
156 struct cpuinfo_mips *c = &current_cpu_data;
157
55d04dff 158 if (nowait) {
c2379230 159 printk("Wait instruction disabled.\n");
55d04dff
RB		 160 return;
161 }
162
1da177e4
LT		 163 switch (c->cputype) {
164 case CPU_R3081:
165 case CPU_R3081E:
166 cpu_wait = r3081_wait;
1da177e4
LT		 167 break;
168 case CPU_TX3927:
169 cpu_wait = r39xx_wait;
1da177e4
LT		 170 break;
171 case CPU_R4200:
172/* case CPU_R4300: */
173 case CPU_R4600:
174 case CPU_R4640:
175 case CPU_R4650:
176 case CPU_R4700:
177 case CPU_R5000:
a644b277 178 case CPU_R5500:
1da177e4 179 case CPU_NEVADA:
1da177e4
LT		 180 case CPU_4KC:
181 case CPU_4KEC:
182 case CPU_4KSC:
183 case CPU_5KC:
1da177e4 184 case CPU_25KF:
4b3e975e 185 case CPU_PR4450:
602977b0
KC		 186 case CPU_BMIPS3300:
187 case CPU_BMIPS4350:
188 case CPU_BMIPS4380:
189 case CPU_BMIPS5000:
0dd4781b 190 case CPU_CAVIUM_OCTEON:
6f329468 191 case CPU_CAVIUM_OCTEON_PLUS:
0e56b385 192 case CPU_CAVIUM_OCTEON2:
83ccf69d 193 case CPU_JZRISC:
4b3e975e
RB		 194 cpu_wait = r4k_wait;
195 break;
196
5a812999
RB		 197 case CPU_RM7000:
198 cpu_wait = rm7k_wait_irqoff;
199 break;
200
4b3e975e 201 case CPU_24K:
bbc7f22f 202 case CPU_34K:
39b8d525 203 case CPU_1004K:
4b3e975e
RB		 204 cpu_wait = r4k_wait;
205 if (read_c0_config7() & MIPS_CONF7_WII)
206 cpu_wait = r4k_wait_irqoff;
207 break;
208
c620953c 209 case CPU_74K:
1da177e4 210 cpu_wait = r4k_wait;
4b3e975e
RB		 211 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
212 cpu_wait = r4k_wait_irqoff;
1da177e4 213 break;
4b3e975e 214
60a6c377
AN		 215 case CPU_TX49XX:
216 cpu_wait = r4k_wait_irqoff;
60a6c377 217 break;
270717a8 218 case CPU_ALCHEMY:
0c694de1 219 cpu_wait = au1k_wait;
1da177e4 220 break;
c8eae71d
RB		 221 case CPU_20KC:
222 /*
223 * WAIT on Rev1.0 has E1, E2, E3 and E16.
224 * WAIT on Rev2.0 and Rev3.0 has E16.
225 * Rev3.1 WAIT is nop, why bother
226 */
227 if ((c->processor_id & 0xff) <= 0x64)
228 break;
229
50da469a
RB		 230 /*
231 * Another rev is incremeting c0_count at a reduced clock
232 * rate while in WAIT mode. So we basically have the choice
233 * between using the cp0 timer as clocksource or avoiding
234 * the WAIT instruction. Until more details are known,
235 * disable the use of WAIT for 20Kc entirely.
236 cpu_wait = r4k_wait;
237 */
c8eae71d 238 break;
441ee341 239 case CPU_RM9000:
c2379230 240 if ((c->processor_id & 0x00ff) >= 0x40)
441ee341 241 cpu_wait = r4k_wait;
441ee341 242 break;
1da177e4 243 default:
1da177e4
LT		 244 break;
245 }
246}
247
9267a30d
MSJ		 248static inline void check_errata(void)
249{
250 struct cpuinfo_mips *c = &current_cpu_data;
251
252 switch (c->cputype) {
253 case CPU_34K:
254 /*
255 * Erratum "RPS May Cause Incorrect Instruction Execution"
256 * This code only handles VPE0, any SMP/SMTC/RTOS code
257 * making use of VPE1 will be responsable for that VPE.
258 */
259 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
260 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
261 break;
262 default:
263 break;
264 }
265}
266
1da177e4
LT		 267void __init check_bugs32(void)
268{
9267a30d 269 check_errata();
1da177e4
LT		 270}
271
272/*
273 * Probe whether cpu has config register by trying to play with
274 * alternate cache bit and see whether it matters.
275 * It's used by cpu_probe to distinguish between R3000A and R3081.
276 */
277static inline int cpu_has_confreg(void)
278{
279#ifdef CONFIG_CPU_R3000
280 extern unsigned long r3k_cache_size(unsigned long);
281 unsigned long size1, size2;
282 unsigned long cfg = read_c0_conf();
283
284 size1 = r3k_cache_size(ST0_ISC);
285 write_c0_conf(cfg ^ R30XX_CONF_AC);
286 size2 = r3k_cache_size(ST0_ISC);
287 write_c0_conf(cfg);
288 return size1 != size2;
289#else
290 return 0;
291#endif
292}
293
294/*
295 * Get the FPU Implementation/Revision.
296 */
297static inline unsigned long cpu_get_fpu_id(void)
298{
299 unsigned long tmp, fpu_id;
300
301 tmp = read_c0_status();
302 __enable_fpu();
303 fpu_id = read_32bit_cp1_register(CP1_REVISION);
304 write_c0_status(tmp);
305 return fpu_id;
306}
307
308/*
309 * Check the CPU has an FPU the official way.
310 */
311static inline int __cpu_has_fpu(void)
312{
313 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
314}
315
91dfc423
GR		 316static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
317{
318#ifdef __NEED_VMBITS_PROBE
5b7efa89 319 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 320 back_to_back_c0_hazard();
5b7efa89 321 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 322#endif
323}
324
02cf2119 325#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 326 | MIPS_CPU_COUNTER)
327
cea7e2df 328static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4
LT		 329{
330 switch (c->processor_id & 0xff00) {
331 case PRID_IMP_R2000:
332 c->cputype = CPU_R2000;
cea7e2df 333 __cpu_name[cpu] = "R2000";
1da177e4 334 c->isa_level = MIPS_CPU_ISA_I;
02cf2119
RB		 335 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
336 MIPS_CPU_NOFPUEX;
1da177e4
LT		 337 if (__cpu_has_fpu())
338 c->options |= MIPS_CPU_FPU;
339 c->tlbsize = 64;
340 break;
341 case PRID_IMP_R3000:
cea7e2df
RB		 342 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
343 if (cpu_has_confreg()) {
1da177e4 344 c->cputype = CPU_R3081E;
cea7e2df
RB		 345 __cpu_name[cpu] = "R3081";
346 } else {
1da177e4 347 c->cputype = CPU_R3000A;
cea7e2df
RB		 348 __cpu_name[cpu] = "R3000A";
349 }
350 break;
351 } else {
1da177e4 352 c->cputype = CPU_R3000;
cea7e2df
RB		 353 __cpu_name[cpu] = "R3000";
354 }
1da177e4 355 c->isa_level = MIPS_CPU_ISA_I;
02cf2119
RB		 356 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
357 MIPS_CPU_NOFPUEX;
1da177e4
LT		 358 if (__cpu_has_fpu())
359 c->options |= MIPS_CPU_FPU;
360 c->tlbsize = 64;
361 break;
362 case PRID_IMP_R4000:
363 if (read_c0_config() & CONF_SC) {
cea7e2df 364 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
1da177e4 365 c->cputype = CPU_R4400PC;
cea7e2df
RB		 366 __cpu_name[cpu] = "R4400PC";
367 } else {
1da177e4 368 c->cputype = CPU_R4000PC;
cea7e2df
RB		 369 __cpu_name[cpu] = "R4000PC";
370 }
1da177e4 371 } else {
cea7e2df 372 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
1da177e4 373 c->cputype = CPU_R4400SC;
cea7e2df
RB		 374 __cpu_name[cpu] = "R4400SC";
375 } else {
1da177e4 376 c->cputype = CPU_R4000SC;
cea7e2df
RB		 377 __cpu_name[cpu] = "R4000SC";
378 }
1da177e4
LT		 379 }
380
381 c->isa_level = MIPS_CPU_ISA_III;
382 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
383 MIPS_CPU_WATCH | MIPS_CPU_VCE |
384 MIPS_CPU_LLSC;
385 c->tlbsize = 48;
386 break;
387 case PRID_IMP_VR41XX:
388 switch (c->processor_id & 0xf0) {
1da177e4
LT		 389 case PRID_REV_VR4111:
390 c->cputype = CPU_VR4111;
cea7e2df 391 __cpu_name[cpu] = "NEC VR4111";
1da177e4 392 break;
1da177e4
LT		 393 case PRID_REV_VR4121:
394 c->cputype = CPU_VR4121;
cea7e2df 395 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 396 break;
397 case PRID_REV_VR4122:
cea7e2df 398 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 399 c->cputype = CPU_VR4122;
cea7e2df
RB		 400 __cpu_name[cpu] = "NEC VR4122";
401 } else {
1da177e4 402 c->cputype = CPU_VR4181A;
cea7e2df
RB		 403 __cpu_name[cpu] = "NEC VR4181A";
404 }
1da177e4
LT		 405 break;
406 case PRID_REV_VR4130:
cea7e2df 407 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 408 c->cputype = CPU_VR4131;
cea7e2df
RB		 409 __cpu_name[cpu] = "NEC VR4131";
410 } else {
1da177e4 411 c->cputype = CPU_VR4133;
cea7e2df
RB		 412 __cpu_name[cpu] = "NEC VR4133";
413 }
1da177e4
LT		 414 break;
415 default:
416 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
417 c->cputype = CPU_VR41XX;
cea7e2df 418 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 419 break;
420 }
421 c->isa_level = MIPS_CPU_ISA_III;
422 c->options = R4K_OPTS;
423 c->tlbsize = 32;
424 break;
425 case PRID_IMP_R4300:
426 c->cputype = CPU_R4300;
cea7e2df 427 __cpu_name[cpu] = "R4300";
1da177e4
LT		 428 c->isa_level = MIPS_CPU_ISA_III;
429 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
430 MIPS_CPU_LLSC;
431 c->tlbsize = 32;
432 break;
433 case PRID_IMP_R4600:
434 c->cputype = CPU_R4600;
cea7e2df 435 __cpu_name[cpu] = "R4600";
1da177e4 436 c->isa_level = MIPS_CPU_ISA_III;
075e7502
TS		 437 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
438 MIPS_CPU_LLSC;
1da177e4
LT		 439 c->tlbsize = 48;
440 break;
441 #if 0
442 case PRID_IMP_R4650:
443 /*
444 * This processor doesn't have an MMU, so it's not
445 * "real easy" to run Linux on it. It is left purely
446 * for documentation. Commented out because it shares
447 * it's c0_prid id number with the TX3900.
448 */
a3dddd56 449 c->cputype = CPU_R4650;
cea7e2df 450 __cpu_name[cpu] = "R4650";
1da177e4
LT		 451 c->isa_level = MIPS_CPU_ISA_III;
452 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
453 c->tlbsize = 48;
454 break;
455 #endif
456 case PRID_IMP_TX39:
457 c->isa_level = MIPS_CPU_ISA_I;
02cf2119 458 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 459
460 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
461 c->cputype = CPU_TX3927;
cea7e2df 462 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 463 c->tlbsize = 64;
464 } else {
465 switch (c->processor_id & 0xff) {
466 case PRID_REV_TX3912:
467 c->cputype = CPU_TX3912;
cea7e2df 468 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 469 c->tlbsize = 32;
470 break;
471 case PRID_REV_TX3922:
472 c->cputype = CPU_TX3922;
cea7e2df 473 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 474 c->tlbsize = 64;
475 break;
1da177e4
LT		 476 }
477 }
478 break;
479 case PRID_IMP_R4700:
480 c->cputype = CPU_R4700;
cea7e2df 481 __cpu_name[cpu] = "R4700";
1da177e4
LT		 482 c->isa_level = MIPS_CPU_ISA_III;
483 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
484 MIPS_CPU_LLSC;
485 c->tlbsize = 48;
486 break;
487 case PRID_IMP_TX49:
488 c->cputype = CPU_TX49XX;
cea7e2df 489 __cpu_name[cpu] = "R49XX";
1da177e4
LT		 490 c->isa_level = MIPS_CPU_ISA_III;
491 c->options = R4K_OPTS | MIPS_CPU_LLSC;
492 if (!(c->processor_id & 0x08))
493 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
494 c->tlbsize = 48;
495 break;
496 case PRID_IMP_R5000:
497 c->cputype = CPU_R5000;
cea7e2df 498 __cpu_name[cpu] = "R5000";
1da177e4
LT		 499 c->isa_level = MIPS_CPU_ISA_IV;
500 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
501 MIPS_CPU_LLSC;
502 c->tlbsize = 48;
503 break;
504 case PRID_IMP_R5432:
505 c->cputype = CPU_R5432;
cea7e2df 506 __cpu_name[cpu] = "R5432";
1da177e4
LT		 507 c->isa_level = MIPS_CPU_ISA_IV;
508 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
509 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
510 c->tlbsize = 48;
511 break;
512 case PRID_IMP_R5500:
513 c->cputype = CPU_R5500;
cea7e2df 514 __cpu_name[cpu] = "R5500";
1da177e4
LT		 515 c->isa_level = MIPS_CPU_ISA_IV;
516 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
517 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
518 c->tlbsize = 48;
519 break;
520 case PRID_IMP_NEVADA:
521 c->cputype = CPU_NEVADA;
cea7e2df 522 __cpu_name[cpu] = "Nevada";
1da177e4
LT		 523 c->isa_level = MIPS_CPU_ISA_IV;
524 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
525 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
526 c->tlbsize = 48;
527 break;
528 case PRID_IMP_R6000:
529 c->cputype = CPU_R6000;
cea7e2df 530 __cpu_name[cpu] = "R6000";
1da177e4
LT		 531 c->isa_level = MIPS_CPU_ISA_II;
532 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
533 MIPS_CPU_LLSC;
534 c->tlbsize = 32;
535 break;
536 case PRID_IMP_R6000A:
537 c->cputype = CPU_R6000A;
cea7e2df 538 __cpu_name[cpu] = "R6000A";
1da177e4
LT		 539 c->isa_level = MIPS_CPU_ISA_II;
540 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
541 MIPS_CPU_LLSC;
542 c->tlbsize = 32;
543 break;
544 case PRID_IMP_RM7000:
545 c->cputype = CPU_RM7000;
cea7e2df 546 __cpu_name[cpu] = "RM7000";
1da177e4
LT		 547 c->isa_level = MIPS_CPU_ISA_IV;
548 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
549 MIPS_CPU_LLSC;
550 /*
551 * Undocumented RM7000: Bit 29 in the info register of
552 * the RM7000 v2.0 indicates if the TLB has 48 or 64
553 * entries.
554 *
555 * 29 1 => 64 entry JTLB
556 * 0 => 48 entry JTLB
557 */
558 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
559 break;
560 case PRID_IMP_RM9000:
561 c->cputype = CPU_RM9000;
cea7e2df 562 __cpu_name[cpu] = "RM9000";
1da177e4
LT		 563 c->isa_level = MIPS_CPU_ISA_IV;
564 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
565 MIPS_CPU_LLSC;
566 /*
567 * Bit 29 in the info register of the RM9000
568 * indicates if the TLB has 48 or 64 entries.
569 *
570 * 29 1 => 64 entry JTLB
571 * 0 => 48 entry JTLB
572 */
573 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
574 break;
575 case PRID_IMP_R8000:
576 c->cputype = CPU_R8000;
cea7e2df 577 __cpu_name[cpu] = "RM8000";
1da177e4
LT		 578 c->isa_level = MIPS_CPU_ISA_IV;
579 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
580 MIPS_CPU_FPU | MIPS_CPU_32FPR |
581 MIPS_CPU_LLSC;
582 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
583 break;
584 case PRID_IMP_R10000:
585 c->cputype = CPU_R10000;
cea7e2df 586 __cpu_name[cpu] = "R10000";
1da177e4 587 c->isa_level = MIPS_CPU_ISA_IV;
8b36612a 588 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1da177e4
LT		 589 MIPS_CPU_FPU | MIPS_CPU_32FPR |
590 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
591 MIPS_CPU_LLSC;
592 c->tlbsize = 64;
593 break;
594 case PRID_IMP_R12000:
595 c->cputype = CPU_R12000;
cea7e2df 596 __cpu_name[cpu] = "R12000";
1da177e4 597 c->isa_level = MIPS_CPU_ISA_IV;
8b36612a 598 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1da177e4
LT		 599 MIPS_CPU_FPU | MIPS_CPU_32FPR |
600 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
601 MIPS_CPU_LLSC;
602 c->tlbsize = 64;
603 break;
44d921b2
K		 604 case PRID_IMP_R14000:
605 c->cputype = CPU_R14000;
cea7e2df 606 __cpu_name[cpu] = "R14000";
44d921b2
K		 607 c->isa_level = MIPS_CPU_ISA_IV;
608 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
609 MIPS_CPU_FPU | MIPS_CPU_32FPR |
610 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
611 MIPS_CPU_LLSC;
612 c->tlbsize = 64;
613 break;
2a21c730
FZ		 614 case PRID_IMP_LOONGSON2:
615 c->cputype = CPU_LOONGSON2;
cea7e2df 616 __cpu_name[cpu] = "ICT Loongson-2";
2a21c730
FZ		 617 c->isa_level = MIPS_CPU_ISA_III;
618 c->options = R4K_OPTS |
619 MIPS_CPU_FPU | MIPS_CPU_LLSC |
620 MIPS_CPU_32FPR;
621 c->tlbsize = 64;
622 break;
1da177e4
LT		 623 }
624}
625
234fcd14 626static char unknown_isa[] __cpuinitdata = KERN_ERR \
b4672d37
RB		 627 "Unsupported ISA type, c0.config0: %d.";
628
4194318c 629static inline unsigned int decode_config0(struct cpuinfo_mips *c)
1da177e4 630{
4194318c
RB		 631 unsigned int config0;
632 int isa;
1da177e4 633
4194318c
RB		 634 config0 = read_c0_config();
635
636 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
02cf2119 637 c->options |= MIPS_CPU_TLB;
4194318c
RB		 638 isa = (config0 & MIPS_CONF_AT) >> 13;
639 switch (isa) {
640 case 0:
3a01c49a 641 switch ((config0 & MIPS_CONF_AR) >> 10) {
b4672d37
RB		 642 case 0:
643 c->isa_level = MIPS_CPU_ISA_M32R1;
644 break;
645 case 1:
646 c->isa_level = MIPS_CPU_ISA_M32R2;
647 break;
648 default:
649 goto unknown;
650 }
4194318c
RB		 651 break;
652 case 2:
3a01c49a 653 switch ((config0 & MIPS_CONF_AR) >> 10) {
b4672d37
RB		 654 case 0:
655 c->isa_level = MIPS_CPU_ISA_M64R1;
656 break;
657 case 1:
658 c->isa_level = MIPS_CPU_ISA_M64R2;
659 break;
660 default:
661 goto unknown;
662 }
4194318c
RB		 663 break;
664 default:
b4672d37 665 goto unknown;
4194318c
RB		 666 }
667
668 return config0 & MIPS_CONF_M;
b4672d37
RB		 669
670unknown:
671 panic(unknown_isa, config0);
4194318c
RB		 672}
673
674static inline unsigned int decode_config1(struct cpuinfo_mips *c)
675{
676 unsigned int config1;
1da177e4 677
1da177e4 678 config1 = read_c0_config1();
4194318c
RB		 679
680 if (config1 & MIPS_CONF1_MD)
681 c->ases |= MIPS_ASE_MDMX;
682 if (config1 & MIPS_CONF1_WR)
1da177e4 683 c->options |= MIPS_CPU_WATCH;
4194318c
RB		 684 if (config1 & MIPS_CONF1_CA)
685 c->ases |= MIPS_ASE_MIPS16;
686 if (config1 & MIPS_CONF1_EP)
1da177e4 687 c->options |= MIPS_CPU_EJTAG;
4194318c 688 if (config1 & MIPS_CONF1_FP) {
1da177e4
LT		 689 c->options |= MIPS_CPU_FPU;
690 c->options |= MIPS_CPU_32FPR;
691 }
4194318c
RB		 692 if (cpu_has_tlb)
693 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
694
695 return config1 & MIPS_CONF_M;
696}
697
698static inline unsigned int decode_config2(struct cpuinfo_mips *c)
699{
700 unsigned int config2;
701
702 config2 = read_c0_config2();
703
704 if (config2 & MIPS_CONF2_SL)
705 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
706
707 return config2 & MIPS_CONF_M;
708}
709
710static inline unsigned int decode_config3(struct cpuinfo_mips *c)
711{
712 unsigned int config3;
713
714 config3 = read_c0_config3();
715
716 if (config3 & MIPS_CONF3_SM)
717 c->ases |= MIPS_ASE_SMARTMIPS;
e50c0a8f
RB		 718 if (config3 & MIPS_CONF3_DSP)
719 c->ases |= MIPS_ASE_DSP;
8f40611d
RB		 720 if (config3 & MIPS_CONF3_VINT)
721 c->options |= MIPS_CPU_VINT;
722 if (config3 & MIPS_CONF3_VEIC)
723 c->options |= MIPS_CPU_VEIC;
724 if (config3 & MIPS_CONF3_MT)
e0daad44 725 c->ases |= MIPS_ASE_MIPSMT;
a3692020
RB		 726 if (config3 & MIPS_CONF3_ULRI)
727 c->options |= MIPS_CPU_ULRI;
4194318c
RB		 728
729 return config3 & MIPS_CONF_M;
730}
731
1b362e3e
DD		 732static inline unsigned int decode_config4(struct cpuinfo_mips *c)
733{
734 unsigned int config4;
735
736 config4 = read_c0_config4();
737
738 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
739 && cpu_has_tlb)
740 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
741
742 return config4 & MIPS_CONF_M;
743}
744
234fcd14 745static void __cpuinit decode_configs(struct cpuinfo_mips *c)
4194318c 746{
558ce124
RB		 747 int ok;
748
4194318c 749 /* MIPS32 or MIPS64 compliant CPU. */
02cf2119
RB		 750 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
751 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
4194318c 752
1da177e4
LT		 753 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
754
558ce124
RB		 755 ok = decode_config0(c); /* Read Config registers. */
756 BUG_ON(!ok); /* Arch spec violation! */
757 if (ok)
758 ok = decode_config1(c);
759 if (ok)
760 ok = decode_config2(c);
761 if (ok)
762 ok = decode_config3(c);
1b362e3e
DD		 763 if (ok)
764 ok = decode_config4(c);
558ce124
RB		 765
766 mips_probe_watch_registers(c);
0c2f4551
DD		 767
768 if (cpu_has_mips_r2)
769 c->core = read_c0_ebase() & 0x3ff;
1da177e4
LT		 770}
771
cea7e2df 772static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 773{
4194318c 774 decode_configs(c);
1da177e4
LT		 775 switch (c->processor_id & 0xff00) {
776 case PRID_IMP_4KC:
777 c->cputype = CPU_4KC;
cea7e2df 778 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 779 break;
780 case PRID_IMP_4KEC:
2b07bd02
RB		 781 case PRID_IMP_4KECR2:
782 c->cputype = CPU_4KEC;
cea7e2df 783 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 784 break;
1da177e4 785 case PRID_IMP_4KSC:
8afcb5d8 786 case PRID_IMP_4KSD:
1da177e4 787 c->cputype = CPU_4KSC;
cea7e2df 788 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 789 break;
790 case PRID_IMP_5KC:
791 c->cputype = CPU_5KC;
cea7e2df 792 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4
LT		 793 break;
794 case PRID_IMP_20KC:
795 c->cputype = CPU_20KC;
cea7e2df 796 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 797 break;
798 case PRID_IMP_24K:
e50c0a8f 799 case PRID_IMP_24KE:
1da177e4 800 c->cputype = CPU_24K;
cea7e2df 801 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4
LT		 802 break;
803 case PRID_IMP_25KF:
804 c->cputype = CPU_25KF;
cea7e2df 805 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 806 break;
bbc7f22f
RB		 807 case PRID_IMP_34K:
808 c->cputype = CPU_34K;
cea7e2df 809 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 810 break;
c620953c
CD		 811 case PRID_IMP_74K:
812 c->cputype = CPU_74K;
cea7e2df 813 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 814 break;
39b8d525
RB		 815 case PRID_IMP_1004K:
816 c->cputype = CPU_1004K;
cea7e2df 817 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 818 break;
1da177e4 819 }
0b6d497f
CD		 820
821 spram_config();
1da177e4
LT		 822}
823
cea7e2df 824static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 825{
4194318c 826 decode_configs(c);
1da177e4
LT		 827 switch (c->processor_id & 0xff00) {
828 case PRID_IMP_AU1_REV1:
829 case PRID_IMP_AU1_REV2:
270717a8 830 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 831 switch ((c->processor_id >> 24) & 0xff) {
832 case 0:
cea7e2df 833 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 834 break;
835 case 1:
cea7e2df 836 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 837 break;
838 case 2:
cea7e2df 839 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 840 break;
841 case 3:
cea7e2df 842 __cpu_name[cpu] = "Au1550";
1da177e4 843 break;
e3ad1c23 844 case 4:
cea7e2df 845 __cpu_name[cpu] = "Au1200";
270717a8 846 if ((c->processor_id & 0xff) == 2)
cea7e2df 847 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 848 break;
849 case 5:
cea7e2df 850 __cpu_name[cpu] = "Au1210";
e3ad1c23 851 break;
1da177e4 852 default:
270717a8 853 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 854 break;
855 }
1da177e4
LT		 856 break;
857 }
858}
859
cea7e2df 860static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 861{
4194318c 862 decode_configs(c);
02cf2119 863
1da177e4
LT		 864 switch (c->processor_id & 0xff00) {
865 case PRID_IMP_SB1:
866 c->cputype = CPU_SB1;
cea7e2df 867 __cpu_name[cpu] = "SiByte SB1";
1da177e4 868 /* FPU in pass1 is known to have issues. */
aa32374a 869 if ((c->processor_id & 0xff) < 0x02)
010b853b 870 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 871 break;
93ce2f52
AI		 872 case PRID_IMP_SB1A:
873 c->cputype = CPU_SB1A;
cea7e2df 874 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 875 break;
1da177e4
LT		 876 }
877}
878
cea7e2df 879static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 880{
4194318c 881 decode_configs(c);
1da177e4
LT		 882 switch (c->processor_id & 0xff00) {
883 case PRID_IMP_SR71000:
884 c->cputype = CPU_SR71000;
cea7e2df 885 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 886 c->scache.ways = 8;
887 c->tlbsize = 64;
888 break;
889 }
890}
891
cea7e2df 892static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 893{
894 decode_configs(c);
895 switch (c->processor_id & 0xff00) {
896 case PRID_IMP_PR4450:
897 c->cputype = CPU_PR4450;
cea7e2df 898 __cpu_name[cpu] = "Philips PR4450";
e7958bb9 899 c->isa_level = MIPS_CPU_ISA_M32R1;
bdf21b18 900 break;
bdf21b18
PP		 901 }
902}
903
cea7e2df 904static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 905{
906 decode_configs(c);
907 switch (c->processor_id & 0xff00) {
602977b0
KC		 908 case PRID_IMP_BMIPS32:
909 c->cputype = CPU_BMIPS32;
910 __cpu_name[cpu] = "Broadcom BMIPS32";
911 break;
912 case PRID_IMP_BMIPS3300:
913 case PRID_IMP_BMIPS3300_ALT:
914 case PRID_IMP_BMIPS3300_BUG:
915 c->cputype = CPU_BMIPS3300;
916 __cpu_name[cpu] = "Broadcom BMIPS3300";
917 break;
918 case PRID_IMP_BMIPS43XX: {
919 int rev = c->processor_id & 0xff;
920
921 if (rev >= PRID_REV_BMIPS4380_LO &&
922 rev <= PRID_REV_BMIPS4380_HI) {
923 c->cputype = CPU_BMIPS4380;
924 __cpu_name[cpu] = "Broadcom BMIPS4380";
925 } else {
926 c->cputype = CPU_BMIPS4350;
927 __cpu_name[cpu] = "Broadcom BMIPS4350";
928 }
0de663ef 929 break;
602977b0
KC		 930 }
931 case PRID_IMP_BMIPS5000:
932 c->cputype = CPU_BMIPS5000;
933 __cpu_name[cpu] = "Broadcom BMIPS5000";
934 c->options |= MIPS_CPU_ULRI;
0de663ef 935 break;
602977b0
KC		 936 case PRID_IMP_BMIPS4KC:
937 c->cputype = CPU_4KC;
938 __cpu_name[cpu] = "MIPS 4Kc";
0de663ef 939 break;
1c0c13eb
AJ		 940 }
941}
942
0dd4781b
DD		 943static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
944{
945 decode_configs(c);
946 switch (c->processor_id & 0xff00) {
947 case PRID_IMP_CAVIUM_CN38XX:
948 case PRID_IMP_CAVIUM_CN31XX:
949 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 950 c->cputype = CPU_CAVIUM_OCTEON;
951 __cpu_name[cpu] = "Cavium Octeon";
952 goto platform;
0dd4781b
DD		 953 case PRID_IMP_CAVIUM_CN58XX:
954 case PRID_IMP_CAVIUM_CN56XX:
955 case PRID_IMP_CAVIUM_CN50XX:
956 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 957 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
958 __cpu_name[cpu] = "Cavium Octeon+";
959platform:
368bf8ef
DD		 960 if (cpu == 0)
961 __elf_platform = "octeon";
0dd4781b 962 break;
0e56b385
DD		 963 case PRID_IMP_CAVIUM_CN63XX:
964 c->cputype = CPU_CAVIUM_OCTEON2;
965 __cpu_name[cpu] = "Cavium Octeon II";
966 if (cpu == 0)
967 __elf_platform = "octeon2";
968 break;
0dd4781b
DD		 969 default:
970 printk(KERN_INFO "Unknown Octeon chip!\n");
971 c->cputype = CPU_UNKNOWN;
972 break;
973 }
974}
975
83ccf69d
LPC		 976static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
977{
978 decode_configs(c);
979 /* JZRISC does not implement the CP0 counter. */
980 c->options &= ~MIPS_CPU_COUNTER;
981 switch (c->processor_id & 0xff00) {
982 case PRID_IMP_JZRISC:
983 c->cputype = CPU_JZRISC;
984 __cpu_name[cpu] = "Ingenic JZRISC";
985 break;
986 default:
987 panic("Unknown Ingenic Processor ID!");
988 break;
989 }
990}
991
949e51be
DD		 992#ifdef CONFIG_64BIT
993/* For use by uaccess.h */
994u64 __ua_limit;
995EXPORT_SYMBOL(__ua_limit);
996#endif
997
9966db25 998const char *__cpu_name[NR_CPUS];
874fd3b5 999const char *__elf_platform;
9966db25 1000
234fcd14 1001__cpuinit void cpu_probe(void)
1da177e4
LT		 1002{
1003 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1004 unsigned int cpu = smp_processor_id();
1da177e4
LT		 1005
1006 c->processor_id = PRID_IMP_UNKNOWN;
1007 c->fpu_id = FPIR_IMP_NONE;
1008 c->cputype = CPU_UNKNOWN;
1009
1010 c->processor_id = read_c0_prid();
1011 switch (c->processor_id & 0xff0000) {
1012 case PRID_COMP_LEGACY:
cea7e2df 1013 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1014 break;
1015 case PRID_COMP_MIPS:
cea7e2df 1016 cpu_probe_mips(c, cpu);
1da177e4
LT		 1017 break;
1018 case PRID_COMP_ALCHEMY:
cea7e2df 1019 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1020 break;
1021 case PRID_COMP_SIBYTE:
cea7e2df 1022 cpu_probe_sibyte(c, cpu);
1da177e4 1023 break;
1c0c13eb 1024 case PRID_COMP_BROADCOM:
cea7e2df 1025 cpu_probe_broadcom(c, cpu);
1c0c13eb 1026 break;
1da177e4 1027 case PRID_COMP_SANDCRAFT:
cea7e2df 1028 cpu_probe_sandcraft(c, cpu);
1da177e4 1029 break;
a92b0588 1030 case PRID_COMP_NXP:
cea7e2df 1031 cpu_probe_nxp(c, cpu);
a3dddd56 1032 break;
0dd4781b
DD		 1033 case PRID_COMP_CAVIUM:
1034 cpu_probe_cavium(c, cpu);
1035 break;
83ccf69d
LPC		 1036 case PRID_COMP_INGENIC:
1037 cpu_probe_ingenic(c, cpu);
1038 break;
1da177e4 1039 }
dec8b1ca 1040
cea7e2df
RB		 1041 BUG_ON(!__cpu_name[cpu]);
1042 BUG_ON(c->cputype == CPU_UNKNOWN);
1043
dec8b1ca
FBH		 1044 /*
1045 * Platform code can force the cpu type to optimize code
1046 * generation. In that case be sure the cpu type is correctly
1047 * manually setup otherwise it could trigger some nasty bugs.
1048 */
1049 BUG_ON(current_cpu_type() != c->cputype);
1050
0103d23f
KC		 1051 if (mips_fpu_disabled)
1052 c->options &= ~MIPS_CPU_FPU;
1053
1054 if (mips_dsp_disabled)
1055 c->ases &= ~MIPS_ASE_DSP;
1056
4194318c 1057 if (c->options & MIPS_CPU_FPU) {
1da177e4 1058 c->fpu_id = cpu_get_fpu_id();
4194318c 1059
e7958bb9 1060 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
b4672d37
RB		 1061 c->isa_level == MIPS_CPU_ISA_M32R2 ||
1062 c->isa_level == MIPS_CPU_ISA_M64R1 ||
1063 c->isa_level == MIPS_CPU_ISA_M64R2) {
4194318c
RB		 1064 if (c->fpu_id & MIPS_FPIR_3D)
1065 c->ases |= MIPS_ASE_MIPS3D;
1066 }
1067 }
9966db25 1068
f6771dbb
RB		 1069 if (cpu_has_mips_r2)
1070 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1071 else
1072 c->srsets = 1;
91dfc423
GR		 1073
1074 cpu_probe_vmbits(c);
949e51be
DD		 1075
1076#ifdef CONFIG_64BIT
1077 if (cpu == 0)
1078 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1079#endif
1da177e4
LT		 1080}
1081
234fcd14 1082__cpuinit void cpu_report(void)
1da177e4
LT		 1083{
1084 struct cpuinfo_mips *c = &current_cpu_data;
1085
9966db25
RB		 1086 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1087 c->processor_id, cpu_name_string());
1da177e4 1088 if (c->options & MIPS_CPU_FPU)
9966db25 1089 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1da177e4 1090}
Clone of davem's net-next-2.6 tree