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1 | /***********************license start*************** |
2 | * Author: Cavium Networks | |
3 | * | |
4 | * Contact: support@caviumnetworks.com | |
5 | * This file is part of the OCTEON SDK | |
6 | * | |
aa32a955 | 7 | * Copyright (c) 2003-2010 Cavium Networks |
8860fb82 DD |
8 | * |
9 | * This file is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License, Version 2, as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This file is distributed in the hope that it will be useful, but | |
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | |
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | |
16 | * NONINFRINGEMENT. See the GNU General Public License for more | |
17 | * details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this file; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
22 | * or visit http://www.gnu.org/licenses/. | |
23 | * | |
24 | * This file may also be available under a different license from Cavium. | |
25 | * Contact Cavium Networks for more information | |
26 | ***********************license end**************************************/ | |
27 | ||
28 | #ifndef __CVMX_PCI_DEFS_H__ | |
29 | #define __CVMX_PCI_DEFS_H__ | |
30 | ||
aa32a955 DD |
31 | #define CVMX_PCI_BAR1_INDEXX(offset) (0x0000000000000100ull + ((offset) & 31) * 4) |
32 | #define CVMX_PCI_BIST_REG (0x00000000000001C0ull) | |
33 | #define CVMX_PCI_CFG00 (0x0000000000000000ull) | |
34 | #define CVMX_PCI_CFG01 (0x0000000000000004ull) | |
35 | #define CVMX_PCI_CFG02 (0x0000000000000008ull) | |
36 | #define CVMX_PCI_CFG03 (0x000000000000000Cull) | |
37 | #define CVMX_PCI_CFG04 (0x0000000000000010ull) | |
38 | #define CVMX_PCI_CFG05 (0x0000000000000014ull) | |
39 | #define CVMX_PCI_CFG06 (0x0000000000000018ull) | |
40 | #define CVMX_PCI_CFG07 (0x000000000000001Cull) | |
41 | #define CVMX_PCI_CFG08 (0x0000000000000020ull) | |
42 | #define CVMX_PCI_CFG09 (0x0000000000000024ull) | |
43 | #define CVMX_PCI_CFG10 (0x0000000000000028ull) | |
44 | #define CVMX_PCI_CFG11 (0x000000000000002Cull) | |
45 | #define CVMX_PCI_CFG12 (0x0000000000000030ull) | |
46 | #define CVMX_PCI_CFG13 (0x0000000000000034ull) | |
47 | #define CVMX_PCI_CFG15 (0x000000000000003Cull) | |
48 | #define CVMX_PCI_CFG16 (0x0000000000000040ull) | |
49 | #define CVMX_PCI_CFG17 (0x0000000000000044ull) | |
50 | #define CVMX_PCI_CFG18 (0x0000000000000048ull) | |
51 | #define CVMX_PCI_CFG19 (0x000000000000004Cull) | |
52 | #define CVMX_PCI_CFG20 (0x0000000000000050ull) | |
53 | #define CVMX_PCI_CFG21 (0x0000000000000054ull) | |
54 | #define CVMX_PCI_CFG22 (0x0000000000000058ull) | |
55 | #define CVMX_PCI_CFG56 (0x00000000000000E0ull) | |
56 | #define CVMX_PCI_CFG57 (0x00000000000000E4ull) | |
57 | #define CVMX_PCI_CFG58 (0x00000000000000E8ull) | |
58 | #define CVMX_PCI_CFG59 (0x00000000000000ECull) | |
59 | #define CVMX_PCI_CFG60 (0x00000000000000F0ull) | |
60 | #define CVMX_PCI_CFG61 (0x00000000000000F4ull) | |
61 | #define CVMX_PCI_CFG62 (0x00000000000000F8ull) | |
62 | #define CVMX_PCI_CFG63 (0x00000000000000FCull) | |
63 | #define CVMX_PCI_CNT_REG (0x00000000000001B8ull) | |
64 | #define CVMX_PCI_CTL_STATUS_2 (0x000000000000018Cull) | |
65 | #define CVMX_PCI_DBELL_X(offset) (0x0000000000000080ull + ((offset) & 3) * 8) | |
66 | #define CVMX_PCI_DMA_CNT0 CVMX_PCI_DMA_CNTX(0) | |
67 | #define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1) | |
68 | #define CVMX_PCI_DMA_CNTX(offset) (0x00000000000000A0ull + ((offset) & 1) * 8) | |
69 | #define CVMX_PCI_DMA_INT_LEV0 CVMX_PCI_DMA_INT_LEVX(0) | |
70 | #define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1) | |
71 | #define CVMX_PCI_DMA_INT_LEVX(offset) (0x00000000000000A4ull + ((offset) & 1) * 8) | |
72 | #define CVMX_PCI_DMA_TIME0 CVMX_PCI_DMA_TIMEX(0) | |
73 | #define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1) | |
74 | #define CVMX_PCI_DMA_TIMEX(offset) (0x00000000000000B0ull + ((offset) & 1) * 4) | |
75 | #define CVMX_PCI_INSTR_COUNT0 CVMX_PCI_INSTR_COUNTX(0) | |
76 | #define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1) | |
77 | #define CVMX_PCI_INSTR_COUNT2 CVMX_PCI_INSTR_COUNTX(2) | |
78 | #define CVMX_PCI_INSTR_COUNT3 CVMX_PCI_INSTR_COUNTX(3) | |
79 | #define CVMX_PCI_INSTR_COUNTX(offset) (0x0000000000000084ull + ((offset) & 3) * 8) | |
80 | #define CVMX_PCI_INT_ENB (0x0000000000000038ull) | |
81 | #define CVMX_PCI_INT_ENB2 (0x00000000000001A0ull) | |
82 | #define CVMX_PCI_INT_SUM (0x0000000000000030ull) | |
83 | #define CVMX_PCI_INT_SUM2 (0x0000000000000198ull) | |
84 | #define CVMX_PCI_MSI_RCV (0x00000000000000F0ull) | |
85 | #define CVMX_PCI_PKTS_SENT0 CVMX_PCI_PKTS_SENTX(0) | |
86 | #define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1) | |
87 | #define CVMX_PCI_PKTS_SENT2 CVMX_PCI_PKTS_SENTX(2) | |
88 | #define CVMX_PCI_PKTS_SENT3 CVMX_PCI_PKTS_SENTX(3) | |
89 | #define CVMX_PCI_PKTS_SENTX(offset) (0x0000000000000040ull + ((offset) & 3) * 16) | |
90 | #define CVMX_PCI_PKTS_SENT_INT_LEV0 CVMX_PCI_PKTS_SENT_INT_LEVX(0) | |
91 | #define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1) | |
92 | #define CVMX_PCI_PKTS_SENT_INT_LEV2 CVMX_PCI_PKTS_SENT_INT_LEVX(2) | |
93 | #define CVMX_PCI_PKTS_SENT_INT_LEV3 CVMX_PCI_PKTS_SENT_INT_LEVX(3) | |
94 | #define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) (0x0000000000000048ull + ((offset) & 3) * 16) | |
95 | #define CVMX_PCI_PKTS_SENT_TIME0 CVMX_PCI_PKTS_SENT_TIMEX(0) | |
96 | #define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1) | |
97 | #define CVMX_PCI_PKTS_SENT_TIME2 CVMX_PCI_PKTS_SENT_TIMEX(2) | |
98 | #define CVMX_PCI_PKTS_SENT_TIME3 CVMX_PCI_PKTS_SENT_TIMEX(3) | |
99 | #define CVMX_PCI_PKTS_SENT_TIMEX(offset) (0x000000000000004Cull + ((offset) & 3) * 16) | |
100 | #define CVMX_PCI_PKT_CREDITS0 CVMX_PCI_PKT_CREDITSX(0) | |
101 | #define CVMX_PCI_PKT_CREDITS1 CVMX_PCI_PKT_CREDITSX(1) | |
102 | #define CVMX_PCI_PKT_CREDITS2 CVMX_PCI_PKT_CREDITSX(2) | |
103 | #define CVMX_PCI_PKT_CREDITS3 CVMX_PCI_PKT_CREDITSX(3) | |
104 | #define CVMX_PCI_PKT_CREDITSX(offset) (0x0000000000000044ull + ((offset) & 3) * 16) | |
105 | #define CVMX_PCI_READ_CMD_6 (0x0000000000000180ull) | |
106 | #define CVMX_PCI_READ_CMD_C (0x0000000000000184ull) | |
107 | #define CVMX_PCI_READ_CMD_E (0x0000000000000188ull) | |
108 | #define CVMX_PCI_READ_TIMEOUT (CVMX_ADD_IO_SEG(0x00011F00000000B0ull)) | |
109 | #define CVMX_PCI_SCM_REG (0x00000000000001A8ull) | |
110 | #define CVMX_PCI_TSR_REG (0x00000000000001B0ull) | |
111 | #define CVMX_PCI_WIN_RD_ADDR (0x0000000000000008ull) | |
112 | #define CVMX_PCI_WIN_RD_DATA (0x0000000000000020ull) | |
113 | #define CVMX_PCI_WIN_WR_ADDR (0x0000000000000000ull) | |
114 | #define CVMX_PCI_WIN_WR_DATA (0x0000000000000010ull) | |
115 | #define CVMX_PCI_WIN_WR_MASK (0x0000000000000018ull) | |
8860fb82 DD |
116 | |
117 | union cvmx_pci_bar1_indexx { | |
118 | uint32_t u32; | |
119 | struct cvmx_pci_bar1_indexx_s { | |
120 | uint32_t reserved_18_31:14; | |
121 | uint32_t addr_idx:14; | |
122 | uint32_t ca:1; | |
123 | uint32_t end_swp:2; | |
124 | uint32_t addr_v:1; | |
125 | } s; | |
126 | struct cvmx_pci_bar1_indexx_s cn30xx; | |
127 | struct cvmx_pci_bar1_indexx_s cn31xx; | |
128 | struct cvmx_pci_bar1_indexx_s cn38xx; | |
129 | struct cvmx_pci_bar1_indexx_s cn38xxp2; | |
130 | struct cvmx_pci_bar1_indexx_s cn50xx; | |
131 | struct cvmx_pci_bar1_indexx_s cn58xx; | |
132 | struct cvmx_pci_bar1_indexx_s cn58xxp1; | |
133 | }; | |
134 | ||
135 | union cvmx_pci_bist_reg { | |
136 | uint64_t u64; | |
137 | struct cvmx_pci_bist_reg_s { | |
138 | uint64_t reserved_10_63:54; | |
139 | uint64_t rsp_bs:1; | |
140 | uint64_t dma0_bs:1; | |
141 | uint64_t cmd0_bs:1; | |
142 | uint64_t cmd_bs:1; | |
143 | uint64_t csr2p_bs:1; | |
144 | uint64_t csrr_bs:1; | |
145 | uint64_t rsp2p_bs:1; | |
146 | uint64_t csr2n_bs:1; | |
147 | uint64_t dat2n_bs:1; | |
148 | uint64_t dbg2n_bs:1; | |
149 | } s; | |
150 | struct cvmx_pci_bist_reg_s cn50xx; | |
151 | }; | |
152 | ||
153 | union cvmx_pci_cfg00 { | |
154 | uint32_t u32; | |
155 | struct cvmx_pci_cfg00_s { | |
156 | uint32_t devid:16; | |
157 | uint32_t vendid:16; | |
158 | } s; | |
159 | struct cvmx_pci_cfg00_s cn30xx; | |
160 | struct cvmx_pci_cfg00_s cn31xx; | |
161 | struct cvmx_pci_cfg00_s cn38xx; | |
162 | struct cvmx_pci_cfg00_s cn38xxp2; | |
163 | struct cvmx_pci_cfg00_s cn50xx; | |
164 | struct cvmx_pci_cfg00_s cn58xx; | |
165 | struct cvmx_pci_cfg00_s cn58xxp1; | |
166 | }; | |
167 | ||
168 | union cvmx_pci_cfg01 { | |
169 | uint32_t u32; | |
170 | struct cvmx_pci_cfg01_s { | |
171 | uint32_t dpe:1; | |
172 | uint32_t sse:1; | |
173 | uint32_t rma:1; | |
174 | uint32_t rta:1; | |
175 | uint32_t sta:1; | |
176 | uint32_t devt:2; | |
177 | uint32_t mdpe:1; | |
178 | uint32_t fbb:1; | |
179 | uint32_t reserved_22_22:1; | |
180 | uint32_t m66:1; | |
181 | uint32_t cle:1; | |
182 | uint32_t i_stat:1; | |
183 | uint32_t reserved_11_18:8; | |
184 | uint32_t i_dis:1; | |
185 | uint32_t fbbe:1; | |
186 | uint32_t see:1; | |
187 | uint32_t ads:1; | |
188 | uint32_t pee:1; | |
189 | uint32_t vps:1; | |
190 | uint32_t mwice:1; | |
191 | uint32_t scse:1; | |
192 | uint32_t me:1; | |
193 | uint32_t msae:1; | |
194 | uint32_t isae:1; | |
195 | } s; | |
196 | struct cvmx_pci_cfg01_s cn30xx; | |
197 | struct cvmx_pci_cfg01_s cn31xx; | |
198 | struct cvmx_pci_cfg01_s cn38xx; | |
199 | struct cvmx_pci_cfg01_s cn38xxp2; | |
200 | struct cvmx_pci_cfg01_s cn50xx; | |
201 | struct cvmx_pci_cfg01_s cn58xx; | |
202 | struct cvmx_pci_cfg01_s cn58xxp1; | |
203 | }; | |
204 | ||
205 | union cvmx_pci_cfg02 { | |
206 | uint32_t u32; | |
207 | struct cvmx_pci_cfg02_s { | |
208 | uint32_t cc:24; | |
209 | uint32_t rid:8; | |
210 | } s; | |
211 | struct cvmx_pci_cfg02_s cn30xx; | |
212 | struct cvmx_pci_cfg02_s cn31xx; | |
213 | struct cvmx_pci_cfg02_s cn38xx; | |
214 | struct cvmx_pci_cfg02_s cn38xxp2; | |
215 | struct cvmx_pci_cfg02_s cn50xx; | |
216 | struct cvmx_pci_cfg02_s cn58xx; | |
217 | struct cvmx_pci_cfg02_s cn58xxp1; | |
218 | }; | |
219 | ||
220 | union cvmx_pci_cfg03 { | |
221 | uint32_t u32; | |
222 | struct cvmx_pci_cfg03_s { | |
223 | uint32_t bcap:1; | |
224 | uint32_t brb:1; | |
225 | uint32_t reserved_28_29:2; | |
226 | uint32_t bcod:4; | |
227 | uint32_t ht:8; | |
228 | uint32_t lt:8; | |
229 | uint32_t cls:8; | |
230 | } s; | |
231 | struct cvmx_pci_cfg03_s cn30xx; | |
232 | struct cvmx_pci_cfg03_s cn31xx; | |
233 | struct cvmx_pci_cfg03_s cn38xx; | |
234 | struct cvmx_pci_cfg03_s cn38xxp2; | |
235 | struct cvmx_pci_cfg03_s cn50xx; | |
236 | struct cvmx_pci_cfg03_s cn58xx; | |
237 | struct cvmx_pci_cfg03_s cn58xxp1; | |
238 | }; | |
239 | ||
240 | union cvmx_pci_cfg04 { | |
241 | uint32_t u32; | |
242 | struct cvmx_pci_cfg04_s { | |
243 | uint32_t lbase:20; | |
244 | uint32_t lbasez:8; | |
245 | uint32_t pf:1; | |
246 | uint32_t typ:2; | |
247 | uint32_t mspc:1; | |
248 | } s; | |
249 | struct cvmx_pci_cfg04_s cn30xx; | |
250 | struct cvmx_pci_cfg04_s cn31xx; | |
251 | struct cvmx_pci_cfg04_s cn38xx; | |
252 | struct cvmx_pci_cfg04_s cn38xxp2; | |
253 | struct cvmx_pci_cfg04_s cn50xx; | |
254 | struct cvmx_pci_cfg04_s cn58xx; | |
255 | struct cvmx_pci_cfg04_s cn58xxp1; | |
256 | }; | |
257 | ||
258 | union cvmx_pci_cfg05 { | |
259 | uint32_t u32; | |
260 | struct cvmx_pci_cfg05_s { | |
261 | uint32_t hbase:32; | |
262 | } s; | |
263 | struct cvmx_pci_cfg05_s cn30xx; | |
264 | struct cvmx_pci_cfg05_s cn31xx; | |
265 | struct cvmx_pci_cfg05_s cn38xx; | |
266 | struct cvmx_pci_cfg05_s cn38xxp2; | |
267 | struct cvmx_pci_cfg05_s cn50xx; | |
268 | struct cvmx_pci_cfg05_s cn58xx; | |
269 | struct cvmx_pci_cfg05_s cn58xxp1; | |
270 | }; | |
271 | ||
272 | union cvmx_pci_cfg06 { | |
273 | uint32_t u32; | |
274 | struct cvmx_pci_cfg06_s { | |
275 | uint32_t lbase:5; | |
276 | uint32_t lbasez:23; | |
277 | uint32_t pf:1; | |
278 | uint32_t typ:2; | |
279 | uint32_t mspc:1; | |
280 | } s; | |
281 | struct cvmx_pci_cfg06_s cn30xx; | |
282 | struct cvmx_pci_cfg06_s cn31xx; | |
283 | struct cvmx_pci_cfg06_s cn38xx; | |
284 | struct cvmx_pci_cfg06_s cn38xxp2; | |
285 | struct cvmx_pci_cfg06_s cn50xx; | |
286 | struct cvmx_pci_cfg06_s cn58xx; | |
287 | struct cvmx_pci_cfg06_s cn58xxp1; | |
288 | }; | |
289 | ||
290 | union cvmx_pci_cfg07 { | |
291 | uint32_t u32; | |
292 | struct cvmx_pci_cfg07_s { | |
293 | uint32_t hbase:32; | |
294 | } s; | |
295 | struct cvmx_pci_cfg07_s cn30xx; | |
296 | struct cvmx_pci_cfg07_s cn31xx; | |
297 | struct cvmx_pci_cfg07_s cn38xx; | |
298 | struct cvmx_pci_cfg07_s cn38xxp2; | |
299 | struct cvmx_pci_cfg07_s cn50xx; | |
300 | struct cvmx_pci_cfg07_s cn58xx; | |
301 | struct cvmx_pci_cfg07_s cn58xxp1; | |
302 | }; | |
303 | ||
304 | union cvmx_pci_cfg08 { | |
305 | uint32_t u32; | |
306 | struct cvmx_pci_cfg08_s { | |
307 | uint32_t lbasez:28; | |
308 | uint32_t pf:1; | |
309 | uint32_t typ:2; | |
310 | uint32_t mspc:1; | |
311 | } s; | |
312 | struct cvmx_pci_cfg08_s cn30xx; | |
313 | struct cvmx_pci_cfg08_s cn31xx; | |
314 | struct cvmx_pci_cfg08_s cn38xx; | |
315 | struct cvmx_pci_cfg08_s cn38xxp2; | |
316 | struct cvmx_pci_cfg08_s cn50xx; | |
317 | struct cvmx_pci_cfg08_s cn58xx; | |
318 | struct cvmx_pci_cfg08_s cn58xxp1; | |
319 | }; | |
320 | ||
321 | union cvmx_pci_cfg09 { | |
322 | uint32_t u32; | |
323 | struct cvmx_pci_cfg09_s { | |
324 | uint32_t hbase:25; | |
325 | uint32_t hbasez:7; | |
326 | } s; | |
327 | struct cvmx_pci_cfg09_s cn30xx; | |
328 | struct cvmx_pci_cfg09_s cn31xx; | |
329 | struct cvmx_pci_cfg09_s cn38xx; | |
330 | struct cvmx_pci_cfg09_s cn38xxp2; | |
331 | struct cvmx_pci_cfg09_s cn50xx; | |
332 | struct cvmx_pci_cfg09_s cn58xx; | |
333 | struct cvmx_pci_cfg09_s cn58xxp1; | |
334 | }; | |
335 | ||
336 | union cvmx_pci_cfg10 { | |
337 | uint32_t u32; | |
338 | struct cvmx_pci_cfg10_s { | |
339 | uint32_t cisp:32; | |
340 | } s; | |
341 | struct cvmx_pci_cfg10_s cn30xx; | |
342 | struct cvmx_pci_cfg10_s cn31xx; | |
343 | struct cvmx_pci_cfg10_s cn38xx; | |
344 | struct cvmx_pci_cfg10_s cn38xxp2; | |
345 | struct cvmx_pci_cfg10_s cn50xx; | |
346 | struct cvmx_pci_cfg10_s cn58xx; | |
347 | struct cvmx_pci_cfg10_s cn58xxp1; | |
348 | }; | |
349 | ||
350 | union cvmx_pci_cfg11 { | |
351 | uint32_t u32; | |
352 | struct cvmx_pci_cfg11_s { | |
353 | uint32_t ssid:16; | |
354 | uint32_t ssvid:16; | |
355 | } s; | |
356 | struct cvmx_pci_cfg11_s cn30xx; | |
357 | struct cvmx_pci_cfg11_s cn31xx; | |
358 | struct cvmx_pci_cfg11_s cn38xx; | |
359 | struct cvmx_pci_cfg11_s cn38xxp2; | |
360 | struct cvmx_pci_cfg11_s cn50xx; | |
361 | struct cvmx_pci_cfg11_s cn58xx; | |
362 | struct cvmx_pci_cfg11_s cn58xxp1; | |
363 | }; | |
364 | ||
365 | union cvmx_pci_cfg12 { | |
366 | uint32_t u32; | |
367 | struct cvmx_pci_cfg12_s { | |
368 | uint32_t erbar:16; | |
369 | uint32_t erbarz:5; | |
370 | uint32_t reserved_1_10:10; | |
371 | uint32_t erbar_en:1; | |
372 | } s; | |
373 | struct cvmx_pci_cfg12_s cn30xx; | |
374 | struct cvmx_pci_cfg12_s cn31xx; | |
375 | struct cvmx_pci_cfg12_s cn38xx; | |
376 | struct cvmx_pci_cfg12_s cn38xxp2; | |
377 | struct cvmx_pci_cfg12_s cn50xx; | |
378 | struct cvmx_pci_cfg12_s cn58xx; | |
379 | struct cvmx_pci_cfg12_s cn58xxp1; | |
380 | }; | |
381 | ||
382 | union cvmx_pci_cfg13 { | |
383 | uint32_t u32; | |
384 | struct cvmx_pci_cfg13_s { | |
385 | uint32_t reserved_8_31:24; | |
386 | uint32_t cp:8; | |
387 | } s; | |
388 | struct cvmx_pci_cfg13_s cn30xx; | |
389 | struct cvmx_pci_cfg13_s cn31xx; | |
390 | struct cvmx_pci_cfg13_s cn38xx; | |
391 | struct cvmx_pci_cfg13_s cn38xxp2; | |
392 | struct cvmx_pci_cfg13_s cn50xx; | |
393 | struct cvmx_pci_cfg13_s cn58xx; | |
394 | struct cvmx_pci_cfg13_s cn58xxp1; | |
395 | }; | |
396 | ||
397 | union cvmx_pci_cfg15 { | |
398 | uint32_t u32; | |
399 | struct cvmx_pci_cfg15_s { | |
400 | uint32_t ml:8; | |
401 | uint32_t mg:8; | |
402 | uint32_t inta:8; | |
403 | uint32_t il:8; | |
404 | } s; | |
405 | struct cvmx_pci_cfg15_s cn30xx; | |
406 | struct cvmx_pci_cfg15_s cn31xx; | |
407 | struct cvmx_pci_cfg15_s cn38xx; | |
408 | struct cvmx_pci_cfg15_s cn38xxp2; | |
409 | struct cvmx_pci_cfg15_s cn50xx; | |
410 | struct cvmx_pci_cfg15_s cn58xx; | |
411 | struct cvmx_pci_cfg15_s cn58xxp1; | |
412 | }; | |
413 | ||
414 | union cvmx_pci_cfg16 { | |
415 | uint32_t u32; | |
416 | struct cvmx_pci_cfg16_s { | |
417 | uint32_t trdnpr:1; | |
418 | uint32_t trdard:1; | |
419 | uint32_t rdsati:1; | |
420 | uint32_t trdrs:1; | |
421 | uint32_t trtae:1; | |
422 | uint32_t twsei:1; | |
423 | uint32_t twsen:1; | |
424 | uint32_t twtae:1; | |
425 | uint32_t tmae:1; | |
426 | uint32_t tslte:3; | |
427 | uint32_t tilt:4; | |
428 | uint32_t pbe:12; | |
429 | uint32_t dppmr:1; | |
430 | uint32_t reserved_2_2:1; | |
431 | uint32_t tswc:1; | |
432 | uint32_t mltd:1; | |
433 | } s; | |
434 | struct cvmx_pci_cfg16_s cn30xx; | |
435 | struct cvmx_pci_cfg16_s cn31xx; | |
436 | struct cvmx_pci_cfg16_s cn38xx; | |
437 | struct cvmx_pci_cfg16_s cn38xxp2; | |
438 | struct cvmx_pci_cfg16_s cn50xx; | |
439 | struct cvmx_pci_cfg16_s cn58xx; | |
440 | struct cvmx_pci_cfg16_s cn58xxp1; | |
441 | }; | |
442 | ||
443 | union cvmx_pci_cfg17 { | |
444 | uint32_t u32; | |
445 | struct cvmx_pci_cfg17_s { | |
446 | uint32_t tscme:32; | |
447 | } s; | |
448 | struct cvmx_pci_cfg17_s cn30xx; | |
449 | struct cvmx_pci_cfg17_s cn31xx; | |
450 | struct cvmx_pci_cfg17_s cn38xx; | |
451 | struct cvmx_pci_cfg17_s cn38xxp2; | |
452 | struct cvmx_pci_cfg17_s cn50xx; | |
453 | struct cvmx_pci_cfg17_s cn58xx; | |
454 | struct cvmx_pci_cfg17_s cn58xxp1; | |
455 | }; | |
456 | ||
457 | union cvmx_pci_cfg18 { | |
458 | uint32_t u32; | |
459 | struct cvmx_pci_cfg18_s { | |
460 | uint32_t tdsrps:32; | |
461 | } s; | |
462 | struct cvmx_pci_cfg18_s cn30xx; | |
463 | struct cvmx_pci_cfg18_s cn31xx; | |
464 | struct cvmx_pci_cfg18_s cn38xx; | |
465 | struct cvmx_pci_cfg18_s cn38xxp2; | |
466 | struct cvmx_pci_cfg18_s cn50xx; | |
467 | struct cvmx_pci_cfg18_s cn58xx; | |
468 | struct cvmx_pci_cfg18_s cn58xxp1; | |
469 | }; | |
470 | ||
471 | union cvmx_pci_cfg19 { | |
472 | uint32_t u32; | |
473 | struct cvmx_pci_cfg19_s { | |
474 | uint32_t mrbcm:1; | |
475 | uint32_t mrbci:1; | |
476 | uint32_t mdwe:1; | |
477 | uint32_t mdre:1; | |
478 | uint32_t mdrimc:1; | |
479 | uint32_t mdrrmc:3; | |
480 | uint32_t tmes:8; | |
481 | uint32_t teci:1; | |
482 | uint32_t tmei:1; | |
483 | uint32_t tmse:1; | |
484 | uint32_t tmdpes:1; | |
485 | uint32_t tmapes:1; | |
486 | uint32_t reserved_9_10:2; | |
487 | uint32_t tibcd:1; | |
488 | uint32_t tibde:1; | |
489 | uint32_t reserved_6_6:1; | |
490 | uint32_t tidomc:1; | |
491 | uint32_t tdomc:5; | |
492 | } s; | |
493 | struct cvmx_pci_cfg19_s cn30xx; | |
494 | struct cvmx_pci_cfg19_s cn31xx; | |
495 | struct cvmx_pci_cfg19_s cn38xx; | |
496 | struct cvmx_pci_cfg19_s cn38xxp2; | |
497 | struct cvmx_pci_cfg19_s cn50xx; | |
498 | struct cvmx_pci_cfg19_s cn58xx; | |
499 | struct cvmx_pci_cfg19_s cn58xxp1; | |
500 | }; | |
501 | ||
502 | union cvmx_pci_cfg20 { | |
503 | uint32_t u32; | |
504 | struct cvmx_pci_cfg20_s { | |
505 | uint32_t mdsp:32; | |
506 | } s; | |
507 | struct cvmx_pci_cfg20_s cn30xx; | |
508 | struct cvmx_pci_cfg20_s cn31xx; | |
509 | struct cvmx_pci_cfg20_s cn38xx; | |
510 | struct cvmx_pci_cfg20_s cn38xxp2; | |
511 | struct cvmx_pci_cfg20_s cn50xx; | |
512 | struct cvmx_pci_cfg20_s cn58xx; | |
513 | struct cvmx_pci_cfg20_s cn58xxp1; | |
514 | }; | |
515 | ||
516 | union cvmx_pci_cfg21 { | |
517 | uint32_t u32; | |
518 | struct cvmx_pci_cfg21_s { | |
519 | uint32_t scmre:32; | |
520 | } s; | |
521 | struct cvmx_pci_cfg21_s cn30xx; | |
522 | struct cvmx_pci_cfg21_s cn31xx; | |
523 | struct cvmx_pci_cfg21_s cn38xx; | |
524 | struct cvmx_pci_cfg21_s cn38xxp2; | |
525 | struct cvmx_pci_cfg21_s cn50xx; | |
526 | struct cvmx_pci_cfg21_s cn58xx; | |
527 | struct cvmx_pci_cfg21_s cn58xxp1; | |
528 | }; | |
529 | ||
530 | union cvmx_pci_cfg22 { | |
531 | uint32_t u32; | |
532 | struct cvmx_pci_cfg22_s { | |
533 | uint32_t mac:7; | |
534 | uint32_t reserved_19_24:6; | |
535 | uint32_t flush:1; | |
536 | uint32_t mra:1; | |
537 | uint32_t mtta:1; | |
538 | uint32_t mrv:8; | |
539 | uint32_t mttv:8; | |
540 | } s; | |
541 | struct cvmx_pci_cfg22_s cn30xx; | |
542 | struct cvmx_pci_cfg22_s cn31xx; | |
543 | struct cvmx_pci_cfg22_s cn38xx; | |
544 | struct cvmx_pci_cfg22_s cn38xxp2; | |
545 | struct cvmx_pci_cfg22_s cn50xx; | |
546 | struct cvmx_pci_cfg22_s cn58xx; | |
547 | struct cvmx_pci_cfg22_s cn58xxp1; | |
548 | }; | |
549 | ||
550 | union cvmx_pci_cfg56 { | |
551 | uint32_t u32; | |
552 | struct cvmx_pci_cfg56_s { | |
553 | uint32_t reserved_23_31:9; | |
554 | uint32_t most:3; | |
555 | uint32_t mmbc:2; | |
556 | uint32_t roe:1; | |
557 | uint32_t dpere:1; | |
558 | uint32_t ncp:8; | |
559 | uint32_t pxcid:8; | |
560 | } s; | |
561 | struct cvmx_pci_cfg56_s cn30xx; | |
562 | struct cvmx_pci_cfg56_s cn31xx; | |
563 | struct cvmx_pci_cfg56_s cn38xx; | |
564 | struct cvmx_pci_cfg56_s cn38xxp2; | |
565 | struct cvmx_pci_cfg56_s cn50xx; | |
566 | struct cvmx_pci_cfg56_s cn58xx; | |
567 | struct cvmx_pci_cfg56_s cn58xxp1; | |
568 | }; | |
569 | ||
570 | union cvmx_pci_cfg57 { | |
571 | uint32_t u32; | |
572 | struct cvmx_pci_cfg57_s { | |
573 | uint32_t reserved_30_31:2; | |
574 | uint32_t scemr:1; | |
575 | uint32_t mcrsd:3; | |
576 | uint32_t mostd:3; | |
577 | uint32_t mmrbcd:2; | |
578 | uint32_t dc:1; | |
579 | uint32_t usc:1; | |
580 | uint32_t scd:1; | |
581 | uint32_t m133:1; | |
582 | uint32_t w64:1; | |
583 | uint32_t bn:8; | |
584 | uint32_t dn:5; | |
585 | uint32_t fn:3; | |
586 | } s; | |
587 | struct cvmx_pci_cfg57_s cn30xx; | |
588 | struct cvmx_pci_cfg57_s cn31xx; | |
589 | struct cvmx_pci_cfg57_s cn38xx; | |
590 | struct cvmx_pci_cfg57_s cn38xxp2; | |
591 | struct cvmx_pci_cfg57_s cn50xx; | |
592 | struct cvmx_pci_cfg57_s cn58xx; | |
593 | struct cvmx_pci_cfg57_s cn58xxp1; | |
594 | }; | |
595 | ||
596 | union cvmx_pci_cfg58 { | |
597 | uint32_t u32; | |
598 | struct cvmx_pci_cfg58_s { | |
599 | uint32_t pmes:5; | |
600 | uint32_t d2s:1; | |
601 | uint32_t d1s:1; | |
602 | uint32_t auxc:3; | |
603 | uint32_t dsi:1; | |
604 | uint32_t reserved_20_20:1; | |
605 | uint32_t pmec:1; | |
606 | uint32_t pcimiv:3; | |
607 | uint32_t ncp:8; | |
608 | uint32_t pmcid:8; | |
609 | } s; | |
610 | struct cvmx_pci_cfg58_s cn30xx; | |
611 | struct cvmx_pci_cfg58_s cn31xx; | |
612 | struct cvmx_pci_cfg58_s cn38xx; | |
613 | struct cvmx_pci_cfg58_s cn38xxp2; | |
614 | struct cvmx_pci_cfg58_s cn50xx; | |
615 | struct cvmx_pci_cfg58_s cn58xx; | |
616 | struct cvmx_pci_cfg58_s cn58xxp1; | |
617 | }; | |
618 | ||
619 | union cvmx_pci_cfg59 { | |
620 | uint32_t u32; | |
621 | struct cvmx_pci_cfg59_s { | |
622 | uint32_t pmdia:8; | |
623 | uint32_t bpccen:1; | |
624 | uint32_t bd3h:1; | |
625 | uint32_t reserved_16_21:6; | |
626 | uint32_t pmess:1; | |
627 | uint32_t pmedsia:2; | |
628 | uint32_t pmds:4; | |
629 | uint32_t pmeens:1; | |
630 | uint32_t reserved_2_7:6; | |
631 | uint32_t ps:2; | |
632 | } s; | |
633 | struct cvmx_pci_cfg59_s cn30xx; | |
634 | struct cvmx_pci_cfg59_s cn31xx; | |
635 | struct cvmx_pci_cfg59_s cn38xx; | |
636 | struct cvmx_pci_cfg59_s cn38xxp2; | |
637 | struct cvmx_pci_cfg59_s cn50xx; | |
638 | struct cvmx_pci_cfg59_s cn58xx; | |
639 | struct cvmx_pci_cfg59_s cn58xxp1; | |
640 | }; | |
641 | ||
642 | union cvmx_pci_cfg60 { | |
643 | uint32_t u32; | |
644 | struct cvmx_pci_cfg60_s { | |
645 | uint32_t reserved_24_31:8; | |
646 | uint32_t m64:1; | |
647 | uint32_t mme:3; | |
648 | uint32_t mmc:3; | |
649 | uint32_t msien:1; | |
650 | uint32_t ncp:8; | |
651 | uint32_t msicid:8; | |
652 | } s; | |
653 | struct cvmx_pci_cfg60_s cn30xx; | |
654 | struct cvmx_pci_cfg60_s cn31xx; | |
655 | struct cvmx_pci_cfg60_s cn38xx; | |
656 | struct cvmx_pci_cfg60_s cn38xxp2; | |
657 | struct cvmx_pci_cfg60_s cn50xx; | |
658 | struct cvmx_pci_cfg60_s cn58xx; | |
659 | struct cvmx_pci_cfg60_s cn58xxp1; | |
660 | }; | |
661 | ||
662 | union cvmx_pci_cfg61 { | |
663 | uint32_t u32; | |
664 | struct cvmx_pci_cfg61_s { | |
665 | uint32_t msi31t2:30; | |
666 | uint32_t reserved_0_1:2; | |
667 | } s; | |
668 | struct cvmx_pci_cfg61_s cn30xx; | |
669 | struct cvmx_pci_cfg61_s cn31xx; | |
670 | struct cvmx_pci_cfg61_s cn38xx; | |
671 | struct cvmx_pci_cfg61_s cn38xxp2; | |
672 | struct cvmx_pci_cfg61_s cn50xx; | |
673 | struct cvmx_pci_cfg61_s cn58xx; | |
674 | struct cvmx_pci_cfg61_s cn58xxp1; | |
675 | }; | |
676 | ||
677 | union cvmx_pci_cfg62 { | |
678 | uint32_t u32; | |
679 | struct cvmx_pci_cfg62_s { | |
680 | uint32_t msi:32; | |
681 | } s; | |
682 | struct cvmx_pci_cfg62_s cn30xx; | |
683 | struct cvmx_pci_cfg62_s cn31xx; | |
684 | struct cvmx_pci_cfg62_s cn38xx; | |
685 | struct cvmx_pci_cfg62_s cn38xxp2; | |
686 | struct cvmx_pci_cfg62_s cn50xx; | |
687 | struct cvmx_pci_cfg62_s cn58xx; | |
688 | struct cvmx_pci_cfg62_s cn58xxp1; | |
689 | }; | |
690 | ||
691 | union cvmx_pci_cfg63 { | |
692 | uint32_t u32; | |
693 | struct cvmx_pci_cfg63_s { | |
694 | uint32_t reserved_16_31:16; | |
695 | uint32_t msimd:16; | |
696 | } s; | |
697 | struct cvmx_pci_cfg63_s cn30xx; | |
698 | struct cvmx_pci_cfg63_s cn31xx; | |
699 | struct cvmx_pci_cfg63_s cn38xx; | |
700 | struct cvmx_pci_cfg63_s cn38xxp2; | |
701 | struct cvmx_pci_cfg63_s cn50xx; | |
702 | struct cvmx_pci_cfg63_s cn58xx; | |
703 | struct cvmx_pci_cfg63_s cn58xxp1; | |
704 | }; | |
705 | ||
706 | union cvmx_pci_cnt_reg { | |
707 | uint64_t u64; | |
708 | struct cvmx_pci_cnt_reg_s { | |
709 | uint64_t reserved_38_63:26; | |
710 | uint64_t hm_pcix:1; | |
711 | uint64_t hm_speed:2; | |
712 | uint64_t ap_pcix:1; | |
713 | uint64_t ap_speed:2; | |
714 | uint64_t pcicnt:32; | |
715 | } s; | |
716 | struct cvmx_pci_cnt_reg_s cn50xx; | |
717 | struct cvmx_pci_cnt_reg_s cn58xx; | |
718 | struct cvmx_pci_cnt_reg_s cn58xxp1; | |
719 | }; | |
720 | ||
721 | union cvmx_pci_ctl_status_2 { | |
722 | uint32_t u32; | |
723 | struct cvmx_pci_ctl_status_2_s { | |
724 | uint32_t reserved_29_31:3; | |
725 | uint32_t bb1_hole:3; | |
726 | uint32_t bb1_siz:1; | |
727 | uint32_t bb_ca:1; | |
728 | uint32_t bb_es:2; | |
729 | uint32_t bb1:1; | |
730 | uint32_t bb0:1; | |
731 | uint32_t erst_n:1; | |
732 | uint32_t bar2pres:1; | |
733 | uint32_t scmtyp:1; | |
734 | uint32_t scm:1; | |
735 | uint32_t en_wfilt:1; | |
736 | uint32_t reserved_14_14:1; | |
737 | uint32_t ap_pcix:1; | |
738 | uint32_t ap_64ad:1; | |
739 | uint32_t b12_bist:1; | |
740 | uint32_t pmo_amod:1; | |
741 | uint32_t pmo_fpc:3; | |
742 | uint32_t tsr_hwm:3; | |
743 | uint32_t bar2_enb:1; | |
744 | uint32_t bar2_esx:2; | |
745 | uint32_t bar2_cax:1; | |
746 | } s; | |
747 | struct cvmx_pci_ctl_status_2_s cn30xx; | |
748 | struct cvmx_pci_ctl_status_2_cn31xx { | |
749 | uint32_t reserved_20_31:12; | |
750 | uint32_t erst_n:1; | |
751 | uint32_t bar2pres:1; | |
752 | uint32_t scmtyp:1; | |
753 | uint32_t scm:1; | |
754 | uint32_t en_wfilt:1; | |
755 | uint32_t reserved_14_14:1; | |
756 | uint32_t ap_pcix:1; | |
757 | uint32_t ap_64ad:1; | |
758 | uint32_t b12_bist:1; | |
759 | uint32_t pmo_amod:1; | |
760 | uint32_t pmo_fpc:3; | |
761 | uint32_t tsr_hwm:3; | |
762 | uint32_t bar2_enb:1; | |
763 | uint32_t bar2_esx:2; | |
764 | uint32_t bar2_cax:1; | |
765 | } cn31xx; | |
766 | struct cvmx_pci_ctl_status_2_s cn38xx; | |
767 | struct cvmx_pci_ctl_status_2_cn31xx cn38xxp2; | |
768 | struct cvmx_pci_ctl_status_2_s cn50xx; | |
769 | struct cvmx_pci_ctl_status_2_s cn58xx; | |
770 | struct cvmx_pci_ctl_status_2_s cn58xxp1; | |
771 | }; | |
772 | ||
773 | union cvmx_pci_dbellx { | |
774 | uint32_t u32; | |
775 | struct cvmx_pci_dbellx_s { | |
776 | uint32_t reserved_16_31:16; | |
777 | uint32_t inc_val:16; | |
778 | } s; | |
779 | struct cvmx_pci_dbellx_s cn30xx; | |
780 | struct cvmx_pci_dbellx_s cn31xx; | |
781 | struct cvmx_pci_dbellx_s cn38xx; | |
782 | struct cvmx_pci_dbellx_s cn38xxp2; | |
783 | struct cvmx_pci_dbellx_s cn50xx; | |
784 | struct cvmx_pci_dbellx_s cn58xx; | |
785 | struct cvmx_pci_dbellx_s cn58xxp1; | |
786 | }; | |
787 | ||
788 | union cvmx_pci_dma_cntx { | |
789 | uint32_t u32; | |
790 | struct cvmx_pci_dma_cntx_s { | |
791 | uint32_t dma_cnt:32; | |
792 | } s; | |
793 | struct cvmx_pci_dma_cntx_s cn30xx; | |
794 | struct cvmx_pci_dma_cntx_s cn31xx; | |
795 | struct cvmx_pci_dma_cntx_s cn38xx; | |
796 | struct cvmx_pci_dma_cntx_s cn38xxp2; | |
797 | struct cvmx_pci_dma_cntx_s cn50xx; | |
798 | struct cvmx_pci_dma_cntx_s cn58xx; | |
799 | struct cvmx_pci_dma_cntx_s cn58xxp1; | |
800 | }; | |
801 | ||
802 | union cvmx_pci_dma_int_levx { | |
803 | uint32_t u32; | |
804 | struct cvmx_pci_dma_int_levx_s { | |
805 | uint32_t pkt_cnt:32; | |
806 | } s; | |
807 | struct cvmx_pci_dma_int_levx_s cn30xx; | |
808 | struct cvmx_pci_dma_int_levx_s cn31xx; | |
809 | struct cvmx_pci_dma_int_levx_s cn38xx; | |
810 | struct cvmx_pci_dma_int_levx_s cn38xxp2; | |
811 | struct cvmx_pci_dma_int_levx_s cn50xx; | |
812 | struct cvmx_pci_dma_int_levx_s cn58xx; | |
813 | struct cvmx_pci_dma_int_levx_s cn58xxp1; | |
814 | }; | |
815 | ||
816 | union cvmx_pci_dma_timex { | |
817 | uint32_t u32; | |
818 | struct cvmx_pci_dma_timex_s { | |
819 | uint32_t dma_time:32; | |
820 | } s; | |
821 | struct cvmx_pci_dma_timex_s cn30xx; | |
822 | struct cvmx_pci_dma_timex_s cn31xx; | |
823 | struct cvmx_pci_dma_timex_s cn38xx; | |
824 | struct cvmx_pci_dma_timex_s cn38xxp2; | |
825 | struct cvmx_pci_dma_timex_s cn50xx; | |
826 | struct cvmx_pci_dma_timex_s cn58xx; | |
827 | struct cvmx_pci_dma_timex_s cn58xxp1; | |
828 | }; | |
829 | ||
830 | union cvmx_pci_instr_countx { | |
831 | uint32_t u32; | |
832 | struct cvmx_pci_instr_countx_s { | |
833 | uint32_t icnt:32; | |
834 | } s; | |
835 | struct cvmx_pci_instr_countx_s cn30xx; | |
836 | struct cvmx_pci_instr_countx_s cn31xx; | |
837 | struct cvmx_pci_instr_countx_s cn38xx; | |
838 | struct cvmx_pci_instr_countx_s cn38xxp2; | |
839 | struct cvmx_pci_instr_countx_s cn50xx; | |
840 | struct cvmx_pci_instr_countx_s cn58xx; | |
841 | struct cvmx_pci_instr_countx_s cn58xxp1; | |
842 | }; | |
843 | ||
844 | union cvmx_pci_int_enb { | |
845 | uint64_t u64; | |
846 | struct cvmx_pci_int_enb_s { | |
847 | uint64_t reserved_34_63:30; | |
848 | uint64_t ill_rd:1; | |
849 | uint64_t ill_wr:1; | |
850 | uint64_t win_wr:1; | |
851 | uint64_t dma1_fi:1; | |
852 | uint64_t dma0_fi:1; | |
853 | uint64_t idtime1:1; | |
854 | uint64_t idtime0:1; | |
855 | uint64_t idcnt1:1; | |
856 | uint64_t idcnt0:1; | |
857 | uint64_t iptime3:1; | |
858 | uint64_t iptime2:1; | |
859 | uint64_t iptime1:1; | |
860 | uint64_t iptime0:1; | |
861 | uint64_t ipcnt3:1; | |
862 | uint64_t ipcnt2:1; | |
863 | uint64_t ipcnt1:1; | |
864 | uint64_t ipcnt0:1; | |
865 | uint64_t irsl_int:1; | |
866 | uint64_t ill_rrd:1; | |
867 | uint64_t ill_rwr:1; | |
868 | uint64_t idperr:1; | |
869 | uint64_t iaperr:1; | |
870 | uint64_t iserr:1; | |
871 | uint64_t itsr_abt:1; | |
872 | uint64_t imsc_msg:1; | |
873 | uint64_t imsi_mabt:1; | |
874 | uint64_t imsi_tabt:1; | |
875 | uint64_t imsi_per:1; | |
876 | uint64_t imr_tto:1; | |
877 | uint64_t imr_abt:1; | |
878 | uint64_t itr_abt:1; | |
879 | uint64_t imr_wtto:1; | |
880 | uint64_t imr_wabt:1; | |
881 | uint64_t itr_wabt:1; | |
882 | } s; | |
883 | struct cvmx_pci_int_enb_cn30xx { | |
884 | uint64_t reserved_34_63:30; | |
885 | uint64_t ill_rd:1; | |
886 | uint64_t ill_wr:1; | |
887 | uint64_t win_wr:1; | |
888 | uint64_t dma1_fi:1; | |
889 | uint64_t dma0_fi:1; | |
890 | uint64_t idtime1:1; | |
891 | uint64_t idtime0:1; | |
892 | uint64_t idcnt1:1; | |
893 | uint64_t idcnt0:1; | |
894 | uint64_t reserved_22_24:3; | |
895 | uint64_t iptime0:1; | |
896 | uint64_t reserved_18_20:3; | |
897 | uint64_t ipcnt0:1; | |
898 | uint64_t irsl_int:1; | |
899 | uint64_t ill_rrd:1; | |
900 | uint64_t ill_rwr:1; | |
901 | uint64_t idperr:1; | |
902 | uint64_t iaperr:1; | |
903 | uint64_t iserr:1; | |
904 | uint64_t itsr_abt:1; | |
905 | uint64_t imsc_msg:1; | |
906 | uint64_t imsi_mabt:1; | |
907 | uint64_t imsi_tabt:1; | |
908 | uint64_t imsi_per:1; | |
909 | uint64_t imr_tto:1; | |
910 | uint64_t imr_abt:1; | |
911 | uint64_t itr_abt:1; | |
912 | uint64_t imr_wtto:1; | |
913 | uint64_t imr_wabt:1; | |
914 | uint64_t itr_wabt:1; | |
915 | } cn30xx; | |
916 | struct cvmx_pci_int_enb_cn31xx { | |
917 | uint64_t reserved_34_63:30; | |
918 | uint64_t ill_rd:1; | |
919 | uint64_t ill_wr:1; | |
920 | uint64_t win_wr:1; | |
921 | uint64_t dma1_fi:1; | |
922 | uint64_t dma0_fi:1; | |
923 | uint64_t idtime1:1; | |
924 | uint64_t idtime0:1; | |
925 | uint64_t idcnt1:1; | |
926 | uint64_t idcnt0:1; | |
927 | uint64_t reserved_23_24:2; | |
928 | uint64_t iptime1:1; | |
929 | uint64_t iptime0:1; | |
930 | uint64_t reserved_19_20:2; | |
931 | uint64_t ipcnt1:1; | |
932 | uint64_t ipcnt0:1; | |
933 | uint64_t irsl_int:1; | |
934 | uint64_t ill_rrd:1; | |
935 | uint64_t ill_rwr:1; | |
936 | uint64_t idperr:1; | |
937 | uint64_t iaperr:1; | |
938 | uint64_t iserr:1; | |
939 | uint64_t itsr_abt:1; | |
940 | uint64_t imsc_msg:1; | |
941 | uint64_t imsi_mabt:1; | |
942 | uint64_t imsi_tabt:1; | |
943 | uint64_t imsi_per:1; | |
944 | uint64_t imr_tto:1; | |
945 | uint64_t imr_abt:1; | |
946 | uint64_t itr_abt:1; | |
947 | uint64_t imr_wtto:1; | |
948 | uint64_t imr_wabt:1; | |
949 | uint64_t itr_wabt:1; | |
950 | } cn31xx; | |
951 | struct cvmx_pci_int_enb_s cn38xx; | |
952 | struct cvmx_pci_int_enb_s cn38xxp2; | |
953 | struct cvmx_pci_int_enb_cn31xx cn50xx; | |
954 | struct cvmx_pci_int_enb_s cn58xx; | |
955 | struct cvmx_pci_int_enb_s cn58xxp1; | |
956 | }; | |
957 | ||
958 | union cvmx_pci_int_enb2 { | |
959 | uint64_t u64; | |
960 | struct cvmx_pci_int_enb2_s { | |
961 | uint64_t reserved_34_63:30; | |
962 | uint64_t ill_rd:1; | |
963 | uint64_t ill_wr:1; | |
964 | uint64_t win_wr:1; | |
965 | uint64_t dma1_fi:1; | |
966 | uint64_t dma0_fi:1; | |
967 | uint64_t rdtime1:1; | |
968 | uint64_t rdtime0:1; | |
969 | uint64_t rdcnt1:1; | |
970 | uint64_t rdcnt0:1; | |
971 | uint64_t rptime3:1; | |
972 | uint64_t rptime2:1; | |
973 | uint64_t rptime1:1; | |
974 | uint64_t rptime0:1; | |
975 | uint64_t rpcnt3:1; | |
976 | uint64_t rpcnt2:1; | |
977 | uint64_t rpcnt1:1; | |
978 | uint64_t rpcnt0:1; | |
979 | uint64_t rrsl_int:1; | |
980 | uint64_t ill_rrd:1; | |
981 | uint64_t ill_rwr:1; | |
982 | uint64_t rdperr:1; | |
983 | uint64_t raperr:1; | |
984 | uint64_t rserr:1; | |
985 | uint64_t rtsr_abt:1; | |
986 | uint64_t rmsc_msg:1; | |
987 | uint64_t rmsi_mabt:1; | |
988 | uint64_t rmsi_tabt:1; | |
989 | uint64_t rmsi_per:1; | |
990 | uint64_t rmr_tto:1; | |
991 | uint64_t rmr_abt:1; | |
992 | uint64_t rtr_abt:1; | |
993 | uint64_t rmr_wtto:1; | |
994 | uint64_t rmr_wabt:1; | |
995 | uint64_t rtr_wabt:1; | |
996 | } s; | |
997 | struct cvmx_pci_int_enb2_cn30xx { | |
998 | uint64_t reserved_34_63:30; | |
999 | uint64_t ill_rd:1; | |
1000 | uint64_t ill_wr:1; | |
1001 | uint64_t win_wr:1; | |
1002 | uint64_t dma1_fi:1; | |
1003 | uint64_t dma0_fi:1; | |
1004 | uint64_t rdtime1:1; | |
1005 | uint64_t rdtime0:1; | |
1006 | uint64_t rdcnt1:1; | |
1007 | uint64_t rdcnt0:1; | |
1008 | uint64_t reserved_22_24:3; | |
1009 | uint64_t rptime0:1; | |
1010 | uint64_t reserved_18_20:3; | |
1011 | uint64_t rpcnt0:1; | |
1012 | uint64_t rrsl_int:1; | |
1013 | uint64_t ill_rrd:1; | |
1014 | uint64_t ill_rwr:1; | |
1015 | uint64_t rdperr:1; | |
1016 | uint64_t raperr:1; | |
1017 | uint64_t rserr:1; | |
1018 | uint64_t rtsr_abt:1; | |
1019 | uint64_t rmsc_msg:1; | |
1020 | uint64_t rmsi_mabt:1; | |
1021 | uint64_t rmsi_tabt:1; | |
1022 | uint64_t rmsi_per:1; | |
1023 | uint64_t rmr_tto:1; | |
1024 | uint64_t rmr_abt:1; | |
1025 | uint64_t rtr_abt:1; | |
1026 | uint64_t rmr_wtto:1; | |
1027 | uint64_t rmr_wabt:1; | |
1028 | uint64_t rtr_wabt:1; | |
1029 | } cn30xx; | |
1030 | struct cvmx_pci_int_enb2_cn31xx { | |
1031 | uint64_t reserved_34_63:30; | |
1032 | uint64_t ill_rd:1; | |
1033 | uint64_t ill_wr:1; | |
1034 | uint64_t win_wr:1; | |
1035 | uint64_t dma1_fi:1; | |
1036 | uint64_t dma0_fi:1; | |
1037 | uint64_t rdtime1:1; | |
1038 | uint64_t rdtime0:1; | |
1039 | uint64_t rdcnt1:1; | |
1040 | uint64_t rdcnt0:1; | |
1041 | uint64_t reserved_23_24:2; | |
1042 | uint64_t rptime1:1; | |
1043 | uint64_t rptime0:1; | |
1044 | uint64_t reserved_19_20:2; | |
1045 | uint64_t rpcnt1:1; | |
1046 | uint64_t rpcnt0:1; | |
1047 | uint64_t rrsl_int:1; | |
1048 | uint64_t ill_rrd:1; | |
1049 | uint64_t ill_rwr:1; | |
1050 | uint64_t rdperr:1; | |
1051 | uint64_t raperr:1; | |
1052 | uint64_t rserr:1; | |
1053 | uint64_t rtsr_abt:1; | |
1054 | uint64_t rmsc_msg:1; | |
1055 | uint64_t rmsi_mabt:1; | |
1056 | uint64_t rmsi_tabt:1; | |
1057 | uint64_t rmsi_per:1; | |
1058 | uint64_t rmr_tto:1; | |
1059 | uint64_t rmr_abt:1; | |
1060 | uint64_t rtr_abt:1; | |
1061 | uint64_t rmr_wtto:1; | |
1062 | uint64_t rmr_wabt:1; | |
1063 | uint64_t rtr_wabt:1; | |
1064 | } cn31xx; | |
1065 | struct cvmx_pci_int_enb2_s cn38xx; | |
1066 | struct cvmx_pci_int_enb2_s cn38xxp2; | |
1067 | struct cvmx_pci_int_enb2_cn31xx cn50xx; | |
1068 | struct cvmx_pci_int_enb2_s cn58xx; | |
1069 | struct cvmx_pci_int_enb2_s cn58xxp1; | |
1070 | }; | |
1071 | ||
1072 | union cvmx_pci_int_sum { | |
1073 | uint64_t u64; | |
1074 | struct cvmx_pci_int_sum_s { | |
1075 | uint64_t reserved_34_63:30; | |
1076 | uint64_t ill_rd:1; | |
1077 | uint64_t ill_wr:1; | |
1078 | uint64_t win_wr:1; | |
1079 | uint64_t dma1_fi:1; | |
1080 | uint64_t dma0_fi:1; | |
1081 | uint64_t dtime1:1; | |
1082 | uint64_t dtime0:1; | |
1083 | uint64_t dcnt1:1; | |
1084 | uint64_t dcnt0:1; | |
1085 | uint64_t ptime3:1; | |
1086 | uint64_t ptime2:1; | |
1087 | uint64_t ptime1:1; | |
1088 | uint64_t ptime0:1; | |
1089 | uint64_t pcnt3:1; | |
1090 | uint64_t pcnt2:1; | |
1091 | uint64_t pcnt1:1; | |
1092 | uint64_t pcnt0:1; | |
1093 | uint64_t rsl_int:1; | |
1094 | uint64_t ill_rrd:1; | |
1095 | uint64_t ill_rwr:1; | |
1096 | uint64_t dperr:1; | |
1097 | uint64_t aperr:1; | |
1098 | uint64_t serr:1; | |
1099 | uint64_t tsr_abt:1; | |
1100 | uint64_t msc_msg:1; | |
1101 | uint64_t msi_mabt:1; | |
1102 | uint64_t msi_tabt:1; | |
1103 | uint64_t msi_per:1; | |
1104 | uint64_t mr_tto:1; | |
1105 | uint64_t mr_abt:1; | |
1106 | uint64_t tr_abt:1; | |
1107 | uint64_t mr_wtto:1; | |
1108 | uint64_t mr_wabt:1; | |
1109 | uint64_t tr_wabt:1; | |
1110 | } s; | |
1111 | struct cvmx_pci_int_sum_cn30xx { | |
1112 | uint64_t reserved_34_63:30; | |
1113 | uint64_t ill_rd:1; | |
1114 | uint64_t ill_wr:1; | |
1115 | uint64_t win_wr:1; | |
1116 | uint64_t dma1_fi:1; | |
1117 | uint64_t dma0_fi:1; | |
1118 | uint64_t dtime1:1; | |
1119 | uint64_t dtime0:1; | |
1120 | uint64_t dcnt1:1; | |
1121 | uint64_t dcnt0:1; | |
1122 | uint64_t reserved_22_24:3; | |
1123 | uint64_t ptime0:1; | |
1124 | uint64_t reserved_18_20:3; | |
1125 | uint64_t pcnt0:1; | |
1126 | uint64_t rsl_int:1; | |
1127 | uint64_t ill_rrd:1; | |
1128 | uint64_t ill_rwr:1; | |
1129 | uint64_t dperr:1; | |
1130 | uint64_t aperr:1; | |
1131 | uint64_t serr:1; | |
1132 | uint64_t tsr_abt:1; | |
1133 | uint64_t msc_msg:1; | |
1134 | uint64_t msi_mabt:1; | |
1135 | uint64_t msi_tabt:1; | |
1136 | uint64_t msi_per:1; | |
1137 | uint64_t mr_tto:1; | |
1138 | uint64_t mr_abt:1; | |
1139 | uint64_t tr_abt:1; | |
1140 | uint64_t mr_wtto:1; | |
1141 | uint64_t mr_wabt:1; | |
1142 | uint64_t tr_wabt:1; | |
1143 | } cn30xx; | |
1144 | struct cvmx_pci_int_sum_cn31xx { | |
1145 | uint64_t reserved_34_63:30; | |
1146 | uint64_t ill_rd:1; | |
1147 | uint64_t ill_wr:1; | |
1148 | uint64_t win_wr:1; | |
1149 | uint64_t dma1_fi:1; | |
1150 | uint64_t dma0_fi:1; | |
1151 | uint64_t dtime1:1; | |
1152 | uint64_t dtime0:1; | |
1153 | uint64_t dcnt1:1; | |
1154 | uint64_t dcnt0:1; | |
1155 | uint64_t reserved_23_24:2; | |
1156 | uint64_t ptime1:1; | |
1157 | uint64_t ptime0:1; | |
1158 | uint64_t reserved_19_20:2; | |
1159 | uint64_t pcnt1:1; | |
1160 | uint64_t pcnt0:1; | |
1161 | uint64_t rsl_int:1; | |
1162 | uint64_t ill_rrd:1; | |
1163 | uint64_t ill_rwr:1; | |
1164 | uint64_t dperr:1; | |
1165 | uint64_t aperr:1; | |
1166 | uint64_t serr:1; | |
1167 | uint64_t tsr_abt:1; | |
1168 | uint64_t msc_msg:1; | |
1169 | uint64_t msi_mabt:1; | |
1170 | uint64_t msi_tabt:1; | |
1171 | uint64_t msi_per:1; | |
1172 | uint64_t mr_tto:1; | |
1173 | uint64_t mr_abt:1; | |
1174 | uint64_t tr_abt:1; | |
1175 | uint64_t mr_wtto:1; | |
1176 | uint64_t mr_wabt:1; | |
1177 | uint64_t tr_wabt:1; | |
1178 | } cn31xx; | |
1179 | struct cvmx_pci_int_sum_s cn38xx; | |
1180 | struct cvmx_pci_int_sum_s cn38xxp2; | |
1181 | struct cvmx_pci_int_sum_cn31xx cn50xx; | |
1182 | struct cvmx_pci_int_sum_s cn58xx; | |
1183 | struct cvmx_pci_int_sum_s cn58xxp1; | |
1184 | }; | |
1185 | ||
1186 | union cvmx_pci_int_sum2 { | |
1187 | uint64_t u64; | |
1188 | struct cvmx_pci_int_sum2_s { | |
1189 | uint64_t reserved_34_63:30; | |
1190 | uint64_t ill_rd:1; | |
1191 | uint64_t ill_wr:1; | |
1192 | uint64_t win_wr:1; | |
1193 | uint64_t dma1_fi:1; | |
1194 | uint64_t dma0_fi:1; | |
1195 | uint64_t dtime1:1; | |
1196 | uint64_t dtime0:1; | |
1197 | uint64_t dcnt1:1; | |
1198 | uint64_t dcnt0:1; | |
1199 | uint64_t ptime3:1; | |
1200 | uint64_t ptime2:1; | |
1201 | uint64_t ptime1:1; | |
1202 | uint64_t ptime0:1; | |
1203 | uint64_t pcnt3:1; | |
1204 | uint64_t pcnt2:1; | |
1205 | uint64_t pcnt1:1; | |
1206 | uint64_t pcnt0:1; | |
1207 | uint64_t rsl_int:1; | |
1208 | uint64_t ill_rrd:1; | |
1209 | uint64_t ill_rwr:1; | |
1210 | uint64_t dperr:1; | |
1211 | uint64_t aperr:1; | |
1212 | uint64_t serr:1; | |
1213 | uint64_t tsr_abt:1; | |
1214 | uint64_t msc_msg:1; | |
1215 | uint64_t msi_mabt:1; | |
1216 | uint64_t msi_tabt:1; | |
1217 | uint64_t msi_per:1; | |
1218 | uint64_t mr_tto:1; | |
1219 | uint64_t mr_abt:1; | |
1220 | uint64_t tr_abt:1; | |
1221 | uint64_t mr_wtto:1; | |
1222 | uint64_t mr_wabt:1; | |
1223 | uint64_t tr_wabt:1; | |
1224 | } s; | |
1225 | struct cvmx_pci_int_sum2_cn30xx { | |
1226 | uint64_t reserved_34_63:30; | |
1227 | uint64_t ill_rd:1; | |
1228 | uint64_t ill_wr:1; | |
1229 | uint64_t win_wr:1; | |
1230 | uint64_t dma1_fi:1; | |
1231 | uint64_t dma0_fi:1; | |
1232 | uint64_t dtime1:1; | |
1233 | uint64_t dtime0:1; | |
1234 | uint64_t dcnt1:1; | |
1235 | uint64_t dcnt0:1; | |
1236 | uint64_t reserved_22_24:3; | |
1237 | uint64_t ptime0:1; | |
1238 | uint64_t reserved_18_20:3; | |
1239 | uint64_t pcnt0:1; | |
1240 | uint64_t rsl_int:1; | |
1241 | uint64_t ill_rrd:1; | |
1242 | uint64_t ill_rwr:1; | |
1243 | uint64_t dperr:1; | |
1244 | uint64_t aperr:1; | |
1245 | uint64_t serr:1; | |
1246 | uint64_t tsr_abt:1; | |
1247 | uint64_t msc_msg:1; | |
1248 | uint64_t msi_mabt:1; | |
1249 | uint64_t msi_tabt:1; | |
1250 | uint64_t msi_per:1; | |
1251 | uint64_t mr_tto:1; | |
1252 | uint64_t mr_abt:1; | |
1253 | uint64_t tr_abt:1; | |
1254 | uint64_t mr_wtto:1; | |
1255 | uint64_t mr_wabt:1; | |
1256 | uint64_t tr_wabt:1; | |
1257 | } cn30xx; | |
1258 | struct cvmx_pci_int_sum2_cn31xx { | |
1259 | uint64_t reserved_34_63:30; | |
1260 | uint64_t ill_rd:1; | |
1261 | uint64_t ill_wr:1; | |
1262 | uint64_t win_wr:1; | |
1263 | uint64_t dma1_fi:1; | |
1264 | uint64_t dma0_fi:1; | |
1265 | uint64_t dtime1:1; | |
1266 | uint64_t dtime0:1; | |
1267 | uint64_t dcnt1:1; | |
1268 | uint64_t dcnt0:1; | |
1269 | uint64_t reserved_23_24:2; | |
1270 | uint64_t ptime1:1; | |
1271 | uint64_t ptime0:1; | |
1272 | uint64_t reserved_19_20:2; | |
1273 | uint64_t pcnt1:1; | |
1274 | uint64_t pcnt0:1; | |
1275 | uint64_t rsl_int:1; | |
1276 | uint64_t ill_rrd:1; | |
1277 | uint64_t ill_rwr:1; | |
1278 | uint64_t dperr:1; | |
1279 | uint64_t aperr:1; | |
1280 | uint64_t serr:1; | |
1281 | uint64_t tsr_abt:1; | |
1282 | uint64_t msc_msg:1; | |
1283 | uint64_t msi_mabt:1; | |
1284 | uint64_t msi_tabt:1; | |
1285 | uint64_t msi_per:1; | |
1286 | uint64_t mr_tto:1; | |
1287 | uint64_t mr_abt:1; | |
1288 | uint64_t tr_abt:1; | |
1289 | uint64_t mr_wtto:1; | |
1290 | uint64_t mr_wabt:1; | |
1291 | uint64_t tr_wabt:1; | |
1292 | } cn31xx; | |
1293 | struct cvmx_pci_int_sum2_s cn38xx; | |
1294 | struct cvmx_pci_int_sum2_s cn38xxp2; | |
1295 | struct cvmx_pci_int_sum2_cn31xx cn50xx; | |
1296 | struct cvmx_pci_int_sum2_s cn58xx; | |
1297 | struct cvmx_pci_int_sum2_s cn58xxp1; | |
1298 | }; | |
1299 | ||
1300 | union cvmx_pci_msi_rcv { | |
1301 | uint32_t u32; | |
1302 | struct cvmx_pci_msi_rcv_s { | |
1303 | uint32_t reserved_6_31:26; | |
1304 | uint32_t intr:6; | |
1305 | } s; | |
1306 | struct cvmx_pci_msi_rcv_s cn30xx; | |
1307 | struct cvmx_pci_msi_rcv_s cn31xx; | |
1308 | struct cvmx_pci_msi_rcv_s cn38xx; | |
1309 | struct cvmx_pci_msi_rcv_s cn38xxp2; | |
1310 | struct cvmx_pci_msi_rcv_s cn50xx; | |
1311 | struct cvmx_pci_msi_rcv_s cn58xx; | |
1312 | struct cvmx_pci_msi_rcv_s cn58xxp1; | |
1313 | }; | |
1314 | ||
1315 | union cvmx_pci_pkt_creditsx { | |
1316 | uint32_t u32; | |
1317 | struct cvmx_pci_pkt_creditsx_s { | |
1318 | uint32_t pkt_cnt:16; | |
1319 | uint32_t ptr_cnt:16; | |
1320 | } s; | |
1321 | struct cvmx_pci_pkt_creditsx_s cn30xx; | |
1322 | struct cvmx_pci_pkt_creditsx_s cn31xx; | |
1323 | struct cvmx_pci_pkt_creditsx_s cn38xx; | |
1324 | struct cvmx_pci_pkt_creditsx_s cn38xxp2; | |
1325 | struct cvmx_pci_pkt_creditsx_s cn50xx; | |
1326 | struct cvmx_pci_pkt_creditsx_s cn58xx; | |
1327 | struct cvmx_pci_pkt_creditsx_s cn58xxp1; | |
1328 | }; | |
1329 | ||
1330 | union cvmx_pci_pkts_sentx { | |
1331 | uint32_t u32; | |
1332 | struct cvmx_pci_pkts_sentx_s { | |
1333 | uint32_t pkt_cnt:32; | |
1334 | } s; | |
1335 | struct cvmx_pci_pkts_sentx_s cn30xx; | |
1336 | struct cvmx_pci_pkts_sentx_s cn31xx; | |
1337 | struct cvmx_pci_pkts_sentx_s cn38xx; | |
1338 | struct cvmx_pci_pkts_sentx_s cn38xxp2; | |
1339 | struct cvmx_pci_pkts_sentx_s cn50xx; | |
1340 | struct cvmx_pci_pkts_sentx_s cn58xx; | |
1341 | struct cvmx_pci_pkts_sentx_s cn58xxp1; | |
1342 | }; | |
1343 | ||
1344 | union cvmx_pci_pkts_sent_int_levx { | |
1345 | uint32_t u32; | |
1346 | struct cvmx_pci_pkts_sent_int_levx_s { | |
1347 | uint32_t pkt_cnt:32; | |
1348 | } s; | |
1349 | struct cvmx_pci_pkts_sent_int_levx_s cn30xx; | |
1350 | struct cvmx_pci_pkts_sent_int_levx_s cn31xx; | |
1351 | struct cvmx_pci_pkts_sent_int_levx_s cn38xx; | |
1352 | struct cvmx_pci_pkts_sent_int_levx_s cn38xxp2; | |
1353 | struct cvmx_pci_pkts_sent_int_levx_s cn50xx; | |
1354 | struct cvmx_pci_pkts_sent_int_levx_s cn58xx; | |
1355 | struct cvmx_pci_pkts_sent_int_levx_s cn58xxp1; | |
1356 | }; | |
1357 | ||
1358 | union cvmx_pci_pkts_sent_timex { | |
1359 | uint32_t u32; | |
1360 | struct cvmx_pci_pkts_sent_timex_s { | |
1361 | uint32_t pkt_time:32; | |
1362 | } s; | |
1363 | struct cvmx_pci_pkts_sent_timex_s cn30xx; | |
1364 | struct cvmx_pci_pkts_sent_timex_s cn31xx; | |
1365 | struct cvmx_pci_pkts_sent_timex_s cn38xx; | |
1366 | struct cvmx_pci_pkts_sent_timex_s cn38xxp2; | |
1367 | struct cvmx_pci_pkts_sent_timex_s cn50xx; | |
1368 | struct cvmx_pci_pkts_sent_timex_s cn58xx; | |
1369 | struct cvmx_pci_pkts_sent_timex_s cn58xxp1; | |
1370 | }; | |
1371 | ||
1372 | union cvmx_pci_read_cmd_6 { | |
1373 | uint32_t u32; | |
1374 | struct cvmx_pci_read_cmd_6_s { | |
1375 | uint32_t reserved_9_31:23; | |
1376 | uint32_t min_data:6; | |
1377 | uint32_t prefetch:3; | |
1378 | } s; | |
1379 | struct cvmx_pci_read_cmd_6_s cn30xx; | |
1380 | struct cvmx_pci_read_cmd_6_s cn31xx; | |
1381 | struct cvmx_pci_read_cmd_6_s cn38xx; | |
1382 | struct cvmx_pci_read_cmd_6_s cn38xxp2; | |
1383 | struct cvmx_pci_read_cmd_6_s cn50xx; | |
1384 | struct cvmx_pci_read_cmd_6_s cn58xx; | |
1385 | struct cvmx_pci_read_cmd_6_s cn58xxp1; | |
1386 | }; | |
1387 | ||
1388 | union cvmx_pci_read_cmd_c { | |
1389 | uint32_t u32; | |
1390 | struct cvmx_pci_read_cmd_c_s { | |
1391 | uint32_t reserved_9_31:23; | |
1392 | uint32_t min_data:6; | |
1393 | uint32_t prefetch:3; | |
1394 | } s; | |
1395 | struct cvmx_pci_read_cmd_c_s cn30xx; | |
1396 | struct cvmx_pci_read_cmd_c_s cn31xx; | |
1397 | struct cvmx_pci_read_cmd_c_s cn38xx; | |
1398 | struct cvmx_pci_read_cmd_c_s cn38xxp2; | |
1399 | struct cvmx_pci_read_cmd_c_s cn50xx; | |
1400 | struct cvmx_pci_read_cmd_c_s cn58xx; | |
1401 | struct cvmx_pci_read_cmd_c_s cn58xxp1; | |
1402 | }; | |
1403 | ||
1404 | union cvmx_pci_read_cmd_e { | |
1405 | uint32_t u32; | |
1406 | struct cvmx_pci_read_cmd_e_s { | |
1407 | uint32_t reserved_9_31:23; | |
1408 | uint32_t min_data:6; | |
1409 | uint32_t prefetch:3; | |
1410 | } s; | |
1411 | struct cvmx_pci_read_cmd_e_s cn30xx; | |
1412 | struct cvmx_pci_read_cmd_e_s cn31xx; | |
1413 | struct cvmx_pci_read_cmd_e_s cn38xx; | |
1414 | struct cvmx_pci_read_cmd_e_s cn38xxp2; | |
1415 | struct cvmx_pci_read_cmd_e_s cn50xx; | |
1416 | struct cvmx_pci_read_cmd_e_s cn58xx; | |
1417 | struct cvmx_pci_read_cmd_e_s cn58xxp1; | |
1418 | }; | |
1419 | ||
1420 | union cvmx_pci_read_timeout { | |
1421 | uint64_t u64; | |
1422 | struct cvmx_pci_read_timeout_s { | |
1423 | uint64_t reserved_32_63:32; | |
1424 | uint64_t enb:1; | |
1425 | uint64_t cnt:31; | |
1426 | } s; | |
1427 | struct cvmx_pci_read_timeout_s cn30xx; | |
1428 | struct cvmx_pci_read_timeout_s cn31xx; | |
1429 | struct cvmx_pci_read_timeout_s cn38xx; | |
1430 | struct cvmx_pci_read_timeout_s cn38xxp2; | |
1431 | struct cvmx_pci_read_timeout_s cn50xx; | |
1432 | struct cvmx_pci_read_timeout_s cn58xx; | |
1433 | struct cvmx_pci_read_timeout_s cn58xxp1; | |
1434 | }; | |
1435 | ||
1436 | union cvmx_pci_scm_reg { | |
1437 | uint64_t u64; | |
1438 | struct cvmx_pci_scm_reg_s { | |
1439 | uint64_t reserved_32_63:32; | |
1440 | uint64_t scm:32; | |
1441 | } s; | |
1442 | struct cvmx_pci_scm_reg_s cn30xx; | |
1443 | struct cvmx_pci_scm_reg_s cn31xx; | |
1444 | struct cvmx_pci_scm_reg_s cn38xx; | |
1445 | struct cvmx_pci_scm_reg_s cn38xxp2; | |
1446 | struct cvmx_pci_scm_reg_s cn50xx; | |
1447 | struct cvmx_pci_scm_reg_s cn58xx; | |
1448 | struct cvmx_pci_scm_reg_s cn58xxp1; | |
1449 | }; | |
1450 | ||
1451 | union cvmx_pci_tsr_reg { | |
1452 | uint64_t u64; | |
1453 | struct cvmx_pci_tsr_reg_s { | |
1454 | uint64_t reserved_36_63:28; | |
1455 | uint64_t tsr:36; | |
1456 | } s; | |
1457 | struct cvmx_pci_tsr_reg_s cn30xx; | |
1458 | struct cvmx_pci_tsr_reg_s cn31xx; | |
1459 | struct cvmx_pci_tsr_reg_s cn38xx; | |
1460 | struct cvmx_pci_tsr_reg_s cn38xxp2; | |
1461 | struct cvmx_pci_tsr_reg_s cn50xx; | |
1462 | struct cvmx_pci_tsr_reg_s cn58xx; | |
1463 | struct cvmx_pci_tsr_reg_s cn58xxp1; | |
1464 | }; | |
1465 | ||
1466 | union cvmx_pci_win_rd_addr { | |
1467 | uint64_t u64; | |
1468 | struct cvmx_pci_win_rd_addr_s { | |
1469 | uint64_t reserved_49_63:15; | |
1470 | uint64_t iobit:1; | |
1471 | uint64_t reserved_0_47:48; | |
1472 | } s; | |
1473 | struct cvmx_pci_win_rd_addr_cn30xx { | |
1474 | uint64_t reserved_49_63:15; | |
1475 | uint64_t iobit:1; | |
1476 | uint64_t rd_addr:46; | |
1477 | uint64_t reserved_0_1:2; | |
1478 | } cn30xx; | |
1479 | struct cvmx_pci_win_rd_addr_cn30xx cn31xx; | |
1480 | struct cvmx_pci_win_rd_addr_cn38xx { | |
1481 | uint64_t reserved_49_63:15; | |
1482 | uint64_t iobit:1; | |
1483 | uint64_t rd_addr:45; | |
1484 | uint64_t reserved_0_2:3; | |
1485 | } cn38xx; | |
1486 | struct cvmx_pci_win_rd_addr_cn38xx cn38xxp2; | |
1487 | struct cvmx_pci_win_rd_addr_cn30xx cn50xx; | |
1488 | struct cvmx_pci_win_rd_addr_cn38xx cn58xx; | |
1489 | struct cvmx_pci_win_rd_addr_cn38xx cn58xxp1; | |
1490 | }; | |
1491 | ||
1492 | union cvmx_pci_win_rd_data { | |
1493 | uint64_t u64; | |
1494 | struct cvmx_pci_win_rd_data_s { | |
1495 | uint64_t rd_data:64; | |
1496 | } s; | |
1497 | struct cvmx_pci_win_rd_data_s cn30xx; | |
1498 | struct cvmx_pci_win_rd_data_s cn31xx; | |
1499 | struct cvmx_pci_win_rd_data_s cn38xx; | |
1500 | struct cvmx_pci_win_rd_data_s cn38xxp2; | |
1501 | struct cvmx_pci_win_rd_data_s cn50xx; | |
1502 | struct cvmx_pci_win_rd_data_s cn58xx; | |
1503 | struct cvmx_pci_win_rd_data_s cn58xxp1; | |
1504 | }; | |
1505 | ||
1506 | union cvmx_pci_win_wr_addr { | |
1507 | uint64_t u64; | |
1508 | struct cvmx_pci_win_wr_addr_s { | |
1509 | uint64_t reserved_49_63:15; | |
1510 | uint64_t iobit:1; | |
1511 | uint64_t wr_addr:45; | |
1512 | uint64_t reserved_0_2:3; | |
1513 | } s; | |
1514 | struct cvmx_pci_win_wr_addr_s cn30xx; | |
1515 | struct cvmx_pci_win_wr_addr_s cn31xx; | |
1516 | struct cvmx_pci_win_wr_addr_s cn38xx; | |
1517 | struct cvmx_pci_win_wr_addr_s cn38xxp2; | |
1518 | struct cvmx_pci_win_wr_addr_s cn50xx; | |
1519 | struct cvmx_pci_win_wr_addr_s cn58xx; | |
1520 | struct cvmx_pci_win_wr_addr_s cn58xxp1; | |
1521 | }; | |
1522 | ||
1523 | union cvmx_pci_win_wr_data { | |
1524 | uint64_t u64; | |
1525 | struct cvmx_pci_win_wr_data_s { | |
1526 | uint64_t wr_data:64; | |
1527 | } s; | |
1528 | struct cvmx_pci_win_wr_data_s cn30xx; | |
1529 | struct cvmx_pci_win_wr_data_s cn31xx; | |
1530 | struct cvmx_pci_win_wr_data_s cn38xx; | |
1531 | struct cvmx_pci_win_wr_data_s cn38xxp2; | |
1532 | struct cvmx_pci_win_wr_data_s cn50xx; | |
1533 | struct cvmx_pci_win_wr_data_s cn58xx; | |
1534 | struct cvmx_pci_win_wr_data_s cn58xxp1; | |
1535 | }; | |
1536 | ||
1537 | union cvmx_pci_win_wr_mask { | |
1538 | uint64_t u64; | |
1539 | struct cvmx_pci_win_wr_mask_s { | |
1540 | uint64_t reserved_8_63:56; | |
1541 | uint64_t wr_mask:8; | |
1542 | } s; | |
1543 | struct cvmx_pci_win_wr_mask_s cn30xx; | |
1544 | struct cvmx_pci_win_wr_mask_s cn31xx; | |
1545 | struct cvmx_pci_win_wr_mask_s cn38xx; | |
1546 | struct cvmx_pci_win_wr_mask_s cn38xxp2; | |
1547 | struct cvmx_pci_win_wr_mask_s cn50xx; | |
1548 | struct cvmx_pci_win_wr_mask_s cn58xx; | |
1549 | struct cvmx_pci_win_wr_mask_s cn58xxp1; | |
1550 | }; | |
1551 | ||
1552 | #endif |