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1 | /***********************license start*************** |
2 | * Author: Cavium Networks | |
3 | * | |
4 | * Contact: support@caviumnetworks.com | |
5 | * This file is part of the OCTEON SDK | |
6 | * | |
7 | * Copyright (c) 2003-2008 Cavium Networks | |
8 | * | |
9 | * This file is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License, Version 2, as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This file is distributed in the hope that it will be useful, but | |
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | |
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | |
16 | * NONINFRINGEMENT. See the GNU General Public License for more | |
17 | * details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this file; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
22 | * or visit http://www.gnu.org/licenses/. | |
23 | * | |
24 | * This file may also be available under a different license from Cavium. | |
25 | * Contact Cavium Networks for more information | |
26 | ***********************license end**************************************/ | |
27 | ||
28 | #ifndef __CVMX_PCI_DEFS_H__ | |
29 | #define __CVMX_PCI_DEFS_H__ | |
30 | ||
31 | #define CVMX_PCI_BAR1_INDEXX(offset) \ | |
32 | (0x0000000000000100ull + (((offset) & 31) * 4)) | |
33 | #define CVMX_PCI_BIST_REG \ | |
34 | (0x00000000000001C0ull) | |
35 | #define CVMX_PCI_CFG00 \ | |
36 | (0x0000000000000000ull) | |
37 | #define CVMX_PCI_CFG01 \ | |
38 | (0x0000000000000004ull) | |
39 | #define CVMX_PCI_CFG02 \ | |
40 | (0x0000000000000008ull) | |
41 | #define CVMX_PCI_CFG03 \ | |
42 | (0x000000000000000Cull) | |
43 | #define CVMX_PCI_CFG04 \ | |
44 | (0x0000000000000010ull) | |
45 | #define CVMX_PCI_CFG05 \ | |
46 | (0x0000000000000014ull) | |
47 | #define CVMX_PCI_CFG06 \ | |
48 | (0x0000000000000018ull) | |
49 | #define CVMX_PCI_CFG07 \ | |
50 | (0x000000000000001Cull) | |
51 | #define CVMX_PCI_CFG08 \ | |
52 | (0x0000000000000020ull) | |
53 | #define CVMX_PCI_CFG09 \ | |
54 | (0x0000000000000024ull) | |
55 | #define CVMX_PCI_CFG10 \ | |
56 | (0x0000000000000028ull) | |
57 | #define CVMX_PCI_CFG11 \ | |
58 | (0x000000000000002Cull) | |
59 | #define CVMX_PCI_CFG12 \ | |
60 | (0x0000000000000030ull) | |
61 | #define CVMX_PCI_CFG13 \ | |
62 | (0x0000000000000034ull) | |
63 | #define CVMX_PCI_CFG15 \ | |
64 | (0x000000000000003Cull) | |
65 | #define CVMX_PCI_CFG16 \ | |
66 | (0x0000000000000040ull) | |
67 | #define CVMX_PCI_CFG17 \ | |
68 | (0x0000000000000044ull) | |
69 | #define CVMX_PCI_CFG18 \ | |
70 | (0x0000000000000048ull) | |
71 | #define CVMX_PCI_CFG19 \ | |
72 | (0x000000000000004Cull) | |
73 | #define CVMX_PCI_CFG20 \ | |
74 | (0x0000000000000050ull) | |
75 | #define CVMX_PCI_CFG21 \ | |
76 | (0x0000000000000054ull) | |
77 | #define CVMX_PCI_CFG22 \ | |
78 | (0x0000000000000058ull) | |
79 | #define CVMX_PCI_CFG56 \ | |
80 | (0x00000000000000E0ull) | |
81 | #define CVMX_PCI_CFG57 \ | |
82 | (0x00000000000000E4ull) | |
83 | #define CVMX_PCI_CFG58 \ | |
84 | (0x00000000000000E8ull) | |
85 | #define CVMX_PCI_CFG59 \ | |
86 | (0x00000000000000ECull) | |
87 | #define CVMX_PCI_CFG60 \ | |
88 | (0x00000000000000F0ull) | |
89 | #define CVMX_PCI_CFG61 \ | |
90 | (0x00000000000000F4ull) | |
91 | #define CVMX_PCI_CFG62 \ | |
92 | (0x00000000000000F8ull) | |
93 | #define CVMX_PCI_CFG63 \ | |
94 | (0x00000000000000FCull) | |
95 | #define CVMX_PCI_CNT_REG \ | |
96 | (0x00000000000001B8ull) | |
97 | #define CVMX_PCI_CTL_STATUS_2 \ | |
98 | (0x000000000000018Cull) | |
99 | #define CVMX_PCI_DBELL_0 \ | |
100 | (0x0000000000000080ull) | |
101 | #define CVMX_PCI_DBELL_1 \ | |
102 | (0x0000000000000088ull) | |
103 | #define CVMX_PCI_DBELL_2 \ | |
104 | (0x0000000000000090ull) | |
105 | #define CVMX_PCI_DBELL_3 \ | |
106 | (0x0000000000000098ull) | |
107 | #define CVMX_PCI_DBELL_X(offset) \ | |
108 | (0x0000000000000080ull + (((offset) & 3) * 8)) | |
109 | #define CVMX_PCI_DMA_CNT0 \ | |
110 | (0x00000000000000A0ull) | |
111 | #define CVMX_PCI_DMA_CNT1 \ | |
112 | (0x00000000000000A8ull) | |
113 | #define CVMX_PCI_DMA_CNTX(offset) \ | |
114 | (0x00000000000000A0ull + (((offset) & 1) * 8)) | |
115 | #define CVMX_PCI_DMA_INT_LEV0 \ | |
116 | (0x00000000000000A4ull) | |
117 | #define CVMX_PCI_DMA_INT_LEV1 \ | |
118 | (0x00000000000000ACull) | |
119 | #define CVMX_PCI_DMA_INT_LEVX(offset) \ | |
120 | (0x00000000000000A4ull + (((offset) & 1) * 8)) | |
121 | #define CVMX_PCI_DMA_TIME0 \ | |
122 | (0x00000000000000B0ull) | |
123 | #define CVMX_PCI_DMA_TIME1 \ | |
124 | (0x00000000000000B4ull) | |
125 | #define CVMX_PCI_DMA_TIMEX(offset) \ | |
126 | (0x00000000000000B0ull + (((offset) & 1) * 4)) | |
127 | #define CVMX_PCI_INSTR_COUNT0 \ | |
128 | (0x0000000000000084ull) | |
129 | #define CVMX_PCI_INSTR_COUNT1 \ | |
130 | (0x000000000000008Cull) | |
131 | #define CVMX_PCI_INSTR_COUNT2 \ | |
132 | (0x0000000000000094ull) | |
133 | #define CVMX_PCI_INSTR_COUNT3 \ | |
134 | (0x000000000000009Cull) | |
135 | #define CVMX_PCI_INSTR_COUNTX(offset) \ | |
136 | (0x0000000000000084ull + (((offset) & 3) * 8)) | |
137 | #define CVMX_PCI_INT_ENB \ | |
138 | (0x0000000000000038ull) | |
139 | #define CVMX_PCI_INT_ENB2 \ | |
140 | (0x00000000000001A0ull) | |
141 | #define CVMX_PCI_INT_SUM \ | |
142 | (0x0000000000000030ull) | |
143 | #define CVMX_PCI_INT_SUM2 \ | |
144 | (0x0000000000000198ull) | |
145 | #define CVMX_PCI_MSI_RCV \ | |
146 | (0x00000000000000F0ull) | |
147 | #define CVMX_PCI_PKTS_SENT0 \ | |
148 | (0x0000000000000040ull) | |
149 | #define CVMX_PCI_PKTS_SENT1 \ | |
150 | (0x0000000000000050ull) | |
151 | #define CVMX_PCI_PKTS_SENT2 \ | |
152 | (0x0000000000000060ull) | |
153 | #define CVMX_PCI_PKTS_SENT3 \ | |
154 | (0x0000000000000070ull) | |
155 | #define CVMX_PCI_PKTS_SENTX(offset) \ | |
156 | (0x0000000000000040ull + (((offset) & 3) * 16)) | |
157 | #define CVMX_PCI_PKTS_SENT_INT_LEV0 \ | |
158 | (0x0000000000000048ull) | |
159 | #define CVMX_PCI_PKTS_SENT_INT_LEV1 \ | |
160 | (0x0000000000000058ull) | |
161 | #define CVMX_PCI_PKTS_SENT_INT_LEV2 \ | |
162 | (0x0000000000000068ull) | |
163 | #define CVMX_PCI_PKTS_SENT_INT_LEV3 \ | |
164 | (0x0000000000000078ull) | |
165 | #define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) \ | |
166 | (0x0000000000000048ull + (((offset) & 3) * 16)) | |
167 | #define CVMX_PCI_PKTS_SENT_TIME0 \ | |
168 | (0x000000000000004Cull) | |
169 | #define CVMX_PCI_PKTS_SENT_TIME1 \ | |
170 | (0x000000000000005Cull) | |
171 | #define CVMX_PCI_PKTS_SENT_TIME2 \ | |
172 | (0x000000000000006Cull) | |
173 | #define CVMX_PCI_PKTS_SENT_TIME3 \ | |
174 | (0x000000000000007Cull) | |
175 | #define CVMX_PCI_PKTS_SENT_TIMEX(offset) \ | |
176 | (0x000000000000004Cull + (((offset) & 3) * 16)) | |
177 | #define CVMX_PCI_PKT_CREDITS0 \ | |
178 | (0x0000000000000044ull) | |
179 | #define CVMX_PCI_PKT_CREDITS1 \ | |
180 | (0x0000000000000054ull) | |
181 | #define CVMX_PCI_PKT_CREDITS2 \ | |
182 | (0x0000000000000064ull) | |
183 | #define CVMX_PCI_PKT_CREDITS3 \ | |
184 | (0x0000000000000074ull) | |
185 | #define CVMX_PCI_PKT_CREDITSX(offset) \ | |
186 | (0x0000000000000044ull + (((offset) & 3) * 16)) | |
187 | #define CVMX_PCI_READ_CMD_6 \ | |
188 | (0x0000000000000180ull) | |
189 | #define CVMX_PCI_READ_CMD_C \ | |
190 | (0x0000000000000184ull) | |
191 | #define CVMX_PCI_READ_CMD_E \ | |
192 | (0x0000000000000188ull) | |
193 | #define CVMX_PCI_READ_TIMEOUT \ | |
194 | CVMX_ADD_IO_SEG(0x00011F00000000B0ull) | |
195 | #define CVMX_PCI_SCM_REG \ | |
196 | (0x00000000000001A8ull) | |
197 | #define CVMX_PCI_TSR_REG \ | |
198 | (0x00000000000001B0ull) | |
199 | #define CVMX_PCI_WIN_RD_ADDR \ | |
200 | (0x0000000000000008ull) | |
201 | #define CVMX_PCI_WIN_RD_DATA \ | |
202 | (0x0000000000000020ull) | |
203 | #define CVMX_PCI_WIN_WR_ADDR \ | |
204 | (0x0000000000000000ull) | |
205 | #define CVMX_PCI_WIN_WR_DATA \ | |
206 | (0x0000000000000010ull) | |
207 | #define CVMX_PCI_WIN_WR_MASK \ | |
208 | (0x0000000000000018ull) | |
209 | ||
210 | union cvmx_pci_bar1_indexx { | |
211 | uint32_t u32; | |
212 | struct cvmx_pci_bar1_indexx_s { | |
213 | uint32_t reserved_18_31:14; | |
214 | uint32_t addr_idx:14; | |
215 | uint32_t ca:1; | |
216 | uint32_t end_swp:2; | |
217 | uint32_t addr_v:1; | |
218 | } s; | |
219 | struct cvmx_pci_bar1_indexx_s cn30xx; | |
220 | struct cvmx_pci_bar1_indexx_s cn31xx; | |
221 | struct cvmx_pci_bar1_indexx_s cn38xx; | |
222 | struct cvmx_pci_bar1_indexx_s cn38xxp2; | |
223 | struct cvmx_pci_bar1_indexx_s cn50xx; | |
224 | struct cvmx_pci_bar1_indexx_s cn58xx; | |
225 | struct cvmx_pci_bar1_indexx_s cn58xxp1; | |
226 | }; | |
227 | ||
228 | union cvmx_pci_bist_reg { | |
229 | uint64_t u64; | |
230 | struct cvmx_pci_bist_reg_s { | |
231 | uint64_t reserved_10_63:54; | |
232 | uint64_t rsp_bs:1; | |
233 | uint64_t dma0_bs:1; | |
234 | uint64_t cmd0_bs:1; | |
235 | uint64_t cmd_bs:1; | |
236 | uint64_t csr2p_bs:1; | |
237 | uint64_t csrr_bs:1; | |
238 | uint64_t rsp2p_bs:1; | |
239 | uint64_t csr2n_bs:1; | |
240 | uint64_t dat2n_bs:1; | |
241 | uint64_t dbg2n_bs:1; | |
242 | } s; | |
243 | struct cvmx_pci_bist_reg_s cn50xx; | |
244 | }; | |
245 | ||
246 | union cvmx_pci_cfg00 { | |
247 | uint32_t u32; | |
248 | struct cvmx_pci_cfg00_s { | |
249 | uint32_t devid:16; | |
250 | uint32_t vendid:16; | |
251 | } s; | |
252 | struct cvmx_pci_cfg00_s cn30xx; | |
253 | struct cvmx_pci_cfg00_s cn31xx; | |
254 | struct cvmx_pci_cfg00_s cn38xx; | |
255 | struct cvmx_pci_cfg00_s cn38xxp2; | |
256 | struct cvmx_pci_cfg00_s cn50xx; | |
257 | struct cvmx_pci_cfg00_s cn58xx; | |
258 | struct cvmx_pci_cfg00_s cn58xxp1; | |
259 | }; | |
260 | ||
261 | union cvmx_pci_cfg01 { | |
262 | uint32_t u32; | |
263 | struct cvmx_pci_cfg01_s { | |
264 | uint32_t dpe:1; | |
265 | uint32_t sse:1; | |
266 | uint32_t rma:1; | |
267 | uint32_t rta:1; | |
268 | uint32_t sta:1; | |
269 | uint32_t devt:2; | |
270 | uint32_t mdpe:1; | |
271 | uint32_t fbb:1; | |
272 | uint32_t reserved_22_22:1; | |
273 | uint32_t m66:1; | |
274 | uint32_t cle:1; | |
275 | uint32_t i_stat:1; | |
276 | uint32_t reserved_11_18:8; | |
277 | uint32_t i_dis:1; | |
278 | uint32_t fbbe:1; | |
279 | uint32_t see:1; | |
280 | uint32_t ads:1; | |
281 | uint32_t pee:1; | |
282 | uint32_t vps:1; | |
283 | uint32_t mwice:1; | |
284 | uint32_t scse:1; | |
285 | uint32_t me:1; | |
286 | uint32_t msae:1; | |
287 | uint32_t isae:1; | |
288 | } s; | |
289 | struct cvmx_pci_cfg01_s cn30xx; | |
290 | struct cvmx_pci_cfg01_s cn31xx; | |
291 | struct cvmx_pci_cfg01_s cn38xx; | |
292 | struct cvmx_pci_cfg01_s cn38xxp2; | |
293 | struct cvmx_pci_cfg01_s cn50xx; | |
294 | struct cvmx_pci_cfg01_s cn58xx; | |
295 | struct cvmx_pci_cfg01_s cn58xxp1; | |
296 | }; | |
297 | ||
298 | union cvmx_pci_cfg02 { | |
299 | uint32_t u32; | |
300 | struct cvmx_pci_cfg02_s { | |
301 | uint32_t cc:24; | |
302 | uint32_t rid:8; | |
303 | } s; | |
304 | struct cvmx_pci_cfg02_s cn30xx; | |
305 | struct cvmx_pci_cfg02_s cn31xx; | |
306 | struct cvmx_pci_cfg02_s cn38xx; | |
307 | struct cvmx_pci_cfg02_s cn38xxp2; | |
308 | struct cvmx_pci_cfg02_s cn50xx; | |
309 | struct cvmx_pci_cfg02_s cn58xx; | |
310 | struct cvmx_pci_cfg02_s cn58xxp1; | |
311 | }; | |
312 | ||
313 | union cvmx_pci_cfg03 { | |
314 | uint32_t u32; | |
315 | struct cvmx_pci_cfg03_s { | |
316 | uint32_t bcap:1; | |
317 | uint32_t brb:1; | |
318 | uint32_t reserved_28_29:2; | |
319 | uint32_t bcod:4; | |
320 | uint32_t ht:8; | |
321 | uint32_t lt:8; | |
322 | uint32_t cls:8; | |
323 | } s; | |
324 | struct cvmx_pci_cfg03_s cn30xx; | |
325 | struct cvmx_pci_cfg03_s cn31xx; | |
326 | struct cvmx_pci_cfg03_s cn38xx; | |
327 | struct cvmx_pci_cfg03_s cn38xxp2; | |
328 | struct cvmx_pci_cfg03_s cn50xx; | |
329 | struct cvmx_pci_cfg03_s cn58xx; | |
330 | struct cvmx_pci_cfg03_s cn58xxp1; | |
331 | }; | |
332 | ||
333 | union cvmx_pci_cfg04 { | |
334 | uint32_t u32; | |
335 | struct cvmx_pci_cfg04_s { | |
336 | uint32_t lbase:20; | |
337 | uint32_t lbasez:8; | |
338 | uint32_t pf:1; | |
339 | uint32_t typ:2; | |
340 | uint32_t mspc:1; | |
341 | } s; | |
342 | struct cvmx_pci_cfg04_s cn30xx; | |
343 | struct cvmx_pci_cfg04_s cn31xx; | |
344 | struct cvmx_pci_cfg04_s cn38xx; | |
345 | struct cvmx_pci_cfg04_s cn38xxp2; | |
346 | struct cvmx_pci_cfg04_s cn50xx; | |
347 | struct cvmx_pci_cfg04_s cn58xx; | |
348 | struct cvmx_pci_cfg04_s cn58xxp1; | |
349 | }; | |
350 | ||
351 | union cvmx_pci_cfg05 { | |
352 | uint32_t u32; | |
353 | struct cvmx_pci_cfg05_s { | |
354 | uint32_t hbase:32; | |
355 | } s; | |
356 | struct cvmx_pci_cfg05_s cn30xx; | |
357 | struct cvmx_pci_cfg05_s cn31xx; | |
358 | struct cvmx_pci_cfg05_s cn38xx; | |
359 | struct cvmx_pci_cfg05_s cn38xxp2; | |
360 | struct cvmx_pci_cfg05_s cn50xx; | |
361 | struct cvmx_pci_cfg05_s cn58xx; | |
362 | struct cvmx_pci_cfg05_s cn58xxp1; | |
363 | }; | |
364 | ||
365 | union cvmx_pci_cfg06 { | |
366 | uint32_t u32; | |
367 | struct cvmx_pci_cfg06_s { | |
368 | uint32_t lbase:5; | |
369 | uint32_t lbasez:23; | |
370 | uint32_t pf:1; | |
371 | uint32_t typ:2; | |
372 | uint32_t mspc:1; | |
373 | } s; | |
374 | struct cvmx_pci_cfg06_s cn30xx; | |
375 | struct cvmx_pci_cfg06_s cn31xx; | |
376 | struct cvmx_pci_cfg06_s cn38xx; | |
377 | struct cvmx_pci_cfg06_s cn38xxp2; | |
378 | struct cvmx_pci_cfg06_s cn50xx; | |
379 | struct cvmx_pci_cfg06_s cn58xx; | |
380 | struct cvmx_pci_cfg06_s cn58xxp1; | |
381 | }; | |
382 | ||
383 | union cvmx_pci_cfg07 { | |
384 | uint32_t u32; | |
385 | struct cvmx_pci_cfg07_s { | |
386 | uint32_t hbase:32; | |
387 | } s; | |
388 | struct cvmx_pci_cfg07_s cn30xx; | |
389 | struct cvmx_pci_cfg07_s cn31xx; | |
390 | struct cvmx_pci_cfg07_s cn38xx; | |
391 | struct cvmx_pci_cfg07_s cn38xxp2; | |
392 | struct cvmx_pci_cfg07_s cn50xx; | |
393 | struct cvmx_pci_cfg07_s cn58xx; | |
394 | struct cvmx_pci_cfg07_s cn58xxp1; | |
395 | }; | |
396 | ||
397 | union cvmx_pci_cfg08 { | |
398 | uint32_t u32; | |
399 | struct cvmx_pci_cfg08_s { | |
400 | uint32_t lbasez:28; | |
401 | uint32_t pf:1; | |
402 | uint32_t typ:2; | |
403 | uint32_t mspc:1; | |
404 | } s; | |
405 | struct cvmx_pci_cfg08_s cn30xx; | |
406 | struct cvmx_pci_cfg08_s cn31xx; | |
407 | struct cvmx_pci_cfg08_s cn38xx; | |
408 | struct cvmx_pci_cfg08_s cn38xxp2; | |
409 | struct cvmx_pci_cfg08_s cn50xx; | |
410 | struct cvmx_pci_cfg08_s cn58xx; | |
411 | struct cvmx_pci_cfg08_s cn58xxp1; | |
412 | }; | |
413 | ||
414 | union cvmx_pci_cfg09 { | |
415 | uint32_t u32; | |
416 | struct cvmx_pci_cfg09_s { | |
417 | uint32_t hbase:25; | |
418 | uint32_t hbasez:7; | |
419 | } s; | |
420 | struct cvmx_pci_cfg09_s cn30xx; | |
421 | struct cvmx_pci_cfg09_s cn31xx; | |
422 | struct cvmx_pci_cfg09_s cn38xx; | |
423 | struct cvmx_pci_cfg09_s cn38xxp2; | |
424 | struct cvmx_pci_cfg09_s cn50xx; | |
425 | struct cvmx_pci_cfg09_s cn58xx; | |
426 | struct cvmx_pci_cfg09_s cn58xxp1; | |
427 | }; | |
428 | ||
429 | union cvmx_pci_cfg10 { | |
430 | uint32_t u32; | |
431 | struct cvmx_pci_cfg10_s { | |
432 | uint32_t cisp:32; | |
433 | } s; | |
434 | struct cvmx_pci_cfg10_s cn30xx; | |
435 | struct cvmx_pci_cfg10_s cn31xx; | |
436 | struct cvmx_pci_cfg10_s cn38xx; | |
437 | struct cvmx_pci_cfg10_s cn38xxp2; | |
438 | struct cvmx_pci_cfg10_s cn50xx; | |
439 | struct cvmx_pci_cfg10_s cn58xx; | |
440 | struct cvmx_pci_cfg10_s cn58xxp1; | |
441 | }; | |
442 | ||
443 | union cvmx_pci_cfg11 { | |
444 | uint32_t u32; | |
445 | struct cvmx_pci_cfg11_s { | |
446 | uint32_t ssid:16; | |
447 | uint32_t ssvid:16; | |
448 | } s; | |
449 | struct cvmx_pci_cfg11_s cn30xx; | |
450 | struct cvmx_pci_cfg11_s cn31xx; | |
451 | struct cvmx_pci_cfg11_s cn38xx; | |
452 | struct cvmx_pci_cfg11_s cn38xxp2; | |
453 | struct cvmx_pci_cfg11_s cn50xx; | |
454 | struct cvmx_pci_cfg11_s cn58xx; | |
455 | struct cvmx_pci_cfg11_s cn58xxp1; | |
456 | }; | |
457 | ||
458 | union cvmx_pci_cfg12 { | |
459 | uint32_t u32; | |
460 | struct cvmx_pci_cfg12_s { | |
461 | uint32_t erbar:16; | |
462 | uint32_t erbarz:5; | |
463 | uint32_t reserved_1_10:10; | |
464 | uint32_t erbar_en:1; | |
465 | } s; | |
466 | struct cvmx_pci_cfg12_s cn30xx; | |
467 | struct cvmx_pci_cfg12_s cn31xx; | |
468 | struct cvmx_pci_cfg12_s cn38xx; | |
469 | struct cvmx_pci_cfg12_s cn38xxp2; | |
470 | struct cvmx_pci_cfg12_s cn50xx; | |
471 | struct cvmx_pci_cfg12_s cn58xx; | |
472 | struct cvmx_pci_cfg12_s cn58xxp1; | |
473 | }; | |
474 | ||
475 | union cvmx_pci_cfg13 { | |
476 | uint32_t u32; | |
477 | struct cvmx_pci_cfg13_s { | |
478 | uint32_t reserved_8_31:24; | |
479 | uint32_t cp:8; | |
480 | } s; | |
481 | struct cvmx_pci_cfg13_s cn30xx; | |
482 | struct cvmx_pci_cfg13_s cn31xx; | |
483 | struct cvmx_pci_cfg13_s cn38xx; | |
484 | struct cvmx_pci_cfg13_s cn38xxp2; | |
485 | struct cvmx_pci_cfg13_s cn50xx; | |
486 | struct cvmx_pci_cfg13_s cn58xx; | |
487 | struct cvmx_pci_cfg13_s cn58xxp1; | |
488 | }; | |
489 | ||
490 | union cvmx_pci_cfg15 { | |
491 | uint32_t u32; | |
492 | struct cvmx_pci_cfg15_s { | |
493 | uint32_t ml:8; | |
494 | uint32_t mg:8; | |
495 | uint32_t inta:8; | |
496 | uint32_t il:8; | |
497 | } s; | |
498 | struct cvmx_pci_cfg15_s cn30xx; | |
499 | struct cvmx_pci_cfg15_s cn31xx; | |
500 | struct cvmx_pci_cfg15_s cn38xx; | |
501 | struct cvmx_pci_cfg15_s cn38xxp2; | |
502 | struct cvmx_pci_cfg15_s cn50xx; | |
503 | struct cvmx_pci_cfg15_s cn58xx; | |
504 | struct cvmx_pci_cfg15_s cn58xxp1; | |
505 | }; | |
506 | ||
507 | union cvmx_pci_cfg16 { | |
508 | uint32_t u32; | |
509 | struct cvmx_pci_cfg16_s { | |
510 | uint32_t trdnpr:1; | |
511 | uint32_t trdard:1; | |
512 | uint32_t rdsati:1; | |
513 | uint32_t trdrs:1; | |
514 | uint32_t trtae:1; | |
515 | uint32_t twsei:1; | |
516 | uint32_t twsen:1; | |
517 | uint32_t twtae:1; | |
518 | uint32_t tmae:1; | |
519 | uint32_t tslte:3; | |
520 | uint32_t tilt:4; | |
521 | uint32_t pbe:12; | |
522 | uint32_t dppmr:1; | |
523 | uint32_t reserved_2_2:1; | |
524 | uint32_t tswc:1; | |
525 | uint32_t mltd:1; | |
526 | } s; | |
527 | struct cvmx_pci_cfg16_s cn30xx; | |
528 | struct cvmx_pci_cfg16_s cn31xx; | |
529 | struct cvmx_pci_cfg16_s cn38xx; | |
530 | struct cvmx_pci_cfg16_s cn38xxp2; | |
531 | struct cvmx_pci_cfg16_s cn50xx; | |
532 | struct cvmx_pci_cfg16_s cn58xx; | |
533 | struct cvmx_pci_cfg16_s cn58xxp1; | |
534 | }; | |
535 | ||
536 | union cvmx_pci_cfg17 { | |
537 | uint32_t u32; | |
538 | struct cvmx_pci_cfg17_s { | |
539 | uint32_t tscme:32; | |
540 | } s; | |
541 | struct cvmx_pci_cfg17_s cn30xx; | |
542 | struct cvmx_pci_cfg17_s cn31xx; | |
543 | struct cvmx_pci_cfg17_s cn38xx; | |
544 | struct cvmx_pci_cfg17_s cn38xxp2; | |
545 | struct cvmx_pci_cfg17_s cn50xx; | |
546 | struct cvmx_pci_cfg17_s cn58xx; | |
547 | struct cvmx_pci_cfg17_s cn58xxp1; | |
548 | }; | |
549 | ||
550 | union cvmx_pci_cfg18 { | |
551 | uint32_t u32; | |
552 | struct cvmx_pci_cfg18_s { | |
553 | uint32_t tdsrps:32; | |
554 | } s; | |
555 | struct cvmx_pci_cfg18_s cn30xx; | |
556 | struct cvmx_pci_cfg18_s cn31xx; | |
557 | struct cvmx_pci_cfg18_s cn38xx; | |
558 | struct cvmx_pci_cfg18_s cn38xxp2; | |
559 | struct cvmx_pci_cfg18_s cn50xx; | |
560 | struct cvmx_pci_cfg18_s cn58xx; | |
561 | struct cvmx_pci_cfg18_s cn58xxp1; | |
562 | }; | |
563 | ||
564 | union cvmx_pci_cfg19 { | |
565 | uint32_t u32; | |
566 | struct cvmx_pci_cfg19_s { | |
567 | uint32_t mrbcm:1; | |
568 | uint32_t mrbci:1; | |
569 | uint32_t mdwe:1; | |
570 | uint32_t mdre:1; | |
571 | uint32_t mdrimc:1; | |
572 | uint32_t mdrrmc:3; | |
573 | uint32_t tmes:8; | |
574 | uint32_t teci:1; | |
575 | uint32_t tmei:1; | |
576 | uint32_t tmse:1; | |
577 | uint32_t tmdpes:1; | |
578 | uint32_t tmapes:1; | |
579 | uint32_t reserved_9_10:2; | |
580 | uint32_t tibcd:1; | |
581 | uint32_t tibde:1; | |
582 | uint32_t reserved_6_6:1; | |
583 | uint32_t tidomc:1; | |
584 | uint32_t tdomc:5; | |
585 | } s; | |
586 | struct cvmx_pci_cfg19_s cn30xx; | |
587 | struct cvmx_pci_cfg19_s cn31xx; | |
588 | struct cvmx_pci_cfg19_s cn38xx; | |
589 | struct cvmx_pci_cfg19_s cn38xxp2; | |
590 | struct cvmx_pci_cfg19_s cn50xx; | |
591 | struct cvmx_pci_cfg19_s cn58xx; | |
592 | struct cvmx_pci_cfg19_s cn58xxp1; | |
593 | }; | |
594 | ||
595 | union cvmx_pci_cfg20 { | |
596 | uint32_t u32; | |
597 | struct cvmx_pci_cfg20_s { | |
598 | uint32_t mdsp:32; | |
599 | } s; | |
600 | struct cvmx_pci_cfg20_s cn30xx; | |
601 | struct cvmx_pci_cfg20_s cn31xx; | |
602 | struct cvmx_pci_cfg20_s cn38xx; | |
603 | struct cvmx_pci_cfg20_s cn38xxp2; | |
604 | struct cvmx_pci_cfg20_s cn50xx; | |
605 | struct cvmx_pci_cfg20_s cn58xx; | |
606 | struct cvmx_pci_cfg20_s cn58xxp1; | |
607 | }; | |
608 | ||
609 | union cvmx_pci_cfg21 { | |
610 | uint32_t u32; | |
611 | struct cvmx_pci_cfg21_s { | |
612 | uint32_t scmre:32; | |
613 | } s; | |
614 | struct cvmx_pci_cfg21_s cn30xx; | |
615 | struct cvmx_pci_cfg21_s cn31xx; | |
616 | struct cvmx_pci_cfg21_s cn38xx; | |
617 | struct cvmx_pci_cfg21_s cn38xxp2; | |
618 | struct cvmx_pci_cfg21_s cn50xx; | |
619 | struct cvmx_pci_cfg21_s cn58xx; | |
620 | struct cvmx_pci_cfg21_s cn58xxp1; | |
621 | }; | |
622 | ||
623 | union cvmx_pci_cfg22 { | |
624 | uint32_t u32; | |
625 | struct cvmx_pci_cfg22_s { | |
626 | uint32_t mac:7; | |
627 | uint32_t reserved_19_24:6; | |
628 | uint32_t flush:1; | |
629 | uint32_t mra:1; | |
630 | uint32_t mtta:1; | |
631 | uint32_t mrv:8; | |
632 | uint32_t mttv:8; | |
633 | } s; | |
634 | struct cvmx_pci_cfg22_s cn30xx; | |
635 | struct cvmx_pci_cfg22_s cn31xx; | |
636 | struct cvmx_pci_cfg22_s cn38xx; | |
637 | struct cvmx_pci_cfg22_s cn38xxp2; | |
638 | struct cvmx_pci_cfg22_s cn50xx; | |
639 | struct cvmx_pci_cfg22_s cn58xx; | |
640 | struct cvmx_pci_cfg22_s cn58xxp1; | |
641 | }; | |
642 | ||
643 | union cvmx_pci_cfg56 { | |
644 | uint32_t u32; | |
645 | struct cvmx_pci_cfg56_s { | |
646 | uint32_t reserved_23_31:9; | |
647 | uint32_t most:3; | |
648 | uint32_t mmbc:2; | |
649 | uint32_t roe:1; | |
650 | uint32_t dpere:1; | |
651 | uint32_t ncp:8; | |
652 | uint32_t pxcid:8; | |
653 | } s; | |
654 | struct cvmx_pci_cfg56_s cn30xx; | |
655 | struct cvmx_pci_cfg56_s cn31xx; | |
656 | struct cvmx_pci_cfg56_s cn38xx; | |
657 | struct cvmx_pci_cfg56_s cn38xxp2; | |
658 | struct cvmx_pci_cfg56_s cn50xx; | |
659 | struct cvmx_pci_cfg56_s cn58xx; | |
660 | struct cvmx_pci_cfg56_s cn58xxp1; | |
661 | }; | |
662 | ||
663 | union cvmx_pci_cfg57 { | |
664 | uint32_t u32; | |
665 | struct cvmx_pci_cfg57_s { | |
666 | uint32_t reserved_30_31:2; | |
667 | uint32_t scemr:1; | |
668 | uint32_t mcrsd:3; | |
669 | uint32_t mostd:3; | |
670 | uint32_t mmrbcd:2; | |
671 | uint32_t dc:1; | |
672 | uint32_t usc:1; | |
673 | uint32_t scd:1; | |
674 | uint32_t m133:1; | |
675 | uint32_t w64:1; | |
676 | uint32_t bn:8; | |
677 | uint32_t dn:5; | |
678 | uint32_t fn:3; | |
679 | } s; | |
680 | struct cvmx_pci_cfg57_s cn30xx; | |
681 | struct cvmx_pci_cfg57_s cn31xx; | |
682 | struct cvmx_pci_cfg57_s cn38xx; | |
683 | struct cvmx_pci_cfg57_s cn38xxp2; | |
684 | struct cvmx_pci_cfg57_s cn50xx; | |
685 | struct cvmx_pci_cfg57_s cn58xx; | |
686 | struct cvmx_pci_cfg57_s cn58xxp1; | |
687 | }; | |
688 | ||
689 | union cvmx_pci_cfg58 { | |
690 | uint32_t u32; | |
691 | struct cvmx_pci_cfg58_s { | |
692 | uint32_t pmes:5; | |
693 | uint32_t d2s:1; | |
694 | uint32_t d1s:1; | |
695 | uint32_t auxc:3; | |
696 | uint32_t dsi:1; | |
697 | uint32_t reserved_20_20:1; | |
698 | uint32_t pmec:1; | |
699 | uint32_t pcimiv:3; | |
700 | uint32_t ncp:8; | |
701 | uint32_t pmcid:8; | |
702 | } s; | |
703 | struct cvmx_pci_cfg58_s cn30xx; | |
704 | struct cvmx_pci_cfg58_s cn31xx; | |
705 | struct cvmx_pci_cfg58_s cn38xx; | |
706 | struct cvmx_pci_cfg58_s cn38xxp2; | |
707 | struct cvmx_pci_cfg58_s cn50xx; | |
708 | struct cvmx_pci_cfg58_s cn58xx; | |
709 | struct cvmx_pci_cfg58_s cn58xxp1; | |
710 | }; | |
711 | ||
712 | union cvmx_pci_cfg59 { | |
713 | uint32_t u32; | |
714 | struct cvmx_pci_cfg59_s { | |
715 | uint32_t pmdia:8; | |
716 | uint32_t bpccen:1; | |
717 | uint32_t bd3h:1; | |
718 | uint32_t reserved_16_21:6; | |
719 | uint32_t pmess:1; | |
720 | uint32_t pmedsia:2; | |
721 | uint32_t pmds:4; | |
722 | uint32_t pmeens:1; | |
723 | uint32_t reserved_2_7:6; | |
724 | uint32_t ps:2; | |
725 | } s; | |
726 | struct cvmx_pci_cfg59_s cn30xx; | |
727 | struct cvmx_pci_cfg59_s cn31xx; | |
728 | struct cvmx_pci_cfg59_s cn38xx; | |
729 | struct cvmx_pci_cfg59_s cn38xxp2; | |
730 | struct cvmx_pci_cfg59_s cn50xx; | |
731 | struct cvmx_pci_cfg59_s cn58xx; | |
732 | struct cvmx_pci_cfg59_s cn58xxp1; | |
733 | }; | |
734 | ||
735 | union cvmx_pci_cfg60 { | |
736 | uint32_t u32; | |
737 | struct cvmx_pci_cfg60_s { | |
738 | uint32_t reserved_24_31:8; | |
739 | uint32_t m64:1; | |
740 | uint32_t mme:3; | |
741 | uint32_t mmc:3; | |
742 | uint32_t msien:1; | |
743 | uint32_t ncp:8; | |
744 | uint32_t msicid:8; | |
745 | } s; | |
746 | struct cvmx_pci_cfg60_s cn30xx; | |
747 | struct cvmx_pci_cfg60_s cn31xx; | |
748 | struct cvmx_pci_cfg60_s cn38xx; | |
749 | struct cvmx_pci_cfg60_s cn38xxp2; | |
750 | struct cvmx_pci_cfg60_s cn50xx; | |
751 | struct cvmx_pci_cfg60_s cn58xx; | |
752 | struct cvmx_pci_cfg60_s cn58xxp1; | |
753 | }; | |
754 | ||
755 | union cvmx_pci_cfg61 { | |
756 | uint32_t u32; | |
757 | struct cvmx_pci_cfg61_s { | |
758 | uint32_t msi31t2:30; | |
759 | uint32_t reserved_0_1:2; | |
760 | } s; | |
761 | struct cvmx_pci_cfg61_s cn30xx; | |
762 | struct cvmx_pci_cfg61_s cn31xx; | |
763 | struct cvmx_pci_cfg61_s cn38xx; | |
764 | struct cvmx_pci_cfg61_s cn38xxp2; | |
765 | struct cvmx_pci_cfg61_s cn50xx; | |
766 | struct cvmx_pci_cfg61_s cn58xx; | |
767 | struct cvmx_pci_cfg61_s cn58xxp1; | |
768 | }; | |
769 | ||
770 | union cvmx_pci_cfg62 { | |
771 | uint32_t u32; | |
772 | struct cvmx_pci_cfg62_s { | |
773 | uint32_t msi:32; | |
774 | } s; | |
775 | struct cvmx_pci_cfg62_s cn30xx; | |
776 | struct cvmx_pci_cfg62_s cn31xx; | |
777 | struct cvmx_pci_cfg62_s cn38xx; | |
778 | struct cvmx_pci_cfg62_s cn38xxp2; | |
779 | struct cvmx_pci_cfg62_s cn50xx; | |
780 | struct cvmx_pci_cfg62_s cn58xx; | |
781 | struct cvmx_pci_cfg62_s cn58xxp1; | |
782 | }; | |
783 | ||
784 | union cvmx_pci_cfg63 { | |
785 | uint32_t u32; | |
786 | struct cvmx_pci_cfg63_s { | |
787 | uint32_t reserved_16_31:16; | |
788 | uint32_t msimd:16; | |
789 | } s; | |
790 | struct cvmx_pci_cfg63_s cn30xx; | |
791 | struct cvmx_pci_cfg63_s cn31xx; | |
792 | struct cvmx_pci_cfg63_s cn38xx; | |
793 | struct cvmx_pci_cfg63_s cn38xxp2; | |
794 | struct cvmx_pci_cfg63_s cn50xx; | |
795 | struct cvmx_pci_cfg63_s cn58xx; | |
796 | struct cvmx_pci_cfg63_s cn58xxp1; | |
797 | }; | |
798 | ||
799 | union cvmx_pci_cnt_reg { | |
800 | uint64_t u64; | |
801 | struct cvmx_pci_cnt_reg_s { | |
802 | uint64_t reserved_38_63:26; | |
803 | uint64_t hm_pcix:1; | |
804 | uint64_t hm_speed:2; | |
805 | uint64_t ap_pcix:1; | |
806 | uint64_t ap_speed:2; | |
807 | uint64_t pcicnt:32; | |
808 | } s; | |
809 | struct cvmx_pci_cnt_reg_s cn50xx; | |
810 | struct cvmx_pci_cnt_reg_s cn58xx; | |
811 | struct cvmx_pci_cnt_reg_s cn58xxp1; | |
812 | }; | |
813 | ||
814 | union cvmx_pci_ctl_status_2 { | |
815 | uint32_t u32; | |
816 | struct cvmx_pci_ctl_status_2_s { | |
817 | uint32_t reserved_29_31:3; | |
818 | uint32_t bb1_hole:3; | |
819 | uint32_t bb1_siz:1; | |
820 | uint32_t bb_ca:1; | |
821 | uint32_t bb_es:2; | |
822 | uint32_t bb1:1; | |
823 | uint32_t bb0:1; | |
824 | uint32_t erst_n:1; | |
825 | uint32_t bar2pres:1; | |
826 | uint32_t scmtyp:1; | |
827 | uint32_t scm:1; | |
828 | uint32_t en_wfilt:1; | |
829 | uint32_t reserved_14_14:1; | |
830 | uint32_t ap_pcix:1; | |
831 | uint32_t ap_64ad:1; | |
832 | uint32_t b12_bist:1; | |
833 | uint32_t pmo_amod:1; | |
834 | uint32_t pmo_fpc:3; | |
835 | uint32_t tsr_hwm:3; | |
836 | uint32_t bar2_enb:1; | |
837 | uint32_t bar2_esx:2; | |
838 | uint32_t bar2_cax:1; | |
839 | } s; | |
840 | struct cvmx_pci_ctl_status_2_s cn30xx; | |
841 | struct cvmx_pci_ctl_status_2_cn31xx { | |
842 | uint32_t reserved_20_31:12; | |
843 | uint32_t erst_n:1; | |
844 | uint32_t bar2pres:1; | |
845 | uint32_t scmtyp:1; | |
846 | uint32_t scm:1; | |
847 | uint32_t en_wfilt:1; | |
848 | uint32_t reserved_14_14:1; | |
849 | uint32_t ap_pcix:1; | |
850 | uint32_t ap_64ad:1; | |
851 | uint32_t b12_bist:1; | |
852 | uint32_t pmo_amod:1; | |
853 | uint32_t pmo_fpc:3; | |
854 | uint32_t tsr_hwm:3; | |
855 | uint32_t bar2_enb:1; | |
856 | uint32_t bar2_esx:2; | |
857 | uint32_t bar2_cax:1; | |
858 | } cn31xx; | |
859 | struct cvmx_pci_ctl_status_2_s cn38xx; | |
860 | struct cvmx_pci_ctl_status_2_cn31xx cn38xxp2; | |
861 | struct cvmx_pci_ctl_status_2_s cn50xx; | |
862 | struct cvmx_pci_ctl_status_2_s cn58xx; | |
863 | struct cvmx_pci_ctl_status_2_s cn58xxp1; | |
864 | }; | |
865 | ||
866 | union cvmx_pci_dbellx { | |
867 | uint32_t u32; | |
868 | struct cvmx_pci_dbellx_s { | |
869 | uint32_t reserved_16_31:16; | |
870 | uint32_t inc_val:16; | |
871 | } s; | |
872 | struct cvmx_pci_dbellx_s cn30xx; | |
873 | struct cvmx_pci_dbellx_s cn31xx; | |
874 | struct cvmx_pci_dbellx_s cn38xx; | |
875 | struct cvmx_pci_dbellx_s cn38xxp2; | |
876 | struct cvmx_pci_dbellx_s cn50xx; | |
877 | struct cvmx_pci_dbellx_s cn58xx; | |
878 | struct cvmx_pci_dbellx_s cn58xxp1; | |
879 | }; | |
880 | ||
881 | union cvmx_pci_dma_cntx { | |
882 | uint32_t u32; | |
883 | struct cvmx_pci_dma_cntx_s { | |
884 | uint32_t dma_cnt:32; | |
885 | } s; | |
886 | struct cvmx_pci_dma_cntx_s cn30xx; | |
887 | struct cvmx_pci_dma_cntx_s cn31xx; | |
888 | struct cvmx_pci_dma_cntx_s cn38xx; | |
889 | struct cvmx_pci_dma_cntx_s cn38xxp2; | |
890 | struct cvmx_pci_dma_cntx_s cn50xx; | |
891 | struct cvmx_pci_dma_cntx_s cn58xx; | |
892 | struct cvmx_pci_dma_cntx_s cn58xxp1; | |
893 | }; | |
894 | ||
895 | union cvmx_pci_dma_int_levx { | |
896 | uint32_t u32; | |
897 | struct cvmx_pci_dma_int_levx_s { | |
898 | uint32_t pkt_cnt:32; | |
899 | } s; | |
900 | struct cvmx_pci_dma_int_levx_s cn30xx; | |
901 | struct cvmx_pci_dma_int_levx_s cn31xx; | |
902 | struct cvmx_pci_dma_int_levx_s cn38xx; | |
903 | struct cvmx_pci_dma_int_levx_s cn38xxp2; | |
904 | struct cvmx_pci_dma_int_levx_s cn50xx; | |
905 | struct cvmx_pci_dma_int_levx_s cn58xx; | |
906 | struct cvmx_pci_dma_int_levx_s cn58xxp1; | |
907 | }; | |
908 | ||
909 | union cvmx_pci_dma_timex { | |
910 | uint32_t u32; | |
911 | struct cvmx_pci_dma_timex_s { | |
912 | uint32_t dma_time:32; | |
913 | } s; | |
914 | struct cvmx_pci_dma_timex_s cn30xx; | |
915 | struct cvmx_pci_dma_timex_s cn31xx; | |
916 | struct cvmx_pci_dma_timex_s cn38xx; | |
917 | struct cvmx_pci_dma_timex_s cn38xxp2; | |
918 | struct cvmx_pci_dma_timex_s cn50xx; | |
919 | struct cvmx_pci_dma_timex_s cn58xx; | |
920 | struct cvmx_pci_dma_timex_s cn58xxp1; | |
921 | }; | |
922 | ||
923 | union cvmx_pci_instr_countx { | |
924 | uint32_t u32; | |
925 | struct cvmx_pci_instr_countx_s { | |
926 | uint32_t icnt:32; | |
927 | } s; | |
928 | struct cvmx_pci_instr_countx_s cn30xx; | |
929 | struct cvmx_pci_instr_countx_s cn31xx; | |
930 | struct cvmx_pci_instr_countx_s cn38xx; | |
931 | struct cvmx_pci_instr_countx_s cn38xxp2; | |
932 | struct cvmx_pci_instr_countx_s cn50xx; | |
933 | struct cvmx_pci_instr_countx_s cn58xx; | |
934 | struct cvmx_pci_instr_countx_s cn58xxp1; | |
935 | }; | |
936 | ||
937 | union cvmx_pci_int_enb { | |
938 | uint64_t u64; | |
939 | struct cvmx_pci_int_enb_s { | |
940 | uint64_t reserved_34_63:30; | |
941 | uint64_t ill_rd:1; | |
942 | uint64_t ill_wr:1; | |
943 | uint64_t win_wr:1; | |
944 | uint64_t dma1_fi:1; | |
945 | uint64_t dma0_fi:1; | |
946 | uint64_t idtime1:1; | |
947 | uint64_t idtime0:1; | |
948 | uint64_t idcnt1:1; | |
949 | uint64_t idcnt0:1; | |
950 | uint64_t iptime3:1; | |
951 | uint64_t iptime2:1; | |
952 | uint64_t iptime1:1; | |
953 | uint64_t iptime0:1; | |
954 | uint64_t ipcnt3:1; | |
955 | uint64_t ipcnt2:1; | |
956 | uint64_t ipcnt1:1; | |
957 | uint64_t ipcnt0:1; | |
958 | uint64_t irsl_int:1; | |
959 | uint64_t ill_rrd:1; | |
960 | uint64_t ill_rwr:1; | |
961 | uint64_t idperr:1; | |
962 | uint64_t iaperr:1; | |
963 | uint64_t iserr:1; | |
964 | uint64_t itsr_abt:1; | |
965 | uint64_t imsc_msg:1; | |
966 | uint64_t imsi_mabt:1; | |
967 | uint64_t imsi_tabt:1; | |
968 | uint64_t imsi_per:1; | |
969 | uint64_t imr_tto:1; | |
970 | uint64_t imr_abt:1; | |
971 | uint64_t itr_abt:1; | |
972 | uint64_t imr_wtto:1; | |
973 | uint64_t imr_wabt:1; | |
974 | uint64_t itr_wabt:1; | |
975 | } s; | |
976 | struct cvmx_pci_int_enb_cn30xx { | |
977 | uint64_t reserved_34_63:30; | |
978 | uint64_t ill_rd:1; | |
979 | uint64_t ill_wr:1; | |
980 | uint64_t win_wr:1; | |
981 | uint64_t dma1_fi:1; | |
982 | uint64_t dma0_fi:1; | |
983 | uint64_t idtime1:1; | |
984 | uint64_t idtime0:1; | |
985 | uint64_t idcnt1:1; | |
986 | uint64_t idcnt0:1; | |
987 | uint64_t reserved_22_24:3; | |
988 | uint64_t iptime0:1; | |
989 | uint64_t reserved_18_20:3; | |
990 | uint64_t ipcnt0:1; | |
991 | uint64_t irsl_int:1; | |
992 | uint64_t ill_rrd:1; | |
993 | uint64_t ill_rwr:1; | |
994 | uint64_t idperr:1; | |
995 | uint64_t iaperr:1; | |
996 | uint64_t iserr:1; | |
997 | uint64_t itsr_abt:1; | |
998 | uint64_t imsc_msg:1; | |
999 | uint64_t imsi_mabt:1; | |
1000 | uint64_t imsi_tabt:1; | |
1001 | uint64_t imsi_per:1; | |
1002 | uint64_t imr_tto:1; | |
1003 | uint64_t imr_abt:1; | |
1004 | uint64_t itr_abt:1; | |
1005 | uint64_t imr_wtto:1; | |
1006 | uint64_t imr_wabt:1; | |
1007 | uint64_t itr_wabt:1; | |
1008 | } cn30xx; | |
1009 | struct cvmx_pci_int_enb_cn31xx { | |
1010 | uint64_t reserved_34_63:30; | |
1011 | uint64_t ill_rd:1; | |
1012 | uint64_t ill_wr:1; | |
1013 | uint64_t win_wr:1; | |
1014 | uint64_t dma1_fi:1; | |
1015 | uint64_t dma0_fi:1; | |
1016 | uint64_t idtime1:1; | |
1017 | uint64_t idtime0:1; | |
1018 | uint64_t idcnt1:1; | |
1019 | uint64_t idcnt0:1; | |
1020 | uint64_t reserved_23_24:2; | |
1021 | uint64_t iptime1:1; | |
1022 | uint64_t iptime0:1; | |
1023 | uint64_t reserved_19_20:2; | |
1024 | uint64_t ipcnt1:1; | |
1025 | uint64_t ipcnt0:1; | |
1026 | uint64_t irsl_int:1; | |
1027 | uint64_t ill_rrd:1; | |
1028 | uint64_t ill_rwr:1; | |
1029 | uint64_t idperr:1; | |
1030 | uint64_t iaperr:1; | |
1031 | uint64_t iserr:1; | |
1032 | uint64_t itsr_abt:1; | |
1033 | uint64_t imsc_msg:1; | |
1034 | uint64_t imsi_mabt:1; | |
1035 | uint64_t imsi_tabt:1; | |
1036 | uint64_t imsi_per:1; | |
1037 | uint64_t imr_tto:1; | |
1038 | uint64_t imr_abt:1; | |
1039 | uint64_t itr_abt:1; | |
1040 | uint64_t imr_wtto:1; | |
1041 | uint64_t imr_wabt:1; | |
1042 | uint64_t itr_wabt:1; | |
1043 | } cn31xx; | |
1044 | struct cvmx_pci_int_enb_s cn38xx; | |
1045 | struct cvmx_pci_int_enb_s cn38xxp2; | |
1046 | struct cvmx_pci_int_enb_cn31xx cn50xx; | |
1047 | struct cvmx_pci_int_enb_s cn58xx; | |
1048 | struct cvmx_pci_int_enb_s cn58xxp1; | |
1049 | }; | |
1050 | ||
1051 | union cvmx_pci_int_enb2 { | |
1052 | uint64_t u64; | |
1053 | struct cvmx_pci_int_enb2_s { | |
1054 | uint64_t reserved_34_63:30; | |
1055 | uint64_t ill_rd:1; | |
1056 | uint64_t ill_wr:1; | |
1057 | uint64_t win_wr:1; | |
1058 | uint64_t dma1_fi:1; | |
1059 | uint64_t dma0_fi:1; | |
1060 | uint64_t rdtime1:1; | |
1061 | uint64_t rdtime0:1; | |
1062 | uint64_t rdcnt1:1; | |
1063 | uint64_t rdcnt0:1; | |
1064 | uint64_t rptime3:1; | |
1065 | uint64_t rptime2:1; | |
1066 | uint64_t rptime1:1; | |
1067 | uint64_t rptime0:1; | |
1068 | uint64_t rpcnt3:1; | |
1069 | uint64_t rpcnt2:1; | |
1070 | uint64_t rpcnt1:1; | |
1071 | uint64_t rpcnt0:1; | |
1072 | uint64_t rrsl_int:1; | |
1073 | uint64_t ill_rrd:1; | |
1074 | uint64_t ill_rwr:1; | |
1075 | uint64_t rdperr:1; | |
1076 | uint64_t raperr:1; | |
1077 | uint64_t rserr:1; | |
1078 | uint64_t rtsr_abt:1; | |
1079 | uint64_t rmsc_msg:1; | |
1080 | uint64_t rmsi_mabt:1; | |
1081 | uint64_t rmsi_tabt:1; | |
1082 | uint64_t rmsi_per:1; | |
1083 | uint64_t rmr_tto:1; | |
1084 | uint64_t rmr_abt:1; | |
1085 | uint64_t rtr_abt:1; | |
1086 | uint64_t rmr_wtto:1; | |
1087 | uint64_t rmr_wabt:1; | |
1088 | uint64_t rtr_wabt:1; | |
1089 | } s; | |
1090 | struct cvmx_pci_int_enb2_cn30xx { | |
1091 | uint64_t reserved_34_63:30; | |
1092 | uint64_t ill_rd:1; | |
1093 | uint64_t ill_wr:1; | |
1094 | uint64_t win_wr:1; | |
1095 | uint64_t dma1_fi:1; | |
1096 | uint64_t dma0_fi:1; | |
1097 | uint64_t rdtime1:1; | |
1098 | uint64_t rdtime0:1; | |
1099 | uint64_t rdcnt1:1; | |
1100 | uint64_t rdcnt0:1; | |
1101 | uint64_t reserved_22_24:3; | |
1102 | uint64_t rptime0:1; | |
1103 | uint64_t reserved_18_20:3; | |
1104 | uint64_t rpcnt0:1; | |
1105 | uint64_t rrsl_int:1; | |
1106 | uint64_t ill_rrd:1; | |
1107 | uint64_t ill_rwr:1; | |
1108 | uint64_t rdperr:1; | |
1109 | uint64_t raperr:1; | |
1110 | uint64_t rserr:1; | |
1111 | uint64_t rtsr_abt:1; | |
1112 | uint64_t rmsc_msg:1; | |
1113 | uint64_t rmsi_mabt:1; | |
1114 | uint64_t rmsi_tabt:1; | |
1115 | uint64_t rmsi_per:1; | |
1116 | uint64_t rmr_tto:1; | |
1117 | uint64_t rmr_abt:1; | |
1118 | uint64_t rtr_abt:1; | |
1119 | uint64_t rmr_wtto:1; | |
1120 | uint64_t rmr_wabt:1; | |
1121 | uint64_t rtr_wabt:1; | |
1122 | } cn30xx; | |
1123 | struct cvmx_pci_int_enb2_cn31xx { | |
1124 | uint64_t reserved_34_63:30; | |
1125 | uint64_t ill_rd:1; | |
1126 | uint64_t ill_wr:1; | |
1127 | uint64_t win_wr:1; | |
1128 | uint64_t dma1_fi:1; | |
1129 | uint64_t dma0_fi:1; | |
1130 | uint64_t rdtime1:1; | |
1131 | uint64_t rdtime0:1; | |
1132 | uint64_t rdcnt1:1; | |
1133 | uint64_t rdcnt0:1; | |
1134 | uint64_t reserved_23_24:2; | |
1135 | uint64_t rptime1:1; | |
1136 | uint64_t rptime0:1; | |
1137 | uint64_t reserved_19_20:2; | |
1138 | uint64_t rpcnt1:1; | |
1139 | uint64_t rpcnt0:1; | |
1140 | uint64_t rrsl_int:1; | |
1141 | uint64_t ill_rrd:1; | |
1142 | uint64_t ill_rwr:1; | |
1143 | uint64_t rdperr:1; | |
1144 | uint64_t raperr:1; | |
1145 | uint64_t rserr:1; | |
1146 | uint64_t rtsr_abt:1; | |
1147 | uint64_t rmsc_msg:1; | |
1148 | uint64_t rmsi_mabt:1; | |
1149 | uint64_t rmsi_tabt:1; | |
1150 | uint64_t rmsi_per:1; | |
1151 | uint64_t rmr_tto:1; | |
1152 | uint64_t rmr_abt:1; | |
1153 | uint64_t rtr_abt:1; | |
1154 | uint64_t rmr_wtto:1; | |
1155 | uint64_t rmr_wabt:1; | |
1156 | uint64_t rtr_wabt:1; | |
1157 | } cn31xx; | |
1158 | struct cvmx_pci_int_enb2_s cn38xx; | |
1159 | struct cvmx_pci_int_enb2_s cn38xxp2; | |
1160 | struct cvmx_pci_int_enb2_cn31xx cn50xx; | |
1161 | struct cvmx_pci_int_enb2_s cn58xx; | |
1162 | struct cvmx_pci_int_enb2_s cn58xxp1; | |
1163 | }; | |
1164 | ||
1165 | union cvmx_pci_int_sum { | |
1166 | uint64_t u64; | |
1167 | struct cvmx_pci_int_sum_s { | |
1168 | uint64_t reserved_34_63:30; | |
1169 | uint64_t ill_rd:1; | |
1170 | uint64_t ill_wr:1; | |
1171 | uint64_t win_wr:1; | |
1172 | uint64_t dma1_fi:1; | |
1173 | uint64_t dma0_fi:1; | |
1174 | uint64_t dtime1:1; | |
1175 | uint64_t dtime0:1; | |
1176 | uint64_t dcnt1:1; | |
1177 | uint64_t dcnt0:1; | |
1178 | uint64_t ptime3:1; | |
1179 | uint64_t ptime2:1; | |
1180 | uint64_t ptime1:1; | |
1181 | uint64_t ptime0:1; | |
1182 | uint64_t pcnt3:1; | |
1183 | uint64_t pcnt2:1; | |
1184 | uint64_t pcnt1:1; | |
1185 | uint64_t pcnt0:1; | |
1186 | uint64_t rsl_int:1; | |
1187 | uint64_t ill_rrd:1; | |
1188 | uint64_t ill_rwr:1; | |
1189 | uint64_t dperr:1; | |
1190 | uint64_t aperr:1; | |
1191 | uint64_t serr:1; | |
1192 | uint64_t tsr_abt:1; | |
1193 | uint64_t msc_msg:1; | |
1194 | uint64_t msi_mabt:1; | |
1195 | uint64_t msi_tabt:1; | |
1196 | uint64_t msi_per:1; | |
1197 | uint64_t mr_tto:1; | |
1198 | uint64_t mr_abt:1; | |
1199 | uint64_t tr_abt:1; | |
1200 | uint64_t mr_wtto:1; | |
1201 | uint64_t mr_wabt:1; | |
1202 | uint64_t tr_wabt:1; | |
1203 | } s; | |
1204 | struct cvmx_pci_int_sum_cn30xx { | |
1205 | uint64_t reserved_34_63:30; | |
1206 | uint64_t ill_rd:1; | |
1207 | uint64_t ill_wr:1; | |
1208 | uint64_t win_wr:1; | |
1209 | uint64_t dma1_fi:1; | |
1210 | uint64_t dma0_fi:1; | |
1211 | uint64_t dtime1:1; | |
1212 | uint64_t dtime0:1; | |
1213 | uint64_t dcnt1:1; | |
1214 | uint64_t dcnt0:1; | |
1215 | uint64_t reserved_22_24:3; | |
1216 | uint64_t ptime0:1; | |
1217 | uint64_t reserved_18_20:3; | |
1218 | uint64_t pcnt0:1; | |
1219 | uint64_t rsl_int:1; | |
1220 | uint64_t ill_rrd:1; | |
1221 | uint64_t ill_rwr:1; | |
1222 | uint64_t dperr:1; | |
1223 | uint64_t aperr:1; | |
1224 | uint64_t serr:1; | |
1225 | uint64_t tsr_abt:1; | |
1226 | uint64_t msc_msg:1; | |
1227 | uint64_t msi_mabt:1; | |
1228 | uint64_t msi_tabt:1; | |
1229 | uint64_t msi_per:1; | |
1230 | uint64_t mr_tto:1; | |
1231 | uint64_t mr_abt:1; | |
1232 | uint64_t tr_abt:1; | |
1233 | uint64_t mr_wtto:1; | |
1234 | uint64_t mr_wabt:1; | |
1235 | uint64_t tr_wabt:1; | |
1236 | } cn30xx; | |
1237 | struct cvmx_pci_int_sum_cn31xx { | |
1238 | uint64_t reserved_34_63:30; | |
1239 | uint64_t ill_rd:1; | |
1240 | uint64_t ill_wr:1; | |
1241 | uint64_t win_wr:1; | |
1242 | uint64_t dma1_fi:1; | |
1243 | uint64_t dma0_fi:1; | |
1244 | uint64_t dtime1:1; | |
1245 | uint64_t dtime0:1; | |
1246 | uint64_t dcnt1:1; | |
1247 | uint64_t dcnt0:1; | |
1248 | uint64_t reserved_23_24:2; | |
1249 | uint64_t ptime1:1; | |
1250 | uint64_t ptime0:1; | |
1251 | uint64_t reserved_19_20:2; | |
1252 | uint64_t pcnt1:1; | |
1253 | uint64_t pcnt0:1; | |
1254 | uint64_t rsl_int:1; | |
1255 | uint64_t ill_rrd:1; | |
1256 | uint64_t ill_rwr:1; | |
1257 | uint64_t dperr:1; | |
1258 | uint64_t aperr:1; | |
1259 | uint64_t serr:1; | |
1260 | uint64_t tsr_abt:1; | |
1261 | uint64_t msc_msg:1; | |
1262 | uint64_t msi_mabt:1; | |
1263 | uint64_t msi_tabt:1; | |
1264 | uint64_t msi_per:1; | |
1265 | uint64_t mr_tto:1; | |
1266 | uint64_t mr_abt:1; | |
1267 | uint64_t tr_abt:1; | |
1268 | uint64_t mr_wtto:1; | |
1269 | uint64_t mr_wabt:1; | |
1270 | uint64_t tr_wabt:1; | |
1271 | } cn31xx; | |
1272 | struct cvmx_pci_int_sum_s cn38xx; | |
1273 | struct cvmx_pci_int_sum_s cn38xxp2; | |
1274 | struct cvmx_pci_int_sum_cn31xx cn50xx; | |
1275 | struct cvmx_pci_int_sum_s cn58xx; | |
1276 | struct cvmx_pci_int_sum_s cn58xxp1; | |
1277 | }; | |
1278 | ||
1279 | union cvmx_pci_int_sum2 { | |
1280 | uint64_t u64; | |
1281 | struct cvmx_pci_int_sum2_s { | |
1282 | uint64_t reserved_34_63:30; | |
1283 | uint64_t ill_rd:1; | |
1284 | uint64_t ill_wr:1; | |
1285 | uint64_t win_wr:1; | |
1286 | uint64_t dma1_fi:1; | |
1287 | uint64_t dma0_fi:1; | |
1288 | uint64_t dtime1:1; | |
1289 | uint64_t dtime0:1; | |
1290 | uint64_t dcnt1:1; | |
1291 | uint64_t dcnt0:1; | |
1292 | uint64_t ptime3:1; | |
1293 | uint64_t ptime2:1; | |
1294 | uint64_t ptime1:1; | |
1295 | uint64_t ptime0:1; | |
1296 | uint64_t pcnt3:1; | |
1297 | uint64_t pcnt2:1; | |
1298 | uint64_t pcnt1:1; | |
1299 | uint64_t pcnt0:1; | |
1300 | uint64_t rsl_int:1; | |
1301 | uint64_t ill_rrd:1; | |
1302 | uint64_t ill_rwr:1; | |
1303 | uint64_t dperr:1; | |
1304 | uint64_t aperr:1; | |
1305 | uint64_t serr:1; | |
1306 | uint64_t tsr_abt:1; | |
1307 | uint64_t msc_msg:1; | |
1308 | uint64_t msi_mabt:1; | |
1309 | uint64_t msi_tabt:1; | |
1310 | uint64_t msi_per:1; | |
1311 | uint64_t mr_tto:1; | |
1312 | uint64_t mr_abt:1; | |
1313 | uint64_t tr_abt:1; | |
1314 | uint64_t mr_wtto:1; | |
1315 | uint64_t mr_wabt:1; | |
1316 | uint64_t tr_wabt:1; | |
1317 | } s; | |
1318 | struct cvmx_pci_int_sum2_cn30xx { | |
1319 | uint64_t reserved_34_63:30; | |
1320 | uint64_t ill_rd:1; | |
1321 | uint64_t ill_wr:1; | |
1322 | uint64_t win_wr:1; | |
1323 | uint64_t dma1_fi:1; | |
1324 | uint64_t dma0_fi:1; | |
1325 | uint64_t dtime1:1; | |
1326 | uint64_t dtime0:1; | |
1327 | uint64_t dcnt1:1; | |
1328 | uint64_t dcnt0:1; | |
1329 | uint64_t reserved_22_24:3; | |
1330 | uint64_t ptime0:1; | |
1331 | uint64_t reserved_18_20:3; | |
1332 | uint64_t pcnt0:1; | |
1333 | uint64_t rsl_int:1; | |
1334 | uint64_t ill_rrd:1; | |
1335 | uint64_t ill_rwr:1; | |
1336 | uint64_t dperr:1; | |
1337 | uint64_t aperr:1; | |
1338 | uint64_t serr:1; | |
1339 | uint64_t tsr_abt:1; | |
1340 | uint64_t msc_msg:1; | |
1341 | uint64_t msi_mabt:1; | |
1342 | uint64_t msi_tabt:1; | |
1343 | uint64_t msi_per:1; | |
1344 | uint64_t mr_tto:1; | |
1345 | uint64_t mr_abt:1; | |
1346 | uint64_t tr_abt:1; | |
1347 | uint64_t mr_wtto:1; | |
1348 | uint64_t mr_wabt:1; | |
1349 | uint64_t tr_wabt:1; | |
1350 | } cn30xx; | |
1351 | struct cvmx_pci_int_sum2_cn31xx { | |
1352 | uint64_t reserved_34_63:30; | |
1353 | uint64_t ill_rd:1; | |
1354 | uint64_t ill_wr:1; | |
1355 | uint64_t win_wr:1; | |
1356 | uint64_t dma1_fi:1; | |
1357 | uint64_t dma0_fi:1; | |
1358 | uint64_t dtime1:1; | |
1359 | uint64_t dtime0:1; | |
1360 | uint64_t dcnt1:1; | |
1361 | uint64_t dcnt0:1; | |
1362 | uint64_t reserved_23_24:2; | |
1363 | uint64_t ptime1:1; | |
1364 | uint64_t ptime0:1; | |
1365 | uint64_t reserved_19_20:2; | |
1366 | uint64_t pcnt1:1; | |
1367 | uint64_t pcnt0:1; | |
1368 | uint64_t rsl_int:1; | |
1369 | uint64_t ill_rrd:1; | |
1370 | uint64_t ill_rwr:1; | |
1371 | uint64_t dperr:1; | |
1372 | uint64_t aperr:1; | |
1373 | uint64_t serr:1; | |
1374 | uint64_t tsr_abt:1; | |
1375 | uint64_t msc_msg:1; | |
1376 | uint64_t msi_mabt:1; | |
1377 | uint64_t msi_tabt:1; | |
1378 | uint64_t msi_per:1; | |
1379 | uint64_t mr_tto:1; | |
1380 | uint64_t mr_abt:1; | |
1381 | uint64_t tr_abt:1; | |
1382 | uint64_t mr_wtto:1; | |
1383 | uint64_t mr_wabt:1; | |
1384 | uint64_t tr_wabt:1; | |
1385 | } cn31xx; | |
1386 | struct cvmx_pci_int_sum2_s cn38xx; | |
1387 | struct cvmx_pci_int_sum2_s cn38xxp2; | |
1388 | struct cvmx_pci_int_sum2_cn31xx cn50xx; | |
1389 | struct cvmx_pci_int_sum2_s cn58xx; | |
1390 | struct cvmx_pci_int_sum2_s cn58xxp1; | |
1391 | }; | |
1392 | ||
1393 | union cvmx_pci_msi_rcv { | |
1394 | uint32_t u32; | |
1395 | struct cvmx_pci_msi_rcv_s { | |
1396 | uint32_t reserved_6_31:26; | |
1397 | uint32_t intr:6; | |
1398 | } s; | |
1399 | struct cvmx_pci_msi_rcv_s cn30xx; | |
1400 | struct cvmx_pci_msi_rcv_s cn31xx; | |
1401 | struct cvmx_pci_msi_rcv_s cn38xx; | |
1402 | struct cvmx_pci_msi_rcv_s cn38xxp2; | |
1403 | struct cvmx_pci_msi_rcv_s cn50xx; | |
1404 | struct cvmx_pci_msi_rcv_s cn58xx; | |
1405 | struct cvmx_pci_msi_rcv_s cn58xxp1; | |
1406 | }; | |
1407 | ||
1408 | union cvmx_pci_pkt_creditsx { | |
1409 | uint32_t u32; | |
1410 | struct cvmx_pci_pkt_creditsx_s { | |
1411 | uint32_t pkt_cnt:16; | |
1412 | uint32_t ptr_cnt:16; | |
1413 | } s; | |
1414 | struct cvmx_pci_pkt_creditsx_s cn30xx; | |
1415 | struct cvmx_pci_pkt_creditsx_s cn31xx; | |
1416 | struct cvmx_pci_pkt_creditsx_s cn38xx; | |
1417 | struct cvmx_pci_pkt_creditsx_s cn38xxp2; | |
1418 | struct cvmx_pci_pkt_creditsx_s cn50xx; | |
1419 | struct cvmx_pci_pkt_creditsx_s cn58xx; | |
1420 | struct cvmx_pci_pkt_creditsx_s cn58xxp1; | |
1421 | }; | |
1422 | ||
1423 | union cvmx_pci_pkts_sentx { | |
1424 | uint32_t u32; | |
1425 | struct cvmx_pci_pkts_sentx_s { | |
1426 | uint32_t pkt_cnt:32; | |
1427 | } s; | |
1428 | struct cvmx_pci_pkts_sentx_s cn30xx; | |
1429 | struct cvmx_pci_pkts_sentx_s cn31xx; | |
1430 | struct cvmx_pci_pkts_sentx_s cn38xx; | |
1431 | struct cvmx_pci_pkts_sentx_s cn38xxp2; | |
1432 | struct cvmx_pci_pkts_sentx_s cn50xx; | |
1433 | struct cvmx_pci_pkts_sentx_s cn58xx; | |
1434 | struct cvmx_pci_pkts_sentx_s cn58xxp1; | |
1435 | }; | |
1436 | ||
1437 | union cvmx_pci_pkts_sent_int_levx { | |
1438 | uint32_t u32; | |
1439 | struct cvmx_pci_pkts_sent_int_levx_s { | |
1440 | uint32_t pkt_cnt:32; | |
1441 | } s; | |
1442 | struct cvmx_pci_pkts_sent_int_levx_s cn30xx; | |
1443 | struct cvmx_pci_pkts_sent_int_levx_s cn31xx; | |
1444 | struct cvmx_pci_pkts_sent_int_levx_s cn38xx; | |
1445 | struct cvmx_pci_pkts_sent_int_levx_s cn38xxp2; | |
1446 | struct cvmx_pci_pkts_sent_int_levx_s cn50xx; | |
1447 | struct cvmx_pci_pkts_sent_int_levx_s cn58xx; | |
1448 | struct cvmx_pci_pkts_sent_int_levx_s cn58xxp1; | |
1449 | }; | |
1450 | ||
1451 | union cvmx_pci_pkts_sent_timex { | |
1452 | uint32_t u32; | |
1453 | struct cvmx_pci_pkts_sent_timex_s { | |
1454 | uint32_t pkt_time:32; | |
1455 | } s; | |
1456 | struct cvmx_pci_pkts_sent_timex_s cn30xx; | |
1457 | struct cvmx_pci_pkts_sent_timex_s cn31xx; | |
1458 | struct cvmx_pci_pkts_sent_timex_s cn38xx; | |
1459 | struct cvmx_pci_pkts_sent_timex_s cn38xxp2; | |
1460 | struct cvmx_pci_pkts_sent_timex_s cn50xx; | |
1461 | struct cvmx_pci_pkts_sent_timex_s cn58xx; | |
1462 | struct cvmx_pci_pkts_sent_timex_s cn58xxp1; | |
1463 | }; | |
1464 | ||
1465 | union cvmx_pci_read_cmd_6 { | |
1466 | uint32_t u32; | |
1467 | struct cvmx_pci_read_cmd_6_s { | |
1468 | uint32_t reserved_9_31:23; | |
1469 | uint32_t min_data:6; | |
1470 | uint32_t prefetch:3; | |
1471 | } s; | |
1472 | struct cvmx_pci_read_cmd_6_s cn30xx; | |
1473 | struct cvmx_pci_read_cmd_6_s cn31xx; | |
1474 | struct cvmx_pci_read_cmd_6_s cn38xx; | |
1475 | struct cvmx_pci_read_cmd_6_s cn38xxp2; | |
1476 | struct cvmx_pci_read_cmd_6_s cn50xx; | |
1477 | struct cvmx_pci_read_cmd_6_s cn58xx; | |
1478 | struct cvmx_pci_read_cmd_6_s cn58xxp1; | |
1479 | }; | |
1480 | ||
1481 | union cvmx_pci_read_cmd_c { | |
1482 | uint32_t u32; | |
1483 | struct cvmx_pci_read_cmd_c_s { | |
1484 | uint32_t reserved_9_31:23; | |
1485 | uint32_t min_data:6; | |
1486 | uint32_t prefetch:3; | |
1487 | } s; | |
1488 | struct cvmx_pci_read_cmd_c_s cn30xx; | |
1489 | struct cvmx_pci_read_cmd_c_s cn31xx; | |
1490 | struct cvmx_pci_read_cmd_c_s cn38xx; | |
1491 | struct cvmx_pci_read_cmd_c_s cn38xxp2; | |
1492 | struct cvmx_pci_read_cmd_c_s cn50xx; | |
1493 | struct cvmx_pci_read_cmd_c_s cn58xx; | |
1494 | struct cvmx_pci_read_cmd_c_s cn58xxp1; | |
1495 | }; | |
1496 | ||
1497 | union cvmx_pci_read_cmd_e { | |
1498 | uint32_t u32; | |
1499 | struct cvmx_pci_read_cmd_e_s { | |
1500 | uint32_t reserved_9_31:23; | |
1501 | uint32_t min_data:6; | |
1502 | uint32_t prefetch:3; | |
1503 | } s; | |
1504 | struct cvmx_pci_read_cmd_e_s cn30xx; | |
1505 | struct cvmx_pci_read_cmd_e_s cn31xx; | |
1506 | struct cvmx_pci_read_cmd_e_s cn38xx; | |
1507 | struct cvmx_pci_read_cmd_e_s cn38xxp2; | |
1508 | struct cvmx_pci_read_cmd_e_s cn50xx; | |
1509 | struct cvmx_pci_read_cmd_e_s cn58xx; | |
1510 | struct cvmx_pci_read_cmd_e_s cn58xxp1; | |
1511 | }; | |
1512 | ||
1513 | union cvmx_pci_read_timeout { | |
1514 | uint64_t u64; | |
1515 | struct cvmx_pci_read_timeout_s { | |
1516 | uint64_t reserved_32_63:32; | |
1517 | uint64_t enb:1; | |
1518 | uint64_t cnt:31; | |
1519 | } s; | |
1520 | struct cvmx_pci_read_timeout_s cn30xx; | |
1521 | struct cvmx_pci_read_timeout_s cn31xx; | |
1522 | struct cvmx_pci_read_timeout_s cn38xx; | |
1523 | struct cvmx_pci_read_timeout_s cn38xxp2; | |
1524 | struct cvmx_pci_read_timeout_s cn50xx; | |
1525 | struct cvmx_pci_read_timeout_s cn58xx; | |
1526 | struct cvmx_pci_read_timeout_s cn58xxp1; | |
1527 | }; | |
1528 | ||
1529 | union cvmx_pci_scm_reg { | |
1530 | uint64_t u64; | |
1531 | struct cvmx_pci_scm_reg_s { | |
1532 | uint64_t reserved_32_63:32; | |
1533 | uint64_t scm:32; | |
1534 | } s; | |
1535 | struct cvmx_pci_scm_reg_s cn30xx; | |
1536 | struct cvmx_pci_scm_reg_s cn31xx; | |
1537 | struct cvmx_pci_scm_reg_s cn38xx; | |
1538 | struct cvmx_pci_scm_reg_s cn38xxp2; | |
1539 | struct cvmx_pci_scm_reg_s cn50xx; | |
1540 | struct cvmx_pci_scm_reg_s cn58xx; | |
1541 | struct cvmx_pci_scm_reg_s cn58xxp1; | |
1542 | }; | |
1543 | ||
1544 | union cvmx_pci_tsr_reg { | |
1545 | uint64_t u64; | |
1546 | struct cvmx_pci_tsr_reg_s { | |
1547 | uint64_t reserved_36_63:28; | |
1548 | uint64_t tsr:36; | |
1549 | } s; | |
1550 | struct cvmx_pci_tsr_reg_s cn30xx; | |
1551 | struct cvmx_pci_tsr_reg_s cn31xx; | |
1552 | struct cvmx_pci_tsr_reg_s cn38xx; | |
1553 | struct cvmx_pci_tsr_reg_s cn38xxp2; | |
1554 | struct cvmx_pci_tsr_reg_s cn50xx; | |
1555 | struct cvmx_pci_tsr_reg_s cn58xx; | |
1556 | struct cvmx_pci_tsr_reg_s cn58xxp1; | |
1557 | }; | |
1558 | ||
1559 | union cvmx_pci_win_rd_addr { | |
1560 | uint64_t u64; | |
1561 | struct cvmx_pci_win_rd_addr_s { | |
1562 | uint64_t reserved_49_63:15; | |
1563 | uint64_t iobit:1; | |
1564 | uint64_t reserved_0_47:48; | |
1565 | } s; | |
1566 | struct cvmx_pci_win_rd_addr_cn30xx { | |
1567 | uint64_t reserved_49_63:15; | |
1568 | uint64_t iobit:1; | |
1569 | uint64_t rd_addr:46; | |
1570 | uint64_t reserved_0_1:2; | |
1571 | } cn30xx; | |
1572 | struct cvmx_pci_win_rd_addr_cn30xx cn31xx; | |
1573 | struct cvmx_pci_win_rd_addr_cn38xx { | |
1574 | uint64_t reserved_49_63:15; | |
1575 | uint64_t iobit:1; | |
1576 | uint64_t rd_addr:45; | |
1577 | uint64_t reserved_0_2:3; | |
1578 | } cn38xx; | |
1579 | struct cvmx_pci_win_rd_addr_cn38xx cn38xxp2; | |
1580 | struct cvmx_pci_win_rd_addr_cn30xx cn50xx; | |
1581 | struct cvmx_pci_win_rd_addr_cn38xx cn58xx; | |
1582 | struct cvmx_pci_win_rd_addr_cn38xx cn58xxp1; | |
1583 | }; | |
1584 | ||
1585 | union cvmx_pci_win_rd_data { | |
1586 | uint64_t u64; | |
1587 | struct cvmx_pci_win_rd_data_s { | |
1588 | uint64_t rd_data:64; | |
1589 | } s; | |
1590 | struct cvmx_pci_win_rd_data_s cn30xx; | |
1591 | struct cvmx_pci_win_rd_data_s cn31xx; | |
1592 | struct cvmx_pci_win_rd_data_s cn38xx; | |
1593 | struct cvmx_pci_win_rd_data_s cn38xxp2; | |
1594 | struct cvmx_pci_win_rd_data_s cn50xx; | |
1595 | struct cvmx_pci_win_rd_data_s cn58xx; | |
1596 | struct cvmx_pci_win_rd_data_s cn58xxp1; | |
1597 | }; | |
1598 | ||
1599 | union cvmx_pci_win_wr_addr { | |
1600 | uint64_t u64; | |
1601 | struct cvmx_pci_win_wr_addr_s { | |
1602 | uint64_t reserved_49_63:15; | |
1603 | uint64_t iobit:1; | |
1604 | uint64_t wr_addr:45; | |
1605 | uint64_t reserved_0_2:3; | |
1606 | } s; | |
1607 | struct cvmx_pci_win_wr_addr_s cn30xx; | |
1608 | struct cvmx_pci_win_wr_addr_s cn31xx; | |
1609 | struct cvmx_pci_win_wr_addr_s cn38xx; | |
1610 | struct cvmx_pci_win_wr_addr_s cn38xxp2; | |
1611 | struct cvmx_pci_win_wr_addr_s cn50xx; | |
1612 | struct cvmx_pci_win_wr_addr_s cn58xx; | |
1613 | struct cvmx_pci_win_wr_addr_s cn58xxp1; | |
1614 | }; | |
1615 | ||
1616 | union cvmx_pci_win_wr_data { | |
1617 | uint64_t u64; | |
1618 | struct cvmx_pci_win_wr_data_s { | |
1619 | uint64_t wr_data:64; | |
1620 | } s; | |
1621 | struct cvmx_pci_win_wr_data_s cn30xx; | |
1622 | struct cvmx_pci_win_wr_data_s cn31xx; | |
1623 | struct cvmx_pci_win_wr_data_s cn38xx; | |
1624 | struct cvmx_pci_win_wr_data_s cn38xxp2; | |
1625 | struct cvmx_pci_win_wr_data_s cn50xx; | |
1626 | struct cvmx_pci_win_wr_data_s cn58xx; | |
1627 | struct cvmx_pci_win_wr_data_s cn58xxp1; | |
1628 | }; | |
1629 | ||
1630 | union cvmx_pci_win_wr_mask { | |
1631 | uint64_t u64; | |
1632 | struct cvmx_pci_win_wr_mask_s { | |
1633 | uint64_t reserved_8_63:56; | |
1634 | uint64_t wr_mask:8; | |
1635 | } s; | |
1636 | struct cvmx_pci_win_wr_mask_s cn30xx; | |
1637 | struct cvmx_pci_win_wr_mask_s cn31xx; | |
1638 | struct cvmx_pci_win_wr_mask_s cn38xx; | |
1639 | struct cvmx_pci_win_wr_mask_s cn38xxp2; | |
1640 | struct cvmx_pci_win_wr_mask_s cn50xx; | |
1641 | struct cvmx_pci_win_wr_mask_s cn58xx; | |
1642 | struct cvmx_pci_win_wr_mask_s cn58xxp1; | |
1643 | }; | |
1644 | ||
1645 | #endif |