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Merge branch 'pm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/suspe...
[net-next-2.6.git] / arch / mips / include / asm / octeon / cvmx-gpio-defs.h
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DD		 1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
aa32a955 7 * Copyright (c) 2003-2010 Cavium Networks
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DD		 8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_GPIO_DEFS_H__
29#define __CVMX_GPIO_DEFS_H__
30
aa32a955
DD		 31#define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8)
32#define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull))
33#define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8)
34#define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8)
35#define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
36#define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull))
37#define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull))
38#define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull))
39#define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull))
40#define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16)
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DD		 41
42union cvmx_gpio_bit_cfgx {
43 uint64_t u64;
44 struct cvmx_gpio_bit_cfgx_s {
aa32a955
DD		 45 uint64_t reserved_17_63:47;
46 uint64_t synce_sel:2;
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DD		 47 uint64_t clk_gen:1;
48 uint64_t clk_sel:2;
49 uint64_t fil_sel:4;
50 uint64_t fil_cnt:4;
51 uint64_t int_type:1;
52 uint64_t int_en:1;
53 uint64_t rx_xor:1;
54 uint64_t tx_oe:1;
55 } s;
56 struct cvmx_gpio_bit_cfgx_cn30xx {
57 uint64_t reserved_12_63:52;
58 uint64_t fil_sel:4;
59 uint64_t fil_cnt:4;
60 uint64_t int_type:1;
61 uint64_t int_en:1;
62 uint64_t rx_xor:1;
63 uint64_t tx_oe:1;
64 } cn30xx;
65 struct cvmx_gpio_bit_cfgx_cn30xx cn31xx;
66 struct cvmx_gpio_bit_cfgx_cn30xx cn38xx;
67 struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2;
68 struct cvmx_gpio_bit_cfgx_cn30xx cn50xx;
aa32a955
DD		 69 struct cvmx_gpio_bit_cfgx_cn52xx {
70 uint64_t reserved_15_63:49;
71 uint64_t clk_gen:1;
72 uint64_t clk_sel:2;
73 uint64_t fil_sel:4;
74 uint64_t fil_cnt:4;
75 uint64_t int_type:1;
76 uint64_t int_en:1;
77 uint64_t rx_xor:1;
78 uint64_t tx_oe:1;
79 } cn52xx;
80 struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1;
81 struct cvmx_gpio_bit_cfgx_cn52xx cn56xx;
82 struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1;
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DD		 83 struct cvmx_gpio_bit_cfgx_cn30xx cn58xx;
84 struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1;
aa32a955
DD		 85 struct cvmx_gpio_bit_cfgx_s cn63xx;
86 struct cvmx_gpio_bit_cfgx_s cn63xxp1;
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DD		 87};
88
89union cvmx_gpio_boot_ena {
90 uint64_t u64;
91 struct cvmx_gpio_boot_ena_s {
92 uint64_t reserved_12_63:52;
93 uint64_t boot_ena:4;
94 uint64_t reserved_0_7:8;
95 } s;
96 struct cvmx_gpio_boot_ena_s cn30xx;
97 struct cvmx_gpio_boot_ena_s cn31xx;
98 struct cvmx_gpio_boot_ena_s cn50xx;
99};
100
101union cvmx_gpio_clk_genx {
102 uint64_t u64;
103 struct cvmx_gpio_clk_genx_s {
104 uint64_t reserved_32_63:32;
105 uint64_t n:32;
106 } s;
107 struct cvmx_gpio_clk_genx_s cn52xx;
108 struct cvmx_gpio_clk_genx_s cn52xxp1;
109 struct cvmx_gpio_clk_genx_s cn56xx;
110 struct cvmx_gpio_clk_genx_s cn56xxp1;
aa32a955
DD		 111 struct cvmx_gpio_clk_genx_s cn63xx;
112 struct cvmx_gpio_clk_genx_s cn63xxp1;
113};
114
115union cvmx_gpio_clk_qlmx {
116 uint64_t u64;
117 struct cvmx_gpio_clk_qlmx_s {
118 uint64_t reserved_3_63:61;
119 uint64_t div:1;
120 uint64_t lane_sel:2;
121 } s;
122 struct cvmx_gpio_clk_qlmx_s cn63xx;
123 struct cvmx_gpio_clk_qlmx_s cn63xxp1;
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DD		 124};
125
126union cvmx_gpio_dbg_ena {
127 uint64_t u64;
128 struct cvmx_gpio_dbg_ena_s {
129 uint64_t reserved_21_63:43;
130 uint64_t dbg_ena:21;
131 } s;
132 struct cvmx_gpio_dbg_ena_s cn30xx;
133 struct cvmx_gpio_dbg_ena_s cn31xx;
134 struct cvmx_gpio_dbg_ena_s cn50xx;
135};
136
137union cvmx_gpio_int_clr {
138 uint64_t u64;
139 struct cvmx_gpio_int_clr_s {
140 uint64_t reserved_16_63:48;
141 uint64_t type:16;
142 } s;
143 struct cvmx_gpio_int_clr_s cn30xx;
144 struct cvmx_gpio_int_clr_s cn31xx;
145 struct cvmx_gpio_int_clr_s cn38xx;
146 struct cvmx_gpio_int_clr_s cn38xxp2;
147 struct cvmx_gpio_int_clr_s cn50xx;
148 struct cvmx_gpio_int_clr_s cn52xx;
149 struct cvmx_gpio_int_clr_s cn52xxp1;
150 struct cvmx_gpio_int_clr_s cn56xx;
151 struct cvmx_gpio_int_clr_s cn56xxp1;
152 struct cvmx_gpio_int_clr_s cn58xx;
153 struct cvmx_gpio_int_clr_s cn58xxp1;
aa32a955
DD		 154 struct cvmx_gpio_int_clr_s cn63xx;
155 struct cvmx_gpio_int_clr_s cn63xxp1;
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DD		 156};
157
158union cvmx_gpio_rx_dat {
159 uint64_t u64;
160 struct cvmx_gpio_rx_dat_s {
161 uint64_t reserved_24_63:40;
162 uint64_t dat:24;
163 } s;
164 struct cvmx_gpio_rx_dat_s cn30xx;
165 struct cvmx_gpio_rx_dat_s cn31xx;
166 struct cvmx_gpio_rx_dat_cn38xx {
167 uint64_t reserved_16_63:48;
168 uint64_t dat:16;
169 } cn38xx;
170 struct cvmx_gpio_rx_dat_cn38xx cn38xxp2;
171 struct cvmx_gpio_rx_dat_s cn50xx;
172 struct cvmx_gpio_rx_dat_cn38xx cn52xx;
173 struct cvmx_gpio_rx_dat_cn38xx cn52xxp1;
174 struct cvmx_gpio_rx_dat_cn38xx cn56xx;
175 struct cvmx_gpio_rx_dat_cn38xx cn56xxp1;
176 struct cvmx_gpio_rx_dat_cn38xx cn58xx;
177 struct cvmx_gpio_rx_dat_cn38xx cn58xxp1;
aa32a955
DD		 178 struct cvmx_gpio_rx_dat_cn38xx cn63xx;
179 struct cvmx_gpio_rx_dat_cn38xx cn63xxp1;
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DD		 180};
181
182union cvmx_gpio_tx_clr {
183 uint64_t u64;
184 struct cvmx_gpio_tx_clr_s {
185 uint64_t reserved_24_63:40;
186 uint64_t clr:24;
187 } s;
188 struct cvmx_gpio_tx_clr_s cn30xx;
189 struct cvmx_gpio_tx_clr_s cn31xx;
190 struct cvmx_gpio_tx_clr_cn38xx {
191 uint64_t reserved_16_63:48;
192 uint64_t clr:16;
193 } cn38xx;
194 struct cvmx_gpio_tx_clr_cn38xx cn38xxp2;
195 struct cvmx_gpio_tx_clr_s cn50xx;
196 struct cvmx_gpio_tx_clr_cn38xx cn52xx;
197 struct cvmx_gpio_tx_clr_cn38xx cn52xxp1;
198 struct cvmx_gpio_tx_clr_cn38xx cn56xx;
199 struct cvmx_gpio_tx_clr_cn38xx cn56xxp1;
200 struct cvmx_gpio_tx_clr_cn38xx cn58xx;
201 struct cvmx_gpio_tx_clr_cn38xx cn58xxp1;
aa32a955
DD		 202 struct cvmx_gpio_tx_clr_cn38xx cn63xx;
203 struct cvmx_gpio_tx_clr_cn38xx cn63xxp1;
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DD		 204};
205
206union cvmx_gpio_tx_set {
207 uint64_t u64;
208 struct cvmx_gpio_tx_set_s {
209 uint64_t reserved_24_63:40;
210 uint64_t set:24;
211 } s;
212 struct cvmx_gpio_tx_set_s cn30xx;
213 struct cvmx_gpio_tx_set_s cn31xx;
214 struct cvmx_gpio_tx_set_cn38xx {
215 uint64_t reserved_16_63:48;
216 uint64_t set:16;
217 } cn38xx;
218 struct cvmx_gpio_tx_set_cn38xx cn38xxp2;
219 struct cvmx_gpio_tx_set_s cn50xx;
220 struct cvmx_gpio_tx_set_cn38xx cn52xx;
221 struct cvmx_gpio_tx_set_cn38xx cn52xxp1;
222 struct cvmx_gpio_tx_set_cn38xx cn56xx;
223 struct cvmx_gpio_tx_set_cn38xx cn56xxp1;
224 struct cvmx_gpio_tx_set_cn38xx cn58xx;
225 struct cvmx_gpio_tx_set_cn38xx cn58xxp1;
aa32a955
DD		 226 struct cvmx_gpio_tx_set_cn38xx cn63xx;
227 struct cvmx_gpio_tx_set_cn38xx cn63xxp1;
54293ec3
DD		 228};
229
230union cvmx_gpio_xbit_cfgx {
231 uint64_t u64;
232 struct cvmx_gpio_xbit_cfgx_s {
233 uint64_t reserved_12_63:52;
234 uint64_t fil_sel:4;
235 uint64_t fil_cnt:4;
236 uint64_t reserved_2_3:2;
237 uint64_t rx_xor:1;
238 uint64_t tx_oe:1;
239 } s;
240 struct cvmx_gpio_xbit_cfgx_s cn30xx;
241 struct cvmx_gpio_xbit_cfgx_s cn31xx;
242 struct cvmx_gpio_xbit_cfgx_s cn50xx;
243};
244
245#endif
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