[net-next-2.6.git] / arch / mips / include / asm / mach-pb1x00 / pb1550.h

/*
 * AMD Alchemy Semi PB1550 Referrence Board
 * Board Registers defines.
 *
 * Copyright 2004 Embedded Edge LLC.
 * Copyright 2005 Ralf Baechle (ralf@linux-mips.org)
 *
 * ########################################################################
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * ########################################################################
 *
 *
 */
#ifndef __ASM_PB1550_H
#define __ASM_PB1550_H

#include <linux/types.h>
#include <asm/mach-au1x00/au1xxx_psc.h>

#define DBDMA_AC97_TX_CHAN	DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN	DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN	DSCR_CMD0_PSC3_TX
#define DBDMA_I2S_RX_CHAN	DSCR_CMD0_PSC3_RX

#define SPI_PSC_BASE		PSC0_BASE_ADDR
#define AC97_PSC_BASE		PSC1_BASE_ADDR
#define SMBUS_PSC_BASE		PSC2_BASE_ADDR
#define I2S_PSC_BASE		PSC3_BASE_ADDR

#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
#define PB1550_BOTH_BANKS
#elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER)
#define PB1550_BOOT_ONLY
#elif !defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
#define PB1550_USER_ONLY
#endif

/*
 * Timing values as described in databook, * ns value stripped of
 * lower 2 bits.
 * These defines are here rather than an SOC1550 generic file because
 * the parts chosen on another board may be different and may require
 * different timings.
 */
#define NAND_T_H		(18 >> 2)
#define NAND_T_PUL		(30 >> 2)
#define NAND_T_SU		(30 >> 2)
#define NAND_T_WH		(30 >> 2)

/* Bitfield shift amounts */
#define NAND_T_H_SHIFT		0
#define NAND_T_PUL_SHIFT	4
#define NAND_T_SU_SHIFT		8
#define NAND_T_WH_SHIFT		12

#define NAND_TIMING	(((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
			 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
			 ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
			 ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))

#define NAND_CS 1

/* Should be done by YAMON */
#define NAND_STCFG	0x00400005 /* 8-bit NAND */
#define NAND_STTIME	0x00007774 /* valid for 396 MHz SD=2 only */
#define NAND_STADDR	0x12000FFF /* physical address 0x20000000 */

#endif /* __ASM_PB1550_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* AMD Alchemy Semi PB1550 Referrence Board
	3	* Board Registers defines.
	4	*
	5	* Copyright 2004 Embedded Edge LLC.
	6	* Copyright 2005 Ralf Baechle (ralf@linux-mips.org)
	7	*
	8	* ########################################################################
	9	*
	10	* This program is free software; you can distribute it and/or modify it
	11	* under the terms of the GNU General Public License (Version 2) as
	12	* published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope it will be useful, but WITHOUT
	15	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	17	* for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License along
	20	* with this program; if not, write to the Free Software Foundation, Inc.,
	21	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	22	*
	23	* ########################################################################
	24	*
	25	*
	26	*/
	27	#ifndef __ASM_PB1550_H
	28	#define __ASM_PB1550_H
	29
1da177e4	30	#include <linux/types.h>
9e39ffef	31	#include <asm/mach-au1x00/au1xxx_psc.h>
1da177e4	32
6afabe6c SS	33	#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
	34	#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
	35	#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
	36	#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
1da177e4	37
6afabe6c SS	38	#define SPI_PSC_BASE PSC0_BASE_ADDR
	39	#define AC97_PSC_BASE PSC1_BASE_ADDR
	40	#define SMBUS_PSC_BASE PSC2_BASE_ADDR
	41	#define I2S_PSC_BASE PSC3_BASE_ADDR
1da177e4	42
1da177e4 LT	43	#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
	44	#define PB1550_BOTH_BANKS
	45	#elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER)
	46	#define PB1550_BOOT_ONLY
	47	#elif !defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
	48	#define PB1550_USER_ONLY
	49	#endif
	50
6afabe6c SS	51	/*
6afabe6c SS	52	* Timing values as described in databook, * ns value stripped of
1da177e4 LT	53	* lower 2 bits.
	54	* These defines are here rather than an SOC1550 generic file because
	55	* the parts chosen on another board may be different and may require
	56	* different timings.
	57	*/
6afabe6c SS	58	#define NAND_T_H (18 >> 2)
	59	#define NAND_T_PUL (30 >> 2)
	60	#define NAND_T_SU (30 >> 2)
	61	#define NAND_T_WH (30 >> 2)
1da177e4 LT	62
	63	/* Bitfield shift amounts */
	64	#define NAND_T_H_SHIFT 0
	65	#define NAND_T_PUL_SHIFT 4
	66	#define NAND_T_SU_SHIFT 8
	67	#define NAND_T_WH_SHIFT 12
	68
6afabe6c SS	69	#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) \| \
	70	((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) \| \
	71	((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) \| \
	72	((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
1da177e4	73
bdc3c3c7 RB	74	#define NAND_CS 1
bdc3c3c7 RB	75
6afabe6c SS	76	/* Should be done by YAMON */
	77	#define NAND_STCFG 0x00400005 /* 8-bit NAND */
	78	#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
	79	#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
bdc3c3c7	80
1da177e4	81	#endif /* __ASM_PB1550_H */