[net-next-2.6.git] / arch / mips / include / asm / mach-db1x00 / db1200.h

/*
 * AMD Alchemy DBAu1200 Reference Board
 * Board register defines.
 *
 * ########################################################################
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * ########################################################################
 *
 *
 */
#ifndef __ASM_DB1200_H
#define __ASM_DB1200_H

#include <linux/types.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_psc.h>

#define DBDMA_AC97_TX_CHAN	DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN	DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN	DSCR_CMD0_PSC1_TX
#define DBDMA_I2S_RX_CHAN	DSCR_CMD0_PSC1_RX

/*
 * SPI and SMB are muxed on the DBAu1200 board.
 * Refer to board documentation.
 */
#define SPI_PSC_BASE		PSC0_BASE_ADDR
#define SMBUS_PSC_BASE		PSC0_BASE_ADDR
/*
 * AC'97 and I2S are muxed on the DBAu1200 board.
 * Refer to board documentation.
 */
#define AC97_PSC_BASE		PSC1_BASE_ADDR
#define I2S_PSC_BASE		PSC1_BASE_ADDR

/* Bit positions for the different interrupt sources */
#define BCSR_INT_IDE		0x0001
#define BCSR_INT_ETH		0x0002
#define BCSR_INT_PC0		0x0004
#define BCSR_INT_PC0STSCHG	0x0008
#define BCSR_INT_PC1		0x0010
#define BCSR_INT_PC1STSCHG	0x0020
#define BCSR_INT_DC		0x0040
#define BCSR_INT_FLASHBUSY	0x0080
#define BCSR_INT_PC0INSERT	0x0100
#define BCSR_INT_PC0EJECT	0x0200
#define BCSR_INT_PC1INSERT	0x0400
#define BCSR_INT_PC1EJECT	0x0800
#define BCSR_INT_SD0INSERT	0x1000
#define BCSR_INT_SD0EJECT	0x2000

#define SMC91C111_PHYS_ADDR	0x19000300
#define SMC91C111_INT		DB1200_ETH_INT

#define IDE_PHYS_ADDR		0x18800000
#define IDE_REG_SHIFT		5
#define IDE_PHYS_LEN		(16 << IDE_REG_SHIFT)
#define IDE_INT 		DB1200_IDE_INT
#define IDE_DDMA_REQ		DSCR_CMD0_DMA_REQ1
#define IDE_RQSIZE		128

#define NAND_PHYS_ADDR		0x20000000

/*
 * External Interrupts for DBAu1200 as of 8/6/2004.
 * Bit positions in the CPLD registers can be calculated by taking
 * the interrupt define and subtracting the DB1200_INT_BEGIN value.
 *
 *   Example: IDE bis pos is  = 64 - 64
 *            ETH bit pos is  = 65 - 64
 */
enum external_pb1200_ints {
	DB1200_INT_BEGIN	= AU1000_MAX_INTR + 1,

	DB1200_IDE_INT		= DB1200_INT_BEGIN,
	DB1200_ETH_INT,
	DB1200_PC0_INT,
	DB1200_PC0_STSCHG_INT,
	DB1200_PC1_INT,
	DB1200_PC1_STSCHG_INT,
	DB1200_DC_INT,
	DB1200_FLASHBUSY_INT,
	DB1200_PC0_INSERT_INT,
	DB1200_PC0_EJECT_INT,
	DB1200_PC1_INSERT_INT,
	DB1200_PC1_EJECT_INT,
	DB1200_SD0_INSERT_INT,
	DB1200_SD0_EJECT_INT,

	DB1200_INT_END		= DB1200_INT_BEGIN + 15,
};


/*
 * DBAu1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
 */
#define PCMCIA_MAX_SOCK  1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)

/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP, SLOT) \
	((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))

#define BOARD_PC0_INT	DB1200_PC0_INT
#define BOARD_PC1_INT	DB1200_PC1_INT
#define BOARD_CARD_INSERTED(SOCKET) (bcsr_read(BCSR_SIGSTAT) & (1 << (8 + (2 * SOCKET))))

/* NAND chip select */
#define NAND_CS 1

#endif /* __ASM_DB1200_H */
Commit	Line	Data
e3ad1c23	1	/*
c3d1d5c8 SS	2	* AMD Alchemy DBAu1200 Reference Board
c3d1d5c8 SS	3	* Board register defines.
e3ad1c23 PP	4	*
	5	* ########################################################################
	6	*
	7	* This program is free software; you can distribute it and/or modify it
	8	* under the terms of the GNU General Public License (Version 2) as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	14	* for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along
	17	* with this program; if not, write to the Free Software Foundation, Inc.,
	18	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	19	*
	20	* ########################################################################
	21	*
	22	*
	23	*/
	24	#ifndef __ASM_DB1200_H
	25	#define __ASM_DB1200_H
	26
	27	#include <linux/types.h>
7e50b2b7	28	#include <asm/mach-au1x00/au1000.h>
9e39ffef	29	#include <asm/mach-au1x00/au1xxx_psc.h>
e3ad1c23	30
c3d1d5c8 SS	31	#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
	32	#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
	33	#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
	34	#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
e3ad1c23	35
c3d1d5c8 SS	36	/*
	37	* SPI and SMB are muxed on the DBAu1200 board.
	38	* Refer to board documentation.
e3ad1c23	39	*/
c3d1d5c8 SS	40	#define SPI_PSC_BASE PSC0_BASE_ADDR
	41	#define SMBUS_PSC_BASE PSC0_BASE_ADDR
	42	/*
	43	* AC'97 and I2S are muxed on the DBAu1200 board.
	44	* Refer to board documentation.
e3ad1c23	45	*/
c3d1d5c8	46	#define AC97_PSC_BASE PSC1_BASE_ADDR
e3ad1c23 PP	47	#define I2S_PSC_BASE PSC1_BASE_ADDR
e3ad1c23 PP	48
e3ad1c23 PP	49	/* Bit positions for the different interrupt sources */
	50	#define BCSR_INT_IDE 0x0001
	51	#define BCSR_INT_ETH 0x0002
	52	#define BCSR_INT_PC0 0x0004
	53	#define BCSR_INT_PC0STSCHG 0x0008
	54	#define BCSR_INT_PC1 0x0010
	55	#define BCSR_INT_PC1STSCHG 0x0020
c3d1d5c8	56	#define BCSR_INT_DC 0x0040
e3ad1c23 PP	57	#define BCSR_INT_FLASHBUSY 0x0080
	58	#define BCSR_INT_PC0INSERT 0x0100
	59	#define BCSR_INT_PC0EJECT 0x0200
	60	#define BCSR_INT_PC1INSERT 0x0400
	61	#define BCSR_INT_PC1EJECT 0x0800
	62	#define BCSR_INT_SD0INSERT 0x1000
	63	#define BCSR_INT_SD0EJECT 0x2000
	64
fcbd3b4b SS	65	#define SMC91C111_PHYS_ADDR 0x19000300
	66	#define SMC91C111_INT DB1200_ETH_INT
	67
	68	#define IDE_PHYS_ADDR 0x18800000
	69	#define IDE_REG_SHIFT 5
	70	#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
	71	#define IDE_INT DB1200_IDE_INT
	72	#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
	73	#define IDE_RQSIZE 128
e3ad1c23	74
c3d1d5c8	75	#define NAND_PHYS_ADDR 0x20000000
e3ad1c23 PP	76
e3ad1c23 PP	77	/*
c3d1d5c8	78	* External Interrupts for DBAu1200 as of 8/6/2004.
9d360ab4 RB	79	* Bit positions in the CPLD registers can be calculated by taking
	80	* the interrupt define and subtracting the DB1200_INT_BEGIN value.
	81	*
	82	* Example: IDE bis pos is = 64 - 64
	83	* ETH bit pos is = 65 - 64
e3ad1c23	84	*/
9d360ab4 RB	85	enum external_pb1200_ints {
	86	DB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
	87
	88	DB1200_IDE_INT = DB1200_INT_BEGIN,
	89	DB1200_ETH_INT,
	90	DB1200_PC0_INT,
	91	DB1200_PC0_STSCHG_INT,
	92	DB1200_PC1_INT,
	93	DB1200_PC1_STSCHG_INT,
	94	DB1200_DC_INT,
	95	DB1200_FLASHBUSY_INT,
	96	DB1200_PC0_INSERT_INT,
	97	DB1200_PC0_EJECT_INT,
	98	DB1200_PC1_INSERT_INT,
	99	DB1200_PC1_EJECT_INT,
	100	DB1200_SD0_INSERT_INT,
	101	DB1200_SD0_EJECT_INT,
	102
	103	DB1200_INT_END = DB1200_INT_BEGIN + 15,
	104	};
	105
e3ad1c23	106
c3d1d5c8 SS	107	/*
	108	* DBAu1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
	109	*/
	110	#define PCMCIA_MAX_SOCK 1
	111	#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
d6460827 PP	112
d6460827 PP	113	/* VPP/VCC */
c3d1d5c8 SS	114	#define SET_VCC_VPP(VCC, VPP, SLOT) \
c3d1d5c8 SS	115	((((VCC) << 2) \| ((VPP) << 0)) << ((SLOT) * 8))
d6460827	116
c3d1d5c8 SS	117	#define BOARD_PC0_INT DB1200_PC0_INT
c3d1d5c8 SS	118	#define BOARD_PC1_INT DB1200_PC1_INT
9bdcf336	119	#define BOARD_CARD_INSERTED(SOCKET) (bcsr_read(BCSR_SIGSTAT) & (1 << (8 + (2 * SOCKET))))
e3ad1c23	120
c3d1d5c8	121	/* NAND chip select */
bdc3c3c7 RB	122	#define NAND_CS 1
bdc3c3c7 RB	123
e3ad1c23	124	#endif /* __ASM_DB1200_H */