[net-next-2.6.git] / arch / mips / cavium-octeon / Kconfig

config CAVIUM_OCTEON_SPECIFIC_OPTIONS
	bool "Enable Octeon specific options"
	depends on CPU_CAVIUM_OCTEON
	default "y"

config CAVIUM_CN63XXP1
	bool "Enable CN63XXP1 errata worarounds"
	depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
	default "n"
	help
	  The CN63XXP1 chip requires build time workarounds to
	  function reliably, select this option to enable them.  These
	  workarounds will cause a slight decrease in performance on
	  non-CN63XXP1 hardware, so it is recommended to select "n"
	  unless it is known the workarounds are needed.

config CAVIUM_OCTEON_2ND_KERNEL
	bool "Build the kernel to be used as a 2nd kernel on the same chip"
	depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
	default "n"
	help
	  This option configures this kernel to be linked at a different
	  address and use the 2nd uart for output. This allows a kernel built
	  with this option to be run at the same time as one built without this
	  option.

config CAVIUM_OCTEON_HW_FIX_UNALIGNED
	bool "Enable hardware fixups of unaligned loads and stores"
	depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
	default "y"
	help
	  Configure the Octeon hardware to automatically fix unaligned loads
	  and stores. Normally unaligned accesses are fixed using a kernel
	  exception handler. This option enables the hardware automatic fixups,
	  which requires only an extra 3 cycles. Disable this option if you
	  are running code that relies on address exceptions on unaligned
	  accesses.

config CAVIUM_OCTEON_CVMSEG_SIZE
	int "Number of L1 cache lines reserved for CVMSEG memory"
	depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
	range 0 54
	default 1
	help
	  CVMSEG LM is a segment that accesses portions of the dcache as a
	  local memory; the larger CVMSEG is, the smaller the cache is.
	  This selects the size of CVMSEG LM, which is in cache blocks. The
	  legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
	  between zero and 6192 bytes).

config CAVIUM_OCTEON_LOCK_L2
	bool "Lock often used kernel code in the L2"
	depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
	default "y"
	help
	  Enable locking parts of the kernel into the L2 cache.

config CAVIUM_OCTEON_LOCK_L2_TLB
	bool "Lock the TLB handler in L2"
	depends on CAVIUM_OCTEON_LOCK_L2
	default "y"
	help
	  Lock the low level TLB fast path into L2.

config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
	bool "Lock the exception handler in L2"
	depends on CAVIUM_OCTEON_LOCK_L2
	default "y"
	help
	  Lock the low level exception handler into L2.

config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
	bool "Lock the interrupt handler in L2"
	depends on CAVIUM_OCTEON_LOCK_L2
	default "y"
	help
	  Lock the low level interrupt handler into L2.

config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
	bool "Lock the 2nd level interrupt handler in L2"
	depends on CAVIUM_OCTEON_LOCK_L2
	default "y"
	help
	  Lock the 2nd level interrupt handler in L2.

config CAVIUM_OCTEON_LOCK_L2_MEMCPY
	bool "Lock memcpy() in L2"
	depends on CAVIUM_OCTEON_LOCK_L2
	default "y"
	help
	  Lock the kernel's implementation of memcpy() into L2.

config ARCH_SPARSEMEM_ENABLE
	def_bool y
	select SPARSEMEM_STATIC
	depends on CPU_CAVIUM_OCTEON

config CAVIUM_OCTEON_HELPER
	def_bool y
	depends on OCTEON_ETHERNET || PCI

config IOMMU_HELPER
	bool

config NEED_SG_DMA_LENGTH
	bool

config SWIOTLB
	def_bool y
	depends on CPU_CAVIUM_OCTEON
	select IOMMU_HELPER
	select NEED_SG_DMA_LENGTH
Commit	Line	Data
5b3b1688 DD	1	config CAVIUM_OCTEON_SPECIFIC_OPTIONS
	2	bool "Enable Octeon specific options"
	3	depends on CPU_CAVIUM_OCTEON
	4	default "y"
	5
c9941158 DD	6	config CAVIUM_CN63XXP1
	7	bool "Enable CN63XXP1 errata worarounds"
	8	depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
	9	default "n"
	10	help
	11	The CN63XXP1 chip requires build time workarounds to
	12	function reliably, select this option to enable them. These
	13	workarounds will cause a slight decrease in performance on
	14	non-CN63XXP1 hardware, so it is recommended to select "n"
	15	unless it is known the workarounds are needed.
	16
5b3b1688 DD	17	config CAVIUM_OCTEON_2ND_KERNEL
	18	bool "Build the kernel to be used as a 2nd kernel on the same chip"
	19	depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
	20	default "n"
	21	help
	22	This option configures this kernel to be linked at a different
	23	address and use the 2nd uart for output. This allows a kernel built
	24	with this option to be run at the same time as one built without this
	25	option.
	26
	27	config CAVIUM_OCTEON_HW_FIX_UNALIGNED
	28	bool "Enable hardware fixups of unaligned loads and stores"
	29	depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
	30	default "y"
	31	help
	32	Configure the Octeon hardware to automatically fix unaligned loads
	33	and stores. Normally unaligned accesses are fixed using a kernel
	34	exception handler. This option enables the hardware automatic fixups,
	35	which requires only an extra 3 cycles. Disable this option if you
	36	are running code that relies on address exceptions on unaligned
	37	accesses.
	38
	39	config CAVIUM_OCTEON_CVMSEG_SIZE
	40	int "Number of L1 cache lines reserved for CVMSEG memory"
	41	depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
	42	range 0 54
	43	default 1
	44	help
	45	CVMSEG LM is a segment that accesses portions of the dcache as a
	46	local memory; the larger CVMSEG is, the smaller the cache is.
	47	This selects the size of CVMSEG LM, which is in cache blocks. The
	48	legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
	49	between zero and 6192 bytes).
	50
	51	config CAVIUM_OCTEON_LOCK_L2
	52	bool "Lock often used kernel code in the L2"
	53	depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
	54	default "y"
	55	help
	56	Enable locking parts of the kernel into the L2 cache.
	57
	58	config CAVIUM_OCTEON_LOCK_L2_TLB
	59	bool "Lock the TLB handler in L2"
	60	depends on CAVIUM_OCTEON_LOCK_L2
	61	default "y"
	62	help
	63	Lock the low level TLB fast path into L2.
	64
	65	config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
	66	bool "Lock the exception handler in L2"
	67	depends on CAVIUM_OCTEON_LOCK_L2
	68	default "y"
	69	help
	70	Lock the low level exception handler into L2.
	71
	72	config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
	73	bool "Lock the interrupt handler in L2"
	74	depends on CAVIUM_OCTEON_LOCK_L2
	75	default "y"
	76	help
	77	Lock the low level interrupt handler into L2.
	78
	79	config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
	80	bool "Lock the 2nd level interrupt handler in L2"
81	depends on CAVIUM_OCTEON_LOCK_L2
82	default "y"
83	help
84	Lock the 2nd level interrupt handler in L2.
85
86	config CAVIUM_OCTEON_LOCK_L2_MEMCPY
87	bool "Lock memcpy() in L2"
88	depends on CAVIUM_OCTEON_LOCK_L2
89	default "y"
90	help
91	Lock the kernel's implementation of memcpy() into L2.
92
93	config ARCH_SPARSEMEM_ENABLE
94	def_bool y
95	select SPARSEMEM_STATIC
96	depends on CPU_CAVIUM_OCTEON
1ec0e739 AB	97
	98	config CAVIUM_OCTEON_HELPER
	99	def_bool y
	100	depends on OCTEON_ETHERNET \|\| PCI
b93b2abc DD	101
	102	config IOMMU_HELPER
	103	bool
	104
	105	config NEED_SG_DMA_LENGTH
	106	bool
	107
	108	config SWIOTLB
	109	def_bool y
	110	depends on CPU_CAVIUM_OCTEON
	111	select IOMMU_HELPER
	112	select NEED_SG_DMA_LENGTH