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1da177e4 | 1 | /* |
2091a17f SS |
2 | * Copyright 2000, 2008 MontaVista Software Inc. |
3 | * Author: MontaVista Software, Inc. <source@mvista.com> | |
1da177e4 LT |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | * | |
10 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
11 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
12 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
13 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
14 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
15 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
16 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
17 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
18 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
19 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License along | |
22 | * with this program; if not, write to the Free Software Foundation, Inc., | |
23 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | */ | |
ce28f94c | 25 | |
1da177e4 | 26 | #include <linux/init.h> |
1da177e4 | 27 | #include <linux/delay.h> |
785e3268 | 28 | #include <linux/interrupt.h> |
1da177e4 | 29 | |
1da177e4 LT |
30 | #include <asm/mach-au1x00/au1000.h> |
31 | #include <asm/mach-pb1x00/pb1500.h> | |
32 | ||
7179380e ML |
33 | #include <prom.h> |
34 | ||
23ba25d5 ML |
35 | |
36 | char irq_tab_alchemy[][5] __initdata = { | |
37 | [12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - HPT370 */ | |
38 | [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */ | |
39 | }; | |
40 | ||
41 | struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { | |
785e3268 ML |
42 | { AU1500_GPIO_204, IRQF_TRIGGER_HIGH, 0 }, |
43 | { AU1500_GPIO_201, IRQF_TRIGGER_LOW, 0 }, | |
44 | { AU1500_GPIO_202, IRQF_TRIGGER_LOW, 0 }, | |
45 | { AU1500_GPIO_203, IRQF_TRIGGER_LOW, 0 }, | |
46 | { AU1500_GPIO_205, IRQF_TRIGGER_LOW, 0 }, | |
23ba25d5 ML |
47 | }; |
48 | ||
23ba25d5 ML |
49 | |
50 | const char *get_system_type(void) | |
51 | { | |
52 | return "Alchemy Pb1500"; | |
53 | } | |
54 | ||
49a89efb | 55 | void board_reset(void) |
1da177e4 | 56 | { |
2091a17f SS |
57 | /* Hit BCSR.RST_VDDI[SOFT_RESET] */ |
58 | au_writel(0x00000000, PB1500_RST_VDDI); | |
1da177e4 LT |
59 | } |
60 | ||
785e3268 ML |
61 | void __init board_init_irq(void) |
62 | { | |
63 | au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map)); | |
64 | } | |
65 | ||
1da177e4 LT |
66 | void __init board_setup(void) |
67 | { | |
68 | u32 pin_func; | |
69 | u32 sys_freqctrl, sys_clksrc; | |
7179380e ML |
70 | char *argptr; |
71 | ||
72 | argptr = prom_getcmdline(); | |
73 | #ifdef CONFIG_SERIAL_8250_CONSOLE | |
74 | argptr = strstr(argptr, "console="); | |
75 | if (argptr == NULL) { | |
76 | argptr = prom_getcmdline(); | |
77 | strcat(argptr, " console=ttyS0,115200"); | |
78 | } | |
79 | #endif | |
80 | ||
81 | #if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000) | |
82 | /* au1000 does not support vra, au1500 and au1100 do */ | |
83 | strcat(argptr, " au1000_audio=vra"); | |
84 | argptr = prom_getcmdline(); | |
85 | #endif | |
1da177e4 LT |
86 | |
87 | sys_clksrc = sys_freqctrl = pin_func = 0; | |
2091a17f | 88 | /* Set AUX clock to 12 MHz * 8 = 96 MHz */ |
1da177e4 LT |
89 | au_writel(8, SYS_AUXPLL); |
90 | au_writel(0, SYS_PINSTATERD); | |
91 | udelay(100); | |
92 | ||
f708631a | 93 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) |
1da177e4 LT |
94 | |
95 | /* GPIO201 is input for PCMCIA card detect */ | |
96 | /* GPIO203 is input for PCMCIA interrupt request */ | |
2091a17f | 97 | au_writel(au_readl(GPIO2_DIR) & ~((1 << 1) | (1 << 3)), GPIO2_DIR); |
1da177e4 | 98 | |
2091a17f | 99 | /* Zero and disable FREQ2 */ |
1da177e4 LT |
100 | sys_freqctrl = au_readl(SYS_FREQCTRL0); |
101 | sys_freqctrl &= ~0xFFF00000; | |
102 | au_writel(sys_freqctrl, SYS_FREQCTRL0); | |
103 | ||
104 | /* zero and disable USBH/USBD clocks */ | |
105 | sys_clksrc = au_readl(SYS_CLKSRC); | |
2091a17f SS |
106 | sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK | |
107 | SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK); | |
1da177e4 LT |
108 | au_writel(sys_clksrc, SYS_CLKSRC); |
109 | ||
110 | sys_freqctrl = au_readl(SYS_FREQCTRL0); | |
111 | sys_freqctrl &= ~0xFFF00000; | |
112 | ||
113 | sys_clksrc = au_readl(SYS_CLKSRC); | |
2091a17f SS |
114 | sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK | |
115 | SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK); | |
1da177e4 | 116 | |
2091a17f SS |
117 | /* FREQ2 = aux/2 = 48 MHz */ |
118 | sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2 | SYS_FC_FS2; | |
1da177e4 LT |
119 | au_writel(sys_freqctrl, SYS_FREQCTRL0); |
120 | ||
121 | /* | |
122 | * Route 48MHz FREQ2 into USB Host and/or Device | |
123 | */ | |
2091a17f | 124 | sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT; |
1da177e4 LT |
125 | au_writel(sys_clksrc, SYS_CLKSRC); |
126 | ||
2091a17f SS |
127 | pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB; |
128 | /* 2nd USB port is USB host */ | |
129 | pin_func |= SYS_PF_USB; | |
1da177e4 | 130 | au_writel(pin_func, SYS_PINFUNC); |
f708631a | 131 | #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ |
1da177e4 | 132 | |
1da177e4 | 133 | #ifdef CONFIG_PCI |
2091a17f | 134 | /* Setup PCI bus controller */ |
1da177e4 LT |
135 | au_writel(0, Au1500_PCI_CMEM); |
136 | au_writel(0x00003fff, Au1500_CFG_BASE); | |
137 | #if defined(__MIPSEB__) | |
2091a17f | 138 | au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); |
1da177e4 LT |
139 | #else |
140 | au_writel(0xf, Au1500_PCI_CFG); | |
141 | #endif | |
142 | au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV); | |
143 | au_writel(0, Au1500_PCI_MWBASE_REV_CCL); | |
144 | au_writel(0x02a00356, Au1500_PCI_STATCMD); | |
145 | au_writel(0x00003c04, Au1500_PCI_HDRTYPE); | |
146 | au_writel(0x00000008, Au1500_PCI_MBAR); | |
147 | au_sync(); | |
148 | #endif | |
149 | ||
150 | /* Enable sys bus clock divider when IDLE state or no bus activity. */ | |
151 | au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); | |
152 | ||
153 | /* Enable the RTC if not already enabled */ | |
154 | if (!(au_readl(0xac000028) & 0x20)) { | |
2091a17f | 155 | printk(KERN_INFO "enabling clock ...\n"); |
1da177e4 LT |
156 | au_writel((au_readl(0xac000028) | 0x20), 0xac000028); |
157 | } | |
158 | /* Put the clock in BCD mode */ | |
2091a17f | 159 | if (au_readl(0xac00002c) & 0x4) { /* reg B */ |
1da177e4 LT |
160 | au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c); |
161 | au_sync(); | |
162 | } | |
163 | } |