[net-next-2.6.git] / arch / mips / alchemy / common / time.c

/*
 *
 * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
 * Copied and modified Carsten Langgaard's time.c
 *
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
 *
 * ########################################################################
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * ########################################################################
 *
 * Setting up the clock on the MIPS boards.
 *
 * We provide the clock interrupt processing and the timer offset compute
 * functions.  If CONFIG_PM is selected, we also ensure the 32KHz timer is
 * available.  -- Dan
 */

#include <linux/types.h>
#include <linux/init.h>
#include <linux/spinlock.h>

#include <asm/mipsregs.h>
#include <asm/time.h>
#include <asm/mach-au1x00/au1000.h>

static int no_au1xxx_32khz;
extern int allow_au1k_wait; /* default off for CP0 Counter */

#ifdef CONFIG_PM
#if HZ < 100 || HZ > 1000
#error "unsupported HZ value! Must be in [100,1000]"
#endif
#define MATCH20_INC (328 * 100 / HZ) /* magic number 328 is for HZ=100... */
static unsigned long last_pc0, last_match20;
#endif

static DEFINE_SPINLOCK(time_lock);

unsigned long wtimer;

#ifdef CONFIG_PM
static irqreturn_t counter0_irq(int irq, void *dev_id)
{
	unsigned long pc0;
	int time_elapsed;
	static int jiffie_drift;

	if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
		/* should never happen! */
		printk(KERN_WARNING "counter 0 w status error\n");
		return IRQ_NONE;
	}

	pc0 = au_readl(SYS_TOYREAD);
	if (pc0 < last_match20)
		/* counter overflowed */
		time_elapsed = (0xffffffff - last_match20) + pc0;
	else
		time_elapsed = pc0 - last_match20;

	while (time_elapsed > 0) {
		do_timer(1);
#ifndef CONFIG_SMP
		update_process_times(user_mode(get_irq_regs()));
#endif
		time_elapsed -= MATCH20_INC;
		last_match20 += MATCH20_INC;
		jiffie_drift++;
	}

	last_pc0 = pc0;
	au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
	au_sync();

	/*
	 * Our counter ticks at 10.009765625 ms/tick, we we're running
	 * almost 10 uS too slow per tick.
	 */

	if (jiffie_drift >= 999) {
		jiffie_drift -= 999;
		do_timer(1); /* increment jiffies by one */
#ifndef CONFIG_SMP
		update_process_times(user_mode(get_irq_regs()));
#endif
	}

	return IRQ_HANDLED;
}

struct irqaction counter0_action = {
	.handler	= counter0_irq,
	.flags		= IRQF_DISABLED,
	.name		= "alchemy-toy",
	.dev_id		= NULL,
};

/* When we wakeup from sleep, we have to "catch up" on all of the
 * timer ticks we have missed.
 */
void wakeup_counter0_adjust(void)
{
	unsigned long pc0;
	int time_elapsed;

	pc0 = au_readl(SYS_TOYREAD);
	if (pc0 < last_match20)
		/* counter overflowed */
		time_elapsed = (0xffffffff - last_match20) + pc0;
	else
		time_elapsed = pc0 - last_match20;

	while (time_elapsed > 0) {
		time_elapsed -= MATCH20_INC;
		last_match20 += MATCH20_INC;
	}

	last_pc0 = pc0;
	au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
	au_sync();

}

/* This is just for debugging to set the timer for a sleep delay. */
void wakeup_counter0_set(int ticks)
{
	unsigned long pc0;

	pc0 = au_readl(SYS_TOYREAD);
	last_pc0 = pc0;
	au_writel(last_match20 + (MATCH20_INC * ticks), SYS_TOYMATCH2);
	au_sync();
}
#endif

/*
 * I haven't found anyone that doesn't use a 12 MHz source clock,
 * but just in case.....
 */
#define AU1000_SRC_CLK	12000000

/*
 * We read the real processor speed from the PLL.  This is important
 * because it is more accurate than computing it from the 32 KHz
 * counter, if it exists.  If we don't have an accurate processor
 * speed, all of the peripherals that derive their clocks based on
 * this advertised speed will introduce error and sometimes not work
 * properly.  This function is futher convoluted to still allow configurations
 * to do that in case they have really, really old silicon with a
 * write-only PLL register, that we need the 32 KHz when power management
 * "wait" is enabled, and we need to detect if the 32 KHz isn't present
 * but requested......got it? :-)		-- Dan
 */
unsigned long calc_clock(void)
{
	unsigned long cpu_speed;
	unsigned long flags;
	unsigned long counter;

	spin_lock_irqsave(&time_lock, flags);

	/* Power management cares if we don't have a 32 KHz counter. */
	no_au1xxx_32khz = 0;
	counter = au_readl(SYS_COUNTER_CNTRL);
	if (counter & SYS_CNTRL_E0) {
		int trim_divide = 16;

		au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL);

		while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
		/* RTC now ticks at 32.768/16 kHz */
		au_writel(trim_divide - 1, SYS_RTCTRIM);
		while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);

		while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
		au_writel(0, SYS_TOYWRITE);
		while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
	} else
		no_au1xxx_32khz = 1;

	/*
	 * On early Au1000, sys_cpupll was write-only. Since these
	 * silicon versions of Au1000 are not sold by AMD, we don't bend
	 * over backwards trying to determine the frequency.
	 */
	if (au1xxx_cpu_has_pll_wo())
#ifdef CONFIG_SOC_AU1000_FREQUENCY
		cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;
#else
		cpu_speed = 396000000;
#endif
	else
		cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
	/* On Alchemy CPU:counter ratio is 1:1 */
	mips_hpt_frequency = cpu_speed;
	/* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */
	set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)
							  & 0x03) + 2) * 16));
	spin_unlock_irqrestore(&time_lock, flags);
	return cpu_speed;
}

void __init plat_time_init(void)
{
	unsigned int est_freq = calc_clock();

	est_freq += 5000;    /* round */
	est_freq -= est_freq%10000;
	printk(KERN_INFO "(PRId %08x) @ %u.%02u MHz\n", read_c0_prid(),
	       est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000);
	set_au1x00_speed(est_freq);

#ifdef CONFIG_PM
	/*
	 * setup counter 0, since it keeps ticking after a
	 * 'wait' instruction has been executed. The CP0 timer and
	 * counter 1 do NOT continue running after 'wait'
	 *
	 * It's too early to call request_irq() here, so we handle
	 * counter 0 interrupt as a special irq and it doesn't show
	 * up under /proc/interrupts.
	 *
	 * Check to ensure we really have a 32 KHz oscillator before
	 * we do this.
	 */
	if (no_au1xxx_32khz)
		printk(KERN_WARNING "WARNING: no 32KHz clock found.\n");
	else {
		while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
		au_writel(0, SYS_TOYWRITE);
		while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);

		au_writel(au_readl(SYS_WAKEMSK) | (1 << 8), SYS_WAKEMSK);
		au_writel(~0, SYS_WAKESRC);
		au_sync();
		while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);

		/* Setup match20 to interrupt once every HZ */
		last_pc0 = last_match20 = au_readl(SYS_TOYREAD);
		au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
		au_sync();
		while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
		setup_irq(AU1000_TOY_MATCH2_INT, &counter0_action);

		/* We can use the real 'wait' instruction. */
		allow_au1k_wait = 1;
	}

#endif
}
Commit	Line	Data
1da177e4 LT	1	/*
1da177e4 LT	2	*
01675095	3	* Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
1da177e4 LT	4	* Copied and modified Carsten Langgaard's time.c
	5	*
	6	* Carsten Langgaard, carstenl@mips.com
	7	* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
	8	*
	9	* ########################################################################
	10	*
	11	* This program is free software; you can distribute it and/or modify it
	12	* under the terms of the GNU General Public License (Version 2) as
	13	* published by the Free Software Foundation.
	14	*
	15	* This program is distributed in the hope it will be useful, but WITHOUT
	16	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	17	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	18	* for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License along
	21	* with this program; if not, write to the Free Software Foundation, Inc.,
	22	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	23	*
	24	* ########################################################################
	25	*
	26	* Setting up the clock on the MIPS boards.
	27	*
c1dcb14e SS	28	* We provide the clock interrupt processing and the timer offset compute
	29	* functions. If CONFIG_PM is selected, we also ensure the 32KHz timer is
	30	* available. -- Dan
1da177e4 LT	31	*/
	32
	33	#include <linux/types.h>
1da177e4	34	#include <linux/init.h>
1da177e4	35	#include <linux/spinlock.h>
1da177e4	36
1da177e4	37	#include <asm/mipsregs.h>
1da177e4	38	#include <asm/time.h>
1da177e4 LT	39	#include <asm/mach-au1x00/au1000.h>
1da177e4 LT	40
eba8291b	41	static int no_au1xxx_32khz;
fe359bf5	42	extern int allow_au1k_wait; /* default off for CP0 Counter */
1da177e4	43
1da177e4	44	#ifdef CONFIG_PM
3ce86ee1 PP	45	#if HZ < 100 \|\| HZ > 1000
	46	#error "unsupported HZ value! Must be in [100,1000]"
	47	#endif
c1dcb14e	48	#define MATCH20_INC (328 * 100 / HZ) /* magic number 328 is for HZ=100... */
1da177e4 LT	49	static unsigned long last_pc0, last_match20;
	50	#endif
	51
	52	static DEFINE_SPINLOCK(time_lock);
	53
1da177e4	54	unsigned long wtimer;
937a8015	55
1da177e4	56	#ifdef CONFIG_PM
310a09d8	57	static irqreturn_t counter0_irq(int irq, void *dev_id)
1da177e4 LT	58	{
	59	unsigned long pc0;
	60	int time_elapsed;
c1dcb14e	61	static int jiffie_drift;
1da177e4	62
1da177e4 LT	63	if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
1da177e4 LT	64	/* should never happen! */
3ce86ee1 PP	65	printk(KERN_WARNING "counter 0 w status error\n");
3ce86ee1 PP	66	return IRQ_NONE;
1da177e4 LT	67	}
	68
	69	pc0 = au_readl(SYS_TOYREAD);
c1dcb14e	70	if (pc0 < last_match20)
1da177e4 LT	71	/* counter overflowed */
1da177e4 LT	72	time_elapsed = (0xffffffff - last_match20) + pc0;
c1dcb14e	73	else
1da177e4	74	time_elapsed = pc0 - last_match20;
1da177e4 LT	75
1da177e4 LT	76	while (time_elapsed > 0) {
3171a030	77	do_timer(1);
1da177e4	78	#ifndef CONFIG_SMP
937a8015	79	update_process_times(user_mode(get_irq_regs()));
1da177e4 LT	80	#endif
	81	time_elapsed -= MATCH20_INC;
	82	last_match20 += MATCH20_INC;
	83	jiffie_drift++;
	84	}
	85
	86	last_pc0 = pc0;
	87	au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
	88	au_sync();
	89
c1dcb14e SS	90	/*
	91	* Our counter ticks at 10.009765625 ms/tick, we we're running
	92	* almost 10 uS too slow per tick.
1da177e4 LT	93	*/
	94
	95	if (jiffie_drift >= 999) {
	96	jiffie_drift -= 999;
3171a030	97	do_timer(1); /* increment jiffies by one */
1da177e4	98	#ifndef CONFIG_SMP
937a8015	99	update_process_times(user_mode(get_irq_regs()));
1da177e4 LT	100	#endif
1da177e4 LT	101	}
3ce86ee1 PP	102
3ce86ee1 PP	103	return IRQ_HANDLED;
1da177e4 LT	104	}
1da177e4 LT	105
310a09d8 RB	106	struct irqaction counter0_action = {
	107	.handler = counter0_irq,
	108	.flags = IRQF_DISABLED,
	109	.name = "alchemy-toy",
	110	.dev_id = NULL,
	111	};
	112
1da177e4 LT	113	/* When we wakeup from sleep, we have to "catch up" on all of the
	114	* timer ticks we have missed.
	115	*/
c1dcb14e	116	void wakeup_counter0_adjust(void)
1da177e4 LT	117	{
	118	unsigned long pc0;
	119	int time_elapsed;
	120
	121	pc0 = au_readl(SYS_TOYREAD);
c1dcb14e	122	if (pc0 < last_match20)
1da177e4 LT	123	/* counter overflowed */
1da177e4 LT	124	time_elapsed = (0xffffffff - last_match20) + pc0;
c1dcb14e	125	else
1da177e4	126	time_elapsed = pc0 - last_match20;
1da177e4 LT	127
	128	while (time_elapsed > 0) {
	129	time_elapsed -= MATCH20_INC;
	130	last_match20 += MATCH20_INC;
	131	}
	132
	133	last_pc0 = pc0;
	134	au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
	135	au_sync();
	136
	137	}
	138
c1dcb14e SS	139	/* This is just for debugging to set the timer for a sleep delay. */
c1dcb14e SS	140	void wakeup_counter0_set(int ticks)
1da177e4 LT	141	{
	142	unsigned long pc0;
	143
	144	pc0 = au_readl(SYS_TOYREAD);
	145	last_pc0 = pc0;
	146	au_writel(last_match20 + (MATCH20_INC * ticks), SYS_TOYMATCH2);
	147	au_sync();
	148	}
	149	#endif
	150
c1dcb14e SS	151	/*
c1dcb14e SS	152	* I haven't found anyone that doesn't use a 12 MHz source clock,
1da177e4 LT	153	* but just in case.....
1da177e4 LT	154	*/
1da177e4	155	#define AU1000_SRC_CLK 12000000
1da177e4 LT	156
	157	/*
	158	* We read the real processor speed from the PLL. This is important
c1dcb14e	159	* because it is more accurate than computing it from the 32 KHz
1da177e4 LT	160	* counter, if it exists. If we don't have an accurate processor
	161	* speed, all of the peripherals that derive their clocks based on
	162	* this advertised speed will introduce error and sometimes not work
	163	* properly. This function is futher convoluted to still allow configurations
	164	* to do that in case they have really, really old silicon with a
c1dcb14e SS	165	* write-only PLL register, that we need the 32 KHz when power management
c1dcb14e SS	166	* "wait" is enabled, and we need to detect if the 32 KHz isn't present
1da177e4 LT	167	* but requested......got it? :-) -- Dan
1da177e4 LT	168	*/
eba8291b	169	unsigned long calc_clock(void)
1da177e4	170	{
1da177e4 LT	171	unsigned long cpu_speed;
	172	unsigned long flags;
	173	unsigned long counter;
	174
	175	spin_lock_irqsave(&time_lock, flags);
	176
c1dcb14e	177	/* Power management cares if we don't have a 32 KHz counter. */
1da177e4 LT	178	no_au1xxx_32khz = 0;
	179	counter = au_readl(SYS_COUNTER_CNTRL);
	180	if (counter & SYS_CNTRL_E0) {
	181	int trim_divide = 16;
	182
	183	au_writel(counter \| SYS_CNTRL_EN1, SYS_COUNTER_CNTRL);
	184
	185	while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
	186	/* RTC now ticks at 32.768/16 kHz */
c1dcb14e	187	au_writel(trim_divide - 1, SYS_RTCTRIM);
1da177e4 LT	188	while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
	189
	190	while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
49a89efb	191	au_writel(0, SYS_TOYWRITE);
1da177e4	192	while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
758e285f SS	193	} else
758e285f SS	194	no_au1xxx_32khz = 1;
1da177e4	195
758e285f SS	196	/*
	197	* On early Au1000, sys_cpupll was write-only. Since these
	198	* silicon versions of Au1000 are not sold by AMD, we don't bend
	199	* over backwards trying to determine the frequency.
	200	*/
074cf656	201	if (au1xxx_cpu_has_pll_wo())
758e285f SS	202	#ifdef CONFIG_SOC_AU1000_FREQUENCY
	203	cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;
	204	#else
	205	cpu_speed = 396000000;
	206	#endif
	207	else
1da177e4	208	cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
c1dcb14e	209	/* On Alchemy CPU:counter ratio is 1:1 */
53c1b192	210	mips_hpt_frequency = cpu_speed;
c1dcb14e SS	211	/* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */
	212	set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)
	213	& 0x03) + 2) * 16));
1da177e4	214	spin_unlock_irqrestore(&time_lock, flags);
eba8291b	215	return cpu_speed;
1da177e4 LT	216	}
1da177e4 LT	217
bc2f2a24	218	void __init plat_time_init(void)
1da177e4	219	{
eba8291b	220	unsigned int est_freq = calc_clock();
1da177e4	221
1da177e4 LT	222	est_freq += 5000; /* round */
1da177e4 LT	223	est_freq -= est_freq%10000;
074cf656	224	printk(KERN_INFO "(PRId %08x) @ %u.%02u MHz\n", read_c0_prid(),
c1dcb14e SS	225	est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000);
c1dcb14e SS	226	set_au1x00_speed(est_freq);
1da177e4	227
1da177e4 LT	228	#ifdef CONFIG_PM
	229	/*
	230	* setup counter 0, since it keeps ticking after a
	231	* 'wait' instruction has been executed. The CP0 timer and
	232	* counter 1 do NOT continue running after 'wait'
	233	*
	234	* It's too early to call request_irq() here, so we handle
	235	* counter 0 interrupt as a special irq and it doesn't show
	236	* up under /proc/interrupts.
	237	*
c1dcb14e	238	* Check to ensure we really have a 32 KHz oscillator before
1da177e4 LT	239	* we do this.
1da177e4 LT	240	*/
01675095	241	if (no_au1xxx_32khz)
c1dcb14e	242	printk(KERN_WARNING "WARNING: no 32KHz clock found.\n");
1da177e4 LT	243	else {
	244	while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
	245	au_writel(0, SYS_TOYWRITE);
	246	while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
	247
c1dcb14e	248	au_writel(au_readl(SYS_WAKEMSK) \| (1 << 8), SYS_WAKEMSK);
1da177e4 LT	249	au_writel(~0, SYS_WAKESRC);
	250	au_sync();
	251	while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
	252
c1dcb14e	253	/* Setup match20 to interrupt once every HZ */
1da177e4 LT	254	last_pc0 = last_match20 = au_readl(SYS_TOYREAD);
	255	au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
	256	au_sync();
	257	while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
310a09d8	258	setup_irq(AU1000_TOY_MATCH2_INT, &counter0_action);
1da177e4	259
c1dcb14e	260	/* We can use the real 'wait' instruction. */
494900af	261	allow_au1k_wait = 1;
1da177e4 LT	262	}
1da177e4 LT	263
1da177e4 LT	264	#endif
1da177e4 LT	265	}