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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
e08e6c52 | 6 | * Copyright (C) 1999,2001-2006 Silicon Graphics, Inc. All rights reserved. |
1da177e4 LT |
7 | */ |
8 | ||
9 | #include <linux/config.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/kdev_t.h> | |
15 | #include <linux/string.h> | |
16 | #include <linux/tty.h> | |
17 | #include <linux/console.h> | |
18 | #include <linux/timex.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/ioport.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/serial.h> | |
23 | #include <linux/irq.h> | |
24 | #include <linux/bootmem.h> | |
25 | #include <linux/mmzone.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/acpi.h> | |
28 | #include <linux/compiler.h> | |
29 | #include <linux/sched.h> | |
30 | #include <linux/root_dev.h> | |
31 | #include <linux/nodemask.h> | |
c1298c5c | 32 | #include <linux/pm.h> |
ff51224c | 33 | #include <linux/efi.h> |
1da177e4 LT |
34 | |
35 | #include <asm/io.h> | |
36 | #include <asm/sal.h> | |
37 | #include <asm/machvec.h> | |
38 | #include <asm/system.h> | |
39 | #include <asm/processor.h> | |
a9f9de73 | 40 | #include <asm/vga.h> |
1da177e4 LT |
41 | #include <asm/sn/arch.h> |
42 | #include <asm/sn/addrs.h> | |
43 | #include <asm/sn/pda.h> | |
44 | #include <asm/sn/nodepda.h> | |
45 | #include <asm/sn/sn_cpuid.h> | |
46 | #include <asm/sn/simulator.h> | |
47 | #include <asm/sn/leds.h> | |
48 | #include <asm/sn/bte.h> | |
49 | #include <asm/sn/shub_mmr.h> | |
50 | #include <asm/sn/clksupport.h> | |
51 | #include <asm/sn/sn_sal.h> | |
52 | #include <asm/sn/geo.h> | |
a1cddb88 | 53 | #include <asm/sn/sn_feature_sets.h> |
1da177e4 LT |
54 | #include "xtalk/xwidgetdev.h" |
55 | #include "xtalk/hubdev.h" | |
56 | #include <asm/sn/klconfig.h> | |
57 | ||
58 | ||
59 | DEFINE_PER_CPU(struct pda_s, pda_percpu); | |
60 | ||
9b17e7e7 | 61 | #define MAX_PHYS_MEMORY (1UL << IA64_MAX_PHYS_BITS) /* Max physical address supported */ |
1da177e4 | 62 | |
1da177e4 LT |
63 | extern void bte_init_node(nodepda_t *, cnodeid_t); |
64 | ||
65 | extern void sn_timer_init(void); | |
66 | extern unsigned long last_time_offset; | |
67 | extern void (*ia64_mark_idle) (int); | |
68 | extern void snidle(int); | |
69 | extern unsigned char acpi_kbd_controller_present; | |
d6e56a2a | 70 | extern unsigned long long (*ia64_printk_clock)(void); |
1da177e4 LT |
71 | |
72 | unsigned long sn_rtc_cycles_per_second; | |
73 | EXPORT_SYMBOL(sn_rtc_cycles_per_second); | |
74 | ||
75 | DEFINE_PER_CPU(struct sn_hub_info_s, __sn_hub_info); | |
76 | EXPORT_PER_CPU_SYMBOL(__sn_hub_info); | |
77 | ||
c2a4969b | 78 | DEFINE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_COMPACT_NODES]); |
2e34f07f DN |
79 | EXPORT_PER_CPU_SYMBOL(__sn_cnodeid_to_nasid); |
80 | ||
9b48b466 DN |
81 | DEFINE_PER_CPU(struct nodepda_s *, __sn_nodepda); |
82 | EXPORT_PER_CPU_SYMBOL(__sn_nodepda); | |
83 | ||
1da177e4 LT |
84 | char sn_system_serial_number_string[128]; |
85 | EXPORT_SYMBOL(sn_system_serial_number_string); | |
86 | u64 sn_partition_serial_number; | |
87 | EXPORT_SYMBOL(sn_partition_serial_number); | |
88 | u8 sn_partition_id; | |
89 | EXPORT_SYMBOL(sn_partition_id); | |
90 | u8 sn_system_size; | |
91 | EXPORT_SYMBOL(sn_system_size); | |
92 | u8 sn_sharing_domain_size; | |
93 | EXPORT_SYMBOL(sn_sharing_domain_size); | |
94 | u8 sn_coherency_id; | |
95 | EXPORT_SYMBOL(sn_coherency_id); | |
96 | u8 sn_region_size; | |
97 | EXPORT_SYMBOL(sn_region_size); | |
71a5d027 | 98 | int sn_prom_type; /* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */ |
1da177e4 | 99 | |
24ee0a6d | 100 | short physical_node_map[MAX_NUMALINK_NODES]; |
a1cddb88 | 101 | static unsigned long sn_prom_features[MAX_PROM_FEATURE_SETS]; |
1da177e4 LT |
102 | |
103 | EXPORT_SYMBOL(physical_node_map); | |
104 | ||
24ee0a6d | 105 | int num_cnodes; |
1da177e4 LT |
106 | |
107 | static void sn_init_pdas(char **); | |
24ee0a6d | 108 | static void build_cnode_tables(void); |
1da177e4 LT |
109 | |
110 | static nodepda_t *nodepdaindr[MAX_COMPACT_NODES]; | |
111 | ||
112 | /* | |
113 | * The format of "screen_info" is strange, and due to early i386-setup | |
114 | * code. This is just enough to make the console code think we're on a | |
115 | * VGA color display. | |
116 | */ | |
117 | struct screen_info sn_screen_info = { | |
118 | .orig_x = 0, | |
119 | .orig_y = 0, | |
120 | .orig_video_mode = 3, | |
121 | .orig_video_cols = 80, | |
122 | .orig_video_ega_bx = 3, | |
123 | .orig_video_lines = 25, | |
124 | .orig_video_isVGA = 1, | |
125 | .orig_video_points = 16 | |
126 | }; | |
127 | ||
1da177e4 LT |
128 | /* |
129 | * This routine can only be used during init, since | |
130 | * smp_boot_data is an init data structure. | |
131 | * We have to use smp_boot_data.cpu_phys_id to find | |
132 | * the physical id of the processor because the normal | |
133 | * cpu_physical_id() relies on data structures that | |
134 | * may not be initialized yet. | |
135 | */ | |
136 | ||
137 | static int __init pxm_to_nasid(int pxm) | |
138 | { | |
139 | int i; | |
140 | int nid; | |
141 | ||
762834e8 | 142 | nid = pxm_to_node(pxm); |
1da177e4 LT |
143 | for (i = 0; i < num_node_memblks; i++) { |
144 | if (node_memblk[i].nid == nid) { | |
145 | return NASID_GET(node_memblk[i].start_paddr); | |
146 | } | |
147 | } | |
148 | return -1; | |
149 | } | |
150 | ||
151 | /** | |
152 | * early_sn_setup - early setup routine for SN platforms | |
153 | * | |
154 | * Sets up an initial console to aid debugging. Intended primarily | |
155 | * for bringup. See start_kernel() in init/main.c. | |
156 | */ | |
157 | ||
158 | void __init early_sn_setup(void) | |
159 | { | |
160 | efi_system_table_t *efi_systab; | |
161 | efi_config_table_t *config_tables; | |
162 | struct ia64_sal_systab *sal_systab; | |
163 | struct ia64_sal_desc_entry_point *ep; | |
164 | char *p; | |
165 | int i, j; | |
166 | ||
167 | /* | |
168 | * Parse enough of the SAL tables to locate the SAL entry point. Since, console | |
169 | * IO on SN2 is done via SAL calls, early_printk won't work without this. | |
170 | * | |
171 | * This code duplicates some of the ACPI table parsing that is in efi.c & sal.c. | |
172 | * Any changes to those file may have to be made hereas well. | |
173 | */ | |
174 | efi_systab = (efi_system_table_t *) __va(ia64_boot_param->efi_systab); | |
175 | config_tables = __va(efi_systab->tables); | |
176 | for (i = 0; i < efi_systab->nr_tables; i++) { | |
177 | if (efi_guidcmp(config_tables[i].guid, SAL_SYSTEM_TABLE_GUID) == | |
178 | 0) { | |
179 | sal_systab = __va(config_tables[i].table); | |
180 | p = (char *)(sal_systab + 1); | |
181 | for (j = 0; j < sal_systab->entry_count; j++) { | |
182 | if (*p == SAL_DESC_ENTRY_POINT) { | |
183 | ep = (struct ia64_sal_desc_entry_point | |
184 | *)p; | |
185 | ia64_sal_handler_init(__va | |
186 | (ep->sal_proc), | |
187 | __va(ep->gp)); | |
188 | return; | |
189 | } | |
190 | p += SAL_DESC_SIZE(*p); | |
191 | } | |
192 | } | |
193 | } | |
194 | /* Uh-oh, SAL not available?? */ | |
195 | printk(KERN_ERR "failed to find SAL entry point\n"); | |
196 | } | |
197 | ||
198 | extern int platform_intr_list[]; | |
2fcc3db0 | 199 | static int __initdata shub_1_1_found; |
1da177e4 LT |
200 | |
201 | /* | |
202 | * sn_check_for_wars | |
203 | * | |
204 | * Set flag for enabling shub specific wars | |
205 | */ | |
206 | ||
207 | static inline int __init is_shub_1_1(int nasid) | |
208 | { | |
209 | unsigned long id; | |
210 | int rev; | |
211 | ||
212 | if (is_shub2()) | |
213 | return 0; | |
214 | id = REMOTE_HUB_L(nasid, SH1_SHUB_ID); | |
215 | rev = (id & SH1_SHUB_ID_REVISION_MASK) >> SH1_SHUB_ID_REVISION_SHFT; | |
216 | return rev <= 2; | |
217 | } | |
218 | ||
219 | static void __init sn_check_for_wars(void) | |
220 | { | |
221 | int cnode; | |
222 | ||
223 | if (is_shub2()) { | |
224 | /* none yet */ | |
225 | } else { | |
226 | for_each_online_node(cnode) { | |
227 | if (is_shub_1_1(cnodeid_to_nasid(cnode))) | |
ff89bf3b | 228 | shub_1_1_found = 1; |
1da177e4 LT |
229 | } |
230 | } | |
231 | } | |
232 | ||
ff51224c MM |
233 | /* |
234 | * Scan the EFI PCDP table (if it exists) for an acceptable VGA console | |
235 | * output device. If one exists, pick it and set sn_legacy_{io,mem} to | |
236 | * reflect the bus offsets needed to address it. | |
237 | * | |
238 | * Since pcdp support in SN is not supported in the 2.4 kernel (or at least | |
239 | * the one lbs is based on) just declare the needed structs here. | |
240 | * | |
241 | * Reference spec http://www.dig64.org/specifications/DIG64_PCDPv20.pdf | |
242 | * | |
243 | * Returns 0 if no acceptable vga is found, !0 otherwise. | |
244 | * | |
245 | * Note: This stuff is duped here because Altix requires the PCDP to | |
246 | * locate a usable VGA device due to lack of proper ACPI support. Structures | |
247 | * could be used from drivers/firmware/pcdp.h, but it was decided that moving | |
248 | * this file to a more public location just for Altix use was undesireable. | |
249 | */ | |
250 | ||
251 | struct hcdp_uart_desc { | |
252 | u8 pad[45]; | |
253 | }; | |
254 | ||
255 | struct pcdp { | |
256 | u8 signature[4]; /* should be 'HCDP' */ | |
257 | u32 length; | |
258 | u8 rev; /* should be >=3 for pcdp, <3 for hcdp */ | |
259 | u8 sum; | |
260 | u8 oem_id[6]; | |
261 | u64 oem_tableid; | |
262 | u32 oem_rev; | |
263 | u32 creator_id; | |
264 | u32 creator_rev; | |
265 | u32 num_type0; | |
266 | struct hcdp_uart_desc uart[0]; /* num_type0 of these */ | |
267 | /* pcdp descriptors follow */ | |
268 | } __attribute__((packed)); | |
269 | ||
270 | struct pcdp_device_desc { | |
271 | u8 type; | |
272 | u8 primary; | |
273 | u16 length; | |
274 | u16 index; | |
275 | /* interconnect specific structure follows */ | |
276 | /* device specific structure follows that */ | |
277 | } __attribute__((packed)); | |
278 | ||
279 | struct pcdp_interface_pci { | |
280 | u8 type; /* 1 == pci */ | |
281 | u8 reserved; | |
282 | u16 length; | |
283 | u8 segment; | |
284 | u8 bus; | |
285 | u8 dev; | |
286 | u8 fun; | |
287 | u16 devid; | |
288 | u16 vendid; | |
289 | u32 acpi_interrupt; | |
290 | u64 mmio_tra; | |
291 | u64 ioport_tra; | |
292 | u8 flags; | |
293 | u8 translation; | |
294 | } __attribute__((packed)); | |
295 | ||
296 | struct pcdp_vga_device { | |
297 | u8 num_eas_desc; | |
298 | /* ACPI Extended Address Space Desc follows */ | |
299 | } __attribute__((packed)); | |
300 | ||
301 | /* from pcdp_device_desc.primary */ | |
302 | #define PCDP_PRIMARY_CONSOLE 0x01 | |
303 | ||
304 | /* from pcdp_device_desc.type */ | |
305 | #define PCDP_CONSOLE_INOUT 0x0 | |
306 | #define PCDP_CONSOLE_DEBUG 0x1 | |
307 | #define PCDP_CONSOLE_OUT 0x2 | |
308 | #define PCDP_CONSOLE_IN 0x3 | |
309 | #define PCDP_CONSOLE_TYPE_VGA 0x8 | |
310 | ||
311 | #define PCDP_CONSOLE_VGA (PCDP_CONSOLE_TYPE_VGA | PCDP_CONSOLE_OUT) | |
312 | ||
313 | /* from pcdp_interface_pci.type */ | |
314 | #define PCDP_IF_PCI 1 | |
315 | ||
316 | /* from pcdp_interface_pci.translation */ | |
317 | #define PCDP_PCI_TRANS_IOPORT 0x02 | |
318 | #define PCDP_PCI_TRANS_MMIO 0x01 | |
319 | ||
26d10915 | 320 | #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) |
ff51224c MM |
321 | static void |
322 | sn_scan_pcdp(void) | |
323 | { | |
324 | u8 *bp; | |
325 | struct pcdp *pcdp; | |
326 | struct pcdp_device_desc device; | |
327 | struct pcdp_interface_pci if_pci; | |
328 | extern struct efi efi; | |
329 | ||
b2c99e3c | 330 | if (efi.hcdp == EFI_INVALID_TABLE_ADDR) |
ff51224c MM |
331 | return; /* no hcdp/pcdp table */ |
332 | ||
b2c99e3c BH |
333 | pcdp = __va(efi.hcdp); |
334 | ||
ff51224c MM |
335 | if (pcdp->rev < 3) |
336 | return; /* only support PCDP (rev >= 3) */ | |
337 | ||
338 | for (bp = (u8 *)&pcdp->uart[pcdp->num_type0]; | |
339 | bp < (u8 *)pcdp + pcdp->length; | |
340 | bp += device.length) { | |
341 | memcpy(&device, bp, sizeof(device)); | |
342 | if (! (device.primary & PCDP_PRIMARY_CONSOLE)) | |
343 | continue; /* not primary console */ | |
344 | ||
345 | if (device.type != PCDP_CONSOLE_VGA) | |
346 | continue; /* not VGA descriptor */ | |
347 | ||
348 | memcpy(&if_pci, bp+sizeof(device), sizeof(if_pci)); | |
349 | if (if_pci.type != PCDP_IF_PCI) | |
350 | continue; /* not PCI interconnect */ | |
351 | ||
352 | if (if_pci.translation & PCDP_PCI_TRANS_IOPORT) | |
353 | vga_console_iobase = | |
354 | if_pci.ioport_tra | __IA64_UNCACHED_OFFSET; | |
355 | ||
356 | if (if_pci.translation & PCDP_PCI_TRANS_MMIO) | |
357 | vga_console_membase = | |
358 | if_pci.mmio_tra | __IA64_UNCACHED_OFFSET; | |
359 | ||
360 | break; /* once we find the primary, we're done */ | |
361 | } | |
362 | } | |
26d10915 | 363 | #endif |
ff51224c | 364 | |
d6e56a2a TL |
365 | static unsigned long sn2_rtc_initial; |
366 | ||
367 | static unsigned long long ia64_sn2_printk_clock(void) | |
368 | { | |
369 | unsigned long rtc_now = rtc_time(); | |
370 | ||
371 | return (rtc_now - sn2_rtc_initial) * | |
372 | (1000000000 / sn_rtc_cycles_per_second); | |
373 | } | |
374 | ||
1da177e4 LT |
375 | /** |
376 | * sn_setup - SN platform setup routine | |
377 | * @cmdline_p: kernel command line | |
378 | * | |
379 | * Handles platform setup for SN machines. This includes determining | |
380 | * the RTC frequency (via a SAL call), initializing secondary CPUs, and | |
381 | * setting up per-node data areas. The console is also initialized here. | |
382 | */ | |
383 | void __init sn_setup(char **cmdline_p) | |
384 | { | |
385 | long status, ticks_per_sec, drift; | |
283c7f6a | 386 | u32 version = sn_sal_rev(); |
1da177e4 LT |
387 | extern void sn_cpu_init(void); |
388 | ||
d6e56a2a | 389 | sn2_rtc_initial = rtc_time(); |
a1cddb88 JS |
390 | ia64_sn_plat_set_error_handling_features(); // obsolete |
391 | ia64_sn_set_os_feature(OSF_MCA_SLV_TO_OS_INIT_SLV); | |
392 | ia64_sn_set_os_feature(OSF_FEAT_LOG_SBES); | |
393 | ||
6872ec54 | 394 | |
a9f9de73 | 395 | #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) |
1da177e4 | 396 | /* |
ff51224c MM |
397 | * Handle SN vga console. |
398 | * | |
399 | * SN systems do not have enough ACPI table information | |
400 | * being passed from prom to identify VGA adapters and the legacy | |
401 | * addresses to access them. Until that is done, SN systems rely | |
402 | * on the PCDP table to identify the primary VGA console if one | |
403 | * exists. | |
404 | * | |
405 | * However, kernel PCDP support is optional, and even if it is built | |
406 | * into the kernel, it will not be used if the boot cmdline contains | |
407 | * console= directives. | |
408 | * | |
409 | * So, to work around this mess, we duplicate some of the PCDP code | |
410 | * here so that the primary VGA console (as defined by PCDP) will | |
411 | * work on SN systems even if a different console (e.g. serial) is | |
412 | * selected on the boot line (or CONFIG_EFI_PCDP is off). | |
1da177e4 | 413 | */ |
a9f9de73 | 414 | |
ff51224c MM |
415 | if (! vga_console_membase) |
416 | sn_scan_pcdp(); | |
417 | ||
a9f9de73 MM |
418 | if (vga_console_membase) { |
419 | /* usable vga ... make tty0 the preferred default console */ | |
ff51224c MM |
420 | if (!strstr(*cmdline_p, "console=")) |
421 | add_preferred_console("tty", 0, NULL); | |
a9f9de73 | 422 | } else { |
1da177e4 | 423 | printk(KERN_DEBUG "SGI: Disabling VGA console\n"); |
ff51224c MM |
424 | if (!strstr(*cmdline_p, "console=")) |
425 | add_preferred_console("ttySG", 0, NULL); | |
1da177e4 LT |
426 | #ifdef CONFIG_DUMMY_CONSOLE |
427 | conswitchp = &dummy_con; | |
428 | #else | |
429 | conswitchp = NULL; | |
430 | #endif /* CONFIG_DUMMY_CONSOLE */ | |
431 | } | |
432 | #endif /* def(CONFIG_VT) && def(CONFIG_VGA_CONSOLE) */ | |
433 | ||
434 | MAX_DMA_ADDRESS = PAGE_OFFSET + MAX_PHYS_MEMORY; | |
435 | ||
24ee0a6d JS |
436 | /* |
437 | * Build the tables for managing cnodes. | |
438 | */ | |
439 | build_cnode_tables(); | |
1da177e4 | 440 | |
1da177e4 LT |
441 | status = |
442 | ia64_sal_freq_base(SAL_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec, | |
443 | &drift); | |
444 | if (status != 0 || ticks_per_sec < 100000) { | |
445 | printk(KERN_WARNING | |
446 | "unable to determine platform RTC clock frequency, guessing.\n"); | |
447 | /* PROM gives wrong value for clock freq. so guess */ | |
448 | sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; | |
449 | } else | |
450 | sn_rtc_cycles_per_second = ticks_per_sec; | |
451 | ||
452 | platform_intr_list[ACPI_INTERRUPT_CPEI] = IA64_CPE_VECTOR; | |
453 | ||
d6e56a2a TL |
454 | ia64_printk_clock = ia64_sn2_printk_clock; |
455 | ||
456 | /* | |
457 | * Old PROMs do not provide an ACPI FADT. Disable legacy keyboard | |
458 | * support here so we don't have to listen to failed keyboard probe | |
459 | * messages. | |
460 | */ | |
461 | if (version <= 0x0209 && acpi_kbd_controller_present) { | |
462 | printk(KERN_INFO "Disabling legacy keyboard support as prom " | |
463 | "is too old and doesn't provide FADT\n"); | |
464 | acpi_kbd_controller_present = 0; | |
465 | } | |
466 | ||
467 | printk("SGI SAL version %x.%02x\n", version >> 8, version & 0x00FF); | |
468 | ||
1da177e4 LT |
469 | /* |
470 | * we set the default root device to /dev/hda | |
471 | * to make simulation easy | |
472 | */ | |
473 | ROOT_DEV = Root_HDA1; | |
474 | ||
475 | /* | |
476 | * Create the PDAs and NODEPDAs for all the cpus. | |
477 | */ | |
478 | sn_init_pdas(cmdline_p); | |
479 | ||
480 | ia64_mark_idle = &snidle; | |
481 | ||
71a5d027 | 482 | /* |
1da177e4 LT |
483 | * For the bootcpu, we do this here. All other cpus will make the |
484 | * call as part of cpu_init in slave cpu initialization. | |
485 | */ | |
486 | sn_cpu_init(); | |
487 | ||
488 | #ifdef CONFIG_SMP | |
489 | init_smp_config(); | |
490 | #endif | |
491 | screen_info = sn_screen_info; | |
492 | ||
493 | sn_timer_init(); | |
c1298c5c AY |
494 | |
495 | /* | |
496 | * set pm_power_off to a SAL call to allow | |
497 | * sn machines to power off. The SAL call can be replaced | |
498 | * by an ACPI interface call when ACPI is fully implemented | |
499 | * for sn. | |
500 | */ | |
501 | pm_power_off = ia64_sn_power_down; | |
e08e6c52 | 502 | current->thread.flags |= IA64_THREAD_MIGRATION; |
1da177e4 LT |
503 | } |
504 | ||
505 | /** | |
506 | * sn_init_pdas - setup node data areas | |
507 | * | |
508 | * One time setup for Node Data Area. Called by sn_setup(). | |
509 | */ | |
510 | static void __init sn_init_pdas(char **cmdline_p) | |
511 | { | |
512 | cnodeid_t cnode; | |
513 | ||
1da177e4 LT |
514 | /* |
515 | * Allocate & initalize the nodepda for each node. | |
516 | */ | |
517 | for_each_online_node(cnode) { | |
518 | nodepdaindr[cnode] = | |
519 | alloc_bootmem_node(NODE_DATA(cnode), sizeof(nodepda_t)); | |
520 | memset(nodepdaindr[cnode], 0, sizeof(nodepda_t)); | |
71a5d027 | 521 | memset(nodepdaindr[cnode]->phys_cpuid, -1, |
1da177e4 | 522 | sizeof(nodepdaindr[cnode]->phys_cpuid)); |
470ceb05 | 523 | spin_lock_init(&nodepdaindr[cnode]->ptc_lock); |
1da177e4 LT |
524 | } |
525 | ||
526 | /* | |
527 | * Allocate & initialize nodepda for TIOs. For now, put them on node 0. | |
528 | */ | |
24ee0a6d | 529 | for (cnode = num_online_nodes(); cnode < num_cnodes; cnode++) { |
1da177e4 LT |
530 | nodepdaindr[cnode] = |
531 | alloc_bootmem_node(NODE_DATA(0), sizeof(nodepda_t)); | |
532 | memset(nodepdaindr[cnode], 0, sizeof(nodepda_t)); | |
533 | } | |
534 | ||
535 | /* | |
536 | * Now copy the array of nodepda pointers to each nodepda. | |
537 | */ | |
24ee0a6d | 538 | for (cnode = 0; cnode < num_cnodes; cnode++) |
1da177e4 LT |
539 | memcpy(nodepdaindr[cnode]->pernode_pdaindr, nodepdaindr, |
540 | sizeof(nodepdaindr)); | |
541 | ||
542 | /* | |
543 | * Set up IO related platform-dependent nodepda fields. | |
544 | * The following routine actually sets up the hubinfo struct | |
545 | * in nodepda. | |
546 | */ | |
547 | for_each_online_node(cnode) { | |
548 | bte_init_node(nodepdaindr[cnode], cnode); | |
549 | } | |
550 | ||
551 | /* | |
71a5d027 | 552 | * Initialize the per node hubdev. This includes IO Nodes and |
1da177e4 LT |
553 | * headless/memless nodes. |
554 | */ | |
24ee0a6d | 555 | for (cnode = 0; cnode < num_cnodes; cnode++) { |
1da177e4 LT |
556 | hubdev_init_node(nodepdaindr[cnode], cnode); |
557 | } | |
558 | } | |
559 | ||
560 | /** | |
561 | * sn_cpu_init - initialize per-cpu data areas | |
562 | * @cpuid: cpuid of the caller | |
563 | * | |
564 | * Called during cpu initialization on each cpu as it starts. | |
565 | * Currently, initializes the per-cpu data area for SNIA. | |
566 | * Also sets up a few fields in the nodepda. Also known as | |
567 | * platform_cpu_init() by the ia64 machvec code. | |
568 | */ | |
569 | void __init sn_cpu_init(void) | |
570 | { | |
571 | int cpuid; | |
572 | int cpuphyid; | |
573 | int nasid; | |
574 | int subnode; | |
575 | int slice; | |
576 | int cnode; | |
577 | int i; | |
578 | static int wars_have_been_checked; | |
579 | ||
71a5d027 JS |
580 | if (smp_processor_id() == 0 && IS_MEDUSA()) { |
581 | if (ia64_sn_is_fake_prom()) | |
582 | sn_prom_type = 2; | |
583 | else | |
584 | sn_prom_type = 1; | |
2fcc3db0 JS |
585 | printk(KERN_INFO "Running on medusa with %s PROM\n", |
586 | (sn_prom_type == 1) ? "real" : "fake"); | |
71a5d027 JS |
587 | } |
588 | ||
1da177e4 | 589 | memset(pda, 0, sizeof(pda)); |
2fcc3db0 JS |
590 | if (ia64_sn_get_sn_info(0, &sn_hub_info->shub2, |
591 | &sn_hub_info->nasid_bitmask, | |
592 | &sn_hub_info->nasid_shift, | |
593 | &sn_system_size, &sn_sharing_domain_size, | |
594 | &sn_partition_id, &sn_coherency_id, | |
595 | &sn_region_size)) | |
1da177e4 LT |
596 | BUG(); |
597 | sn_hub_info->as_shift = sn_hub_info->nasid_shift - 2; | |
598 | ||
599 | /* | |
600 | * The boot cpu makes this call again after platform initialization is | |
601 | * complete. | |
602 | */ | |
603 | if (nodepdaindr[0] == NULL) | |
604 | return; | |
605 | ||
a1cddb88 JS |
606 | for (i = 0; i < MAX_PROM_FEATURE_SETS; i++) |
607 | if (ia64_sn_get_prom_feature_set(i, &sn_prom_features[i]) != 0) | |
608 | break; | |
609 | ||
1da177e4 LT |
610 | cpuid = smp_processor_id(); |
611 | cpuphyid = get_sapicid(); | |
612 | ||
613 | if (ia64_sn_get_sapic_info(cpuphyid, &nasid, &subnode, &slice)) | |
614 | BUG(); | |
615 | ||
616 | for (i=0; i < MAX_NUMNODES; i++) { | |
617 | if (nodepdaindr[i]) { | |
618 | nodepdaindr[i]->phys_cpuid[cpuid].nasid = nasid; | |
619 | nodepdaindr[i]->phys_cpuid[cpuid].slice = slice; | |
620 | nodepdaindr[i]->phys_cpuid[cpuid].subnode = subnode; | |
621 | } | |
622 | } | |
623 | ||
624 | cnode = nasid_to_cnodeid(nasid); | |
625 | ||
9b48b466 DN |
626 | sn_nodepda = nodepdaindr[cnode]; |
627 | ||
1da177e4 LT |
628 | pda->led_address = |
629 | (typeof(pda->led_address)) (LED0 + (slice << LED_CPU_SHIFT)); | |
630 | pda->led_state = LED_ALWAYS_SET; | |
631 | pda->hb_count = HZ / 2; | |
632 | pda->hb_state = 0; | |
633 | pda->idle_flag = 0; | |
634 | ||
635 | if (cpuid != 0) { | |
2e34f07f DN |
636 | /* copy cpu 0's sn_cnodeid_to_nasid table to this cpu's */ |
637 | memcpy(sn_cnodeid_to_nasid, | |
638 | (&per_cpu(__sn_cnodeid_to_nasid, 0)), | |
639 | sizeof(__ia64_per_cpu_var(__sn_cnodeid_to_nasid))); | |
1da177e4 LT |
640 | } |
641 | ||
642 | /* | |
643 | * Check for WARs. | |
644 | * Only needs to be done once, on BSP. | |
2e34f07f DN |
645 | * Has to be done after loop above, because it uses this cpu's |
646 | * sn_cnodeid_to_nasid table which was just initialized if this | |
647 | * isn't cpu 0. | |
1da177e4 LT |
648 | * Has to be done before assignment below. |
649 | */ | |
650 | if (!wars_have_been_checked) { | |
651 | sn_check_for_wars(); | |
652 | wars_have_been_checked = 1; | |
653 | } | |
654 | sn_hub_info->shub_1_1_found = shub_1_1_found; | |
655 | ||
656 | /* | |
657 | * Set up addresses of PIO/MEM write status registers. | |
658 | */ | |
659 | { | |
660 | u64 pio1[] = {SH1_PIO_WRITE_STATUS_0, 0, SH1_PIO_WRITE_STATUS_1, 0}; | |
2fdbb590 JS |
661 | u64 pio2[] = {SH2_PIO_WRITE_STATUS_0, SH2_PIO_WRITE_STATUS_2, |
662 | SH2_PIO_WRITE_STATUS_1, SH2_PIO_WRITE_STATUS_3}; | |
1da177e4 LT |
663 | u64 *pio; |
664 | pio = is_shub1() ? pio1 : pio2; | |
e08e6c52 BC |
665 | pda->pio_write_status_addr = |
666 | (volatile unsigned long *)GLOBAL_MMR_ADDR(nasid, pio[slice]); | |
1da177e4 LT |
667 | pda->pio_write_status_val = is_shub1() ? SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK : 0; |
668 | } | |
669 | ||
670 | /* | |
671 | * WAR addresses for SHUB 1.x. | |
672 | */ | |
673 | if (local_node_data->active_cpu_count++ == 0 && is_shub1()) { | |
674 | int buddy_nasid; | |
675 | buddy_nasid = | |
676 | cnodeid_to_nasid(numa_node_id() == | |
677 | num_online_nodes() - 1 ? 0 : numa_node_id() + 1); | |
678 | pda->pio_shub_war_cam_addr = | |
679 | (volatile unsigned long *)GLOBAL_MMR_ADDR(nasid, | |
680 | SH1_PI_CAM_CONTROL); | |
681 | } | |
682 | } | |
683 | ||
684 | /* | |
24ee0a6d | 685 | * Build tables for converting between NASIDs and cnodes. |
1da177e4 | 686 | */ |
24ee0a6d JS |
687 | static inline int __init board_needs_cnode(int type) |
688 | { | |
689 | return (type == KLTYPE_SNIA || type == KLTYPE_TIO); | |
690 | } | |
1da177e4 | 691 | |
24ee0a6d | 692 | void __init build_cnode_tables(void) |
1da177e4 | 693 | { |
24ee0a6d JS |
694 | int nasid; |
695 | int node; | |
1da177e4 LT |
696 | lboard_t *brd; |
697 | ||
24ee0a6d JS |
698 | memset(physical_node_map, -1, sizeof(physical_node_map)); |
699 | memset(sn_cnodeid_to_nasid, -1, | |
700 | sizeof(__ia64_per_cpu_var(__sn_cnodeid_to_nasid))); | |
1da177e4 | 701 | |
24ee0a6d JS |
702 | /* |
703 | * First populate the tables with C/M bricks. This ensures that | |
704 | * cnode == node for all C & M bricks. | |
705 | */ | |
706 | for_each_online_node(node) { | |
762834e8 | 707 | nasid = pxm_to_nasid(node_to_pxm(node)); |
24ee0a6d JS |
708 | sn_cnodeid_to_nasid[node] = nasid; |
709 | physical_node_map[nasid] = node; | |
1da177e4 LT |
710 | } |
711 | ||
24ee0a6d JS |
712 | /* |
713 | * num_cnodes is total number of C/M/TIO bricks. Because of the 256 node | |
714 | * limit on the number of nodes, we can't use the generic node numbers | |
715 | * for this. Note that num_cnodes is incremented below as TIOs or | |
716 | * headless/memoryless nodes are discovered. | |
717 | */ | |
718 | num_cnodes = num_online_nodes(); | |
1da177e4 | 719 | |
24ee0a6d JS |
720 | /* fakeprom does not support klgraph */ |
721 | if (IS_RUNNING_ON_FAKE_PROM()) | |
722 | return; | |
1da177e4 | 723 | |
24ee0a6d JS |
724 | /* Find TIOs & headless/memoryless nodes and add them to the tables */ |
725 | for_each_online_node(node) { | |
726 | kl_config_hdr_t *klgraph_header; | |
727 | nasid = cnodeid_to_nasid(node); | |
2fcc3db0 JS |
728 | klgraph_header = ia64_sn_get_klconfig_addr(nasid); |
729 | if (klgraph_header == NULL) | |
24ee0a6d JS |
730 | BUG(); |
731 | brd = NODE_OFFSET_TO_LBOARD(nasid, klgraph_header->ch_board_info); | |
1da177e4 | 732 | while (brd) { |
24ee0a6d JS |
733 | if (board_needs_cnode(brd->brd_type) && physical_node_map[brd->brd_nasid] < 0) { |
734 | sn_cnodeid_to_nasid[num_cnodes] = brd->brd_nasid; | |
735 | physical_node_map[brd->brd_nasid] = num_cnodes++; | |
736 | } | |
737 | brd = find_lboard_next(brd); | |
1da177e4 LT |
738 | } |
739 | } | |
1da177e4 LT |
740 | } |
741 | ||
742 | int | |
743 | nasid_slice_to_cpuid(int nasid, int slice) | |
744 | { | |
745 | long cpu; | |
71a5d027 | 746 | |
2fcc3db0 | 747 | for (cpu = 0; cpu < NR_CPUS; cpu++) |
9b48b466 DN |
748 | if (cpuid_to_nasid(cpu) == nasid && |
749 | cpuid_to_slice(cpu) == slice) | |
1da177e4 LT |
750 | return cpu; |
751 | ||
752 | return -1; | |
753 | } | |
a1cddb88 JS |
754 | |
755 | int sn_prom_feature_available(int id) | |
756 | { | |
757 | if (id >= BITS_PER_LONG * MAX_PROM_FEATURE_SETS) | |
758 | return 0; | |
759 | return test_bit(id, sn_prom_features); | |
760 | } | |
761 | EXPORT_SYMBOL(sn_prom_feature_available); | |
762 |