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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
e08e6c52 | 6 | * Copyright (C) 1999,2001-2006 Silicon Graphics, Inc. All rights reserved. |
1da177e4 LT |
7 | */ |
8 | ||
1da177e4 LT |
9 | #include <linux/module.h> |
10 | #include <linux/init.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/kdev_t.h> | |
14 | #include <linux/string.h> | |
894673ee | 15 | #include <linux/screen_info.h> |
1da177e4 LT |
16 | #include <linux/console.h> |
17 | #include <linux/timex.h> | |
18 | #include <linux/sched.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/serial.h> | |
22 | #include <linux/irq.h> | |
23 | #include <linux/bootmem.h> | |
24 | #include <linux/mmzone.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/acpi.h> | |
27 | #include <linux/compiler.h> | |
28 | #include <linux/sched.h> | |
29 | #include <linux/root_dev.h> | |
30 | #include <linux/nodemask.h> | |
c1298c5c | 31 | #include <linux/pm.h> |
ff51224c | 32 | #include <linux/efi.h> |
1da177e4 LT |
33 | |
34 | #include <asm/io.h> | |
35 | #include <asm/sal.h> | |
36 | #include <asm/machvec.h> | |
37 | #include <asm/system.h> | |
38 | #include <asm/processor.h> | |
a9f9de73 | 39 | #include <asm/vga.h> |
1da177e4 LT |
40 | #include <asm/sn/arch.h> |
41 | #include <asm/sn/addrs.h> | |
42 | #include <asm/sn/pda.h> | |
43 | #include <asm/sn/nodepda.h> | |
44 | #include <asm/sn/sn_cpuid.h> | |
45 | #include <asm/sn/simulator.h> | |
46 | #include <asm/sn/leds.h> | |
47 | #include <asm/sn/bte.h> | |
48 | #include <asm/sn/shub_mmr.h> | |
49 | #include <asm/sn/clksupport.h> | |
50 | #include <asm/sn/sn_sal.h> | |
51 | #include <asm/sn/geo.h> | |
a1cddb88 | 52 | #include <asm/sn/sn_feature_sets.h> |
1da177e4 LT |
53 | #include "xtalk/xwidgetdev.h" |
54 | #include "xtalk/hubdev.h" | |
55 | #include <asm/sn/klconfig.h> | |
56 | ||
57 | ||
58 | DEFINE_PER_CPU(struct pda_s, pda_percpu); | |
59 | ||
9b17e7e7 | 60 | #define MAX_PHYS_MEMORY (1UL << IA64_MAX_PHYS_BITS) /* Max physical address supported */ |
1da177e4 | 61 | |
1da177e4 LT |
62 | extern void bte_init_node(nodepda_t *, cnodeid_t); |
63 | ||
64 | extern void sn_timer_init(void); | |
65 | extern unsigned long last_time_offset; | |
66 | extern void (*ia64_mark_idle) (int); | |
67 | extern void snidle(int); | |
d6e56a2a | 68 | extern unsigned long long (*ia64_printk_clock)(void); |
1da177e4 LT |
69 | |
70 | unsigned long sn_rtc_cycles_per_second; | |
71 | EXPORT_SYMBOL(sn_rtc_cycles_per_second); | |
72 | ||
73 | DEFINE_PER_CPU(struct sn_hub_info_s, __sn_hub_info); | |
74 | EXPORT_PER_CPU_SYMBOL(__sn_hub_info); | |
75 | ||
c2a4969b | 76 | DEFINE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_COMPACT_NODES]); |
2e34f07f DN |
77 | EXPORT_PER_CPU_SYMBOL(__sn_cnodeid_to_nasid); |
78 | ||
9b48b466 DN |
79 | DEFINE_PER_CPU(struct nodepda_s *, __sn_nodepda); |
80 | EXPORT_PER_CPU_SYMBOL(__sn_nodepda); | |
81 | ||
1da177e4 LT |
82 | char sn_system_serial_number_string[128]; |
83 | EXPORT_SYMBOL(sn_system_serial_number_string); | |
84 | u64 sn_partition_serial_number; | |
85 | EXPORT_SYMBOL(sn_partition_serial_number); | |
86 | u8 sn_partition_id; | |
87 | EXPORT_SYMBOL(sn_partition_id); | |
88 | u8 sn_system_size; | |
89 | EXPORT_SYMBOL(sn_system_size); | |
90 | u8 sn_sharing_domain_size; | |
91 | EXPORT_SYMBOL(sn_sharing_domain_size); | |
92 | u8 sn_coherency_id; | |
93 | EXPORT_SYMBOL(sn_coherency_id); | |
94 | u8 sn_region_size; | |
95 | EXPORT_SYMBOL(sn_region_size); | |
71a5d027 | 96 | int sn_prom_type; /* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */ |
1da177e4 | 97 | |
24ee0a6d | 98 | short physical_node_map[MAX_NUMALINK_NODES]; |
a1cddb88 | 99 | static unsigned long sn_prom_features[MAX_PROM_FEATURE_SETS]; |
1da177e4 LT |
100 | |
101 | EXPORT_SYMBOL(physical_node_map); | |
102 | ||
24ee0a6d | 103 | int num_cnodes; |
1da177e4 LT |
104 | |
105 | static void sn_init_pdas(char **); | |
24ee0a6d | 106 | static void build_cnode_tables(void); |
1da177e4 LT |
107 | |
108 | static nodepda_t *nodepdaindr[MAX_COMPACT_NODES]; | |
109 | ||
110 | /* | |
111 | * The format of "screen_info" is strange, and due to early i386-setup | |
112 | * code. This is just enough to make the console code think we're on a | |
113 | * VGA color display. | |
114 | */ | |
115 | struct screen_info sn_screen_info = { | |
116 | .orig_x = 0, | |
117 | .orig_y = 0, | |
118 | .orig_video_mode = 3, | |
119 | .orig_video_cols = 80, | |
120 | .orig_video_ega_bx = 3, | |
121 | .orig_video_lines = 25, | |
122 | .orig_video_isVGA = 1, | |
123 | .orig_video_points = 16 | |
124 | }; | |
125 | ||
1da177e4 LT |
126 | /* |
127 | * This routine can only be used during init, since | |
128 | * smp_boot_data is an init data structure. | |
129 | * We have to use smp_boot_data.cpu_phys_id to find | |
130 | * the physical id of the processor because the normal | |
131 | * cpu_physical_id() relies on data structures that | |
132 | * may not be initialized yet. | |
133 | */ | |
134 | ||
135 | static int __init pxm_to_nasid(int pxm) | |
136 | { | |
137 | int i; | |
138 | int nid; | |
139 | ||
762834e8 | 140 | nid = pxm_to_node(pxm); |
1da177e4 LT |
141 | for (i = 0; i < num_node_memblks; i++) { |
142 | if (node_memblk[i].nid == nid) { | |
143 | return NASID_GET(node_memblk[i].start_paddr); | |
144 | } | |
145 | } | |
146 | return -1; | |
147 | } | |
148 | ||
149 | /** | |
150 | * early_sn_setup - early setup routine for SN platforms | |
151 | * | |
152 | * Sets up an initial console to aid debugging. Intended primarily | |
153 | * for bringup. See start_kernel() in init/main.c. | |
154 | */ | |
155 | ||
156 | void __init early_sn_setup(void) | |
157 | { | |
158 | efi_system_table_t *efi_systab; | |
159 | efi_config_table_t *config_tables; | |
160 | struct ia64_sal_systab *sal_systab; | |
161 | struct ia64_sal_desc_entry_point *ep; | |
162 | char *p; | |
163 | int i, j; | |
164 | ||
165 | /* | |
166 | * Parse enough of the SAL tables to locate the SAL entry point. Since, console | |
167 | * IO on SN2 is done via SAL calls, early_printk won't work without this. | |
168 | * | |
169 | * This code duplicates some of the ACPI table parsing that is in efi.c & sal.c. | |
170 | * Any changes to those file may have to be made hereas well. | |
171 | */ | |
172 | efi_systab = (efi_system_table_t *) __va(ia64_boot_param->efi_systab); | |
173 | config_tables = __va(efi_systab->tables); | |
174 | for (i = 0; i < efi_systab->nr_tables; i++) { | |
175 | if (efi_guidcmp(config_tables[i].guid, SAL_SYSTEM_TABLE_GUID) == | |
176 | 0) { | |
177 | sal_systab = __va(config_tables[i].table); | |
178 | p = (char *)(sal_systab + 1); | |
179 | for (j = 0; j < sal_systab->entry_count; j++) { | |
180 | if (*p == SAL_DESC_ENTRY_POINT) { | |
181 | ep = (struct ia64_sal_desc_entry_point | |
182 | *)p; | |
183 | ia64_sal_handler_init(__va | |
184 | (ep->sal_proc), | |
185 | __va(ep->gp)); | |
186 | return; | |
187 | } | |
188 | p += SAL_DESC_SIZE(*p); | |
189 | } | |
190 | } | |
191 | } | |
192 | /* Uh-oh, SAL not available?? */ | |
193 | printk(KERN_ERR "failed to find SAL entry point\n"); | |
194 | } | |
195 | ||
196 | extern int platform_intr_list[]; | |
2fcc3db0 | 197 | static int __initdata shub_1_1_found; |
1da177e4 LT |
198 | |
199 | /* | |
200 | * sn_check_for_wars | |
201 | * | |
202 | * Set flag for enabling shub specific wars | |
203 | */ | |
204 | ||
205 | static inline int __init is_shub_1_1(int nasid) | |
206 | { | |
207 | unsigned long id; | |
208 | int rev; | |
209 | ||
210 | if (is_shub2()) | |
211 | return 0; | |
212 | id = REMOTE_HUB_L(nasid, SH1_SHUB_ID); | |
213 | rev = (id & SH1_SHUB_ID_REVISION_MASK) >> SH1_SHUB_ID_REVISION_SHFT; | |
214 | return rev <= 2; | |
215 | } | |
216 | ||
217 | static void __init sn_check_for_wars(void) | |
218 | { | |
219 | int cnode; | |
220 | ||
221 | if (is_shub2()) { | |
222 | /* none yet */ | |
223 | } else { | |
224 | for_each_online_node(cnode) { | |
225 | if (is_shub_1_1(cnodeid_to_nasid(cnode))) | |
ff89bf3b | 226 | shub_1_1_found = 1; |
1da177e4 LT |
227 | } |
228 | } | |
229 | } | |
230 | ||
ff51224c MM |
231 | /* |
232 | * Scan the EFI PCDP table (if it exists) for an acceptable VGA console | |
233 | * output device. If one exists, pick it and set sn_legacy_{io,mem} to | |
234 | * reflect the bus offsets needed to address it. | |
235 | * | |
236 | * Since pcdp support in SN is not supported in the 2.4 kernel (or at least | |
237 | * the one lbs is based on) just declare the needed structs here. | |
238 | * | |
239 | * Reference spec http://www.dig64.org/specifications/DIG64_PCDPv20.pdf | |
240 | * | |
241 | * Returns 0 if no acceptable vga is found, !0 otherwise. | |
242 | * | |
243 | * Note: This stuff is duped here because Altix requires the PCDP to | |
244 | * locate a usable VGA device due to lack of proper ACPI support. Structures | |
245 | * could be used from drivers/firmware/pcdp.h, but it was decided that moving | |
246 | * this file to a more public location just for Altix use was undesireable. | |
247 | */ | |
248 | ||
249 | struct hcdp_uart_desc { | |
250 | u8 pad[45]; | |
251 | }; | |
252 | ||
253 | struct pcdp { | |
254 | u8 signature[4]; /* should be 'HCDP' */ | |
255 | u32 length; | |
256 | u8 rev; /* should be >=3 for pcdp, <3 for hcdp */ | |
257 | u8 sum; | |
258 | u8 oem_id[6]; | |
259 | u64 oem_tableid; | |
260 | u32 oem_rev; | |
261 | u32 creator_id; | |
262 | u32 creator_rev; | |
263 | u32 num_type0; | |
264 | struct hcdp_uart_desc uart[0]; /* num_type0 of these */ | |
265 | /* pcdp descriptors follow */ | |
266 | } __attribute__((packed)); | |
267 | ||
268 | struct pcdp_device_desc { | |
269 | u8 type; | |
270 | u8 primary; | |
271 | u16 length; | |
272 | u16 index; | |
273 | /* interconnect specific structure follows */ | |
274 | /* device specific structure follows that */ | |
275 | } __attribute__((packed)); | |
276 | ||
277 | struct pcdp_interface_pci { | |
278 | u8 type; /* 1 == pci */ | |
279 | u8 reserved; | |
280 | u16 length; | |
281 | u8 segment; | |
282 | u8 bus; | |
283 | u8 dev; | |
284 | u8 fun; | |
285 | u16 devid; | |
286 | u16 vendid; | |
287 | u32 acpi_interrupt; | |
288 | u64 mmio_tra; | |
289 | u64 ioport_tra; | |
290 | u8 flags; | |
291 | u8 translation; | |
292 | } __attribute__((packed)); | |
293 | ||
294 | struct pcdp_vga_device { | |
295 | u8 num_eas_desc; | |
296 | /* ACPI Extended Address Space Desc follows */ | |
297 | } __attribute__((packed)); | |
298 | ||
299 | /* from pcdp_device_desc.primary */ | |
300 | #define PCDP_PRIMARY_CONSOLE 0x01 | |
301 | ||
302 | /* from pcdp_device_desc.type */ | |
303 | #define PCDP_CONSOLE_INOUT 0x0 | |
304 | #define PCDP_CONSOLE_DEBUG 0x1 | |
305 | #define PCDP_CONSOLE_OUT 0x2 | |
306 | #define PCDP_CONSOLE_IN 0x3 | |
307 | #define PCDP_CONSOLE_TYPE_VGA 0x8 | |
308 | ||
309 | #define PCDP_CONSOLE_VGA (PCDP_CONSOLE_TYPE_VGA | PCDP_CONSOLE_OUT) | |
310 | ||
311 | /* from pcdp_interface_pci.type */ | |
312 | #define PCDP_IF_PCI 1 | |
313 | ||
314 | /* from pcdp_interface_pci.translation */ | |
315 | #define PCDP_PCI_TRANS_IOPORT 0x02 | |
316 | #define PCDP_PCI_TRANS_MMIO 0x01 | |
317 | ||
26d10915 | 318 | #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) |
ff51224c MM |
319 | static void |
320 | sn_scan_pcdp(void) | |
321 | { | |
322 | u8 *bp; | |
323 | struct pcdp *pcdp; | |
324 | struct pcdp_device_desc device; | |
325 | struct pcdp_interface_pci if_pci; | |
326 | extern struct efi efi; | |
327 | ||
b2c99e3c | 328 | if (efi.hcdp == EFI_INVALID_TABLE_ADDR) |
ff51224c MM |
329 | return; /* no hcdp/pcdp table */ |
330 | ||
b2c99e3c BH |
331 | pcdp = __va(efi.hcdp); |
332 | ||
ff51224c MM |
333 | if (pcdp->rev < 3) |
334 | return; /* only support PCDP (rev >= 3) */ | |
335 | ||
336 | for (bp = (u8 *)&pcdp->uart[pcdp->num_type0]; | |
337 | bp < (u8 *)pcdp + pcdp->length; | |
338 | bp += device.length) { | |
339 | memcpy(&device, bp, sizeof(device)); | |
340 | if (! (device.primary & PCDP_PRIMARY_CONSOLE)) | |
341 | continue; /* not primary console */ | |
342 | ||
343 | if (device.type != PCDP_CONSOLE_VGA) | |
344 | continue; /* not VGA descriptor */ | |
345 | ||
346 | memcpy(&if_pci, bp+sizeof(device), sizeof(if_pci)); | |
347 | if (if_pci.type != PCDP_IF_PCI) | |
348 | continue; /* not PCI interconnect */ | |
349 | ||
350 | if (if_pci.translation & PCDP_PCI_TRANS_IOPORT) | |
0bdfc190 | 351 | vga_console_iobase = if_pci.ioport_tra; |
ff51224c MM |
352 | |
353 | if (if_pci.translation & PCDP_PCI_TRANS_MMIO) | |
354 | vga_console_membase = | |
355 | if_pci.mmio_tra | __IA64_UNCACHED_OFFSET; | |
356 | ||
357 | break; /* once we find the primary, we're done */ | |
358 | } | |
359 | } | |
26d10915 | 360 | #endif |
ff51224c | 361 | |
d6e56a2a TL |
362 | static unsigned long sn2_rtc_initial; |
363 | ||
364 | static unsigned long long ia64_sn2_printk_clock(void) | |
365 | { | |
366 | unsigned long rtc_now = rtc_time(); | |
367 | ||
368 | return (rtc_now - sn2_rtc_initial) * | |
369 | (1000000000 / sn_rtc_cycles_per_second); | |
370 | } | |
371 | ||
1da177e4 LT |
372 | /** |
373 | * sn_setup - SN platform setup routine | |
374 | * @cmdline_p: kernel command line | |
375 | * | |
376 | * Handles platform setup for SN machines. This includes determining | |
377 | * the RTC frequency (via a SAL call), initializing secondary CPUs, and | |
378 | * setting up per-node data areas. The console is also initialized here. | |
379 | */ | |
380 | void __init sn_setup(char **cmdline_p) | |
381 | { | |
382 | long status, ticks_per_sec, drift; | |
283c7f6a | 383 | u32 version = sn_sal_rev(); |
1da177e4 LT |
384 | extern void sn_cpu_init(void); |
385 | ||
d6e56a2a | 386 | sn2_rtc_initial = rtc_time(); |
a1cddb88 JS |
387 | ia64_sn_plat_set_error_handling_features(); // obsolete |
388 | ia64_sn_set_os_feature(OSF_MCA_SLV_TO_OS_INIT_SLV); | |
389 | ia64_sn_set_os_feature(OSF_FEAT_LOG_SBES); | |
8ea6091f JK |
390 | /* |
391 | * Note: The calls to notify the PROM of ACPI and PCI Segment | |
392 | * support must be done prior to acpi_load_tables(), as | |
393 | * an ACPI capable PROM will rebuild the DSDT as result | |
394 | * of the call. | |
395 | */ | |
396 | ia64_sn_set_os_feature(OSF_PCISEGMENT_ENABLE); | |
397 | ia64_sn_set_os_feature(OSF_ACPI_ENABLE); | |
a1cddb88 | 398 | |
3fd0b2d9 JK |
399 | /* Load the new DSDT and SSDT tables into the global table list. */ |
400 | acpi_table_init(); | |
6872ec54 | 401 | |
a9f9de73 | 402 | #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) |
1da177e4 | 403 | /* |
ff51224c MM |
404 | * Handle SN vga console. |
405 | * | |
406 | * SN systems do not have enough ACPI table information | |
407 | * being passed from prom to identify VGA adapters and the legacy | |
408 | * addresses to access them. Until that is done, SN systems rely | |
409 | * on the PCDP table to identify the primary VGA console if one | |
410 | * exists. | |
411 | * | |
412 | * However, kernel PCDP support is optional, and even if it is built | |
413 | * into the kernel, it will not be used if the boot cmdline contains | |
414 | * console= directives. | |
415 | * | |
416 | * So, to work around this mess, we duplicate some of the PCDP code | |
417 | * here so that the primary VGA console (as defined by PCDP) will | |
418 | * work on SN systems even if a different console (e.g. serial) is | |
419 | * selected on the boot line (or CONFIG_EFI_PCDP is off). | |
1da177e4 | 420 | */ |
a9f9de73 | 421 | |
ff51224c MM |
422 | if (! vga_console_membase) |
423 | sn_scan_pcdp(); | |
424 | ||
8ea6091f JK |
425 | /* |
426 | * Setup legacy IO space. | |
427 | * vga_console_iobase maps to PCI IO Space address 0 on the | |
428 | * bus containing the VGA console. | |
429 | */ | |
430 | if (vga_console_iobase) { | |
0bdfc190 JK |
431 | io_space[0].mmio_base = |
432 | (unsigned long) ioremap(vga_console_iobase, 0); | |
8ea6091f JK |
433 | io_space[0].sparse = 0; |
434 | } | |
435 | ||
a9f9de73 MM |
436 | if (vga_console_membase) { |
437 | /* usable vga ... make tty0 the preferred default console */ | |
ff51224c MM |
438 | if (!strstr(*cmdline_p, "console=")) |
439 | add_preferred_console("tty", 0, NULL); | |
a9f9de73 | 440 | } else { |
1da177e4 | 441 | printk(KERN_DEBUG "SGI: Disabling VGA console\n"); |
ff51224c MM |
442 | if (!strstr(*cmdline_p, "console=")) |
443 | add_preferred_console("ttySG", 0, NULL); | |
1da177e4 LT |
444 | #ifdef CONFIG_DUMMY_CONSOLE |
445 | conswitchp = &dummy_con; | |
446 | #else | |
447 | conswitchp = NULL; | |
448 | #endif /* CONFIG_DUMMY_CONSOLE */ | |
449 | } | |
450 | #endif /* def(CONFIG_VT) && def(CONFIG_VGA_CONSOLE) */ | |
451 | ||
452 | MAX_DMA_ADDRESS = PAGE_OFFSET + MAX_PHYS_MEMORY; | |
453 | ||
24ee0a6d JS |
454 | /* |
455 | * Build the tables for managing cnodes. | |
456 | */ | |
457 | build_cnode_tables(); | |
1da177e4 | 458 | |
1da177e4 LT |
459 | status = |
460 | ia64_sal_freq_base(SAL_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec, | |
461 | &drift); | |
462 | if (status != 0 || ticks_per_sec < 100000) { | |
463 | printk(KERN_WARNING | |
464 | "unable to determine platform RTC clock frequency, guessing.\n"); | |
465 | /* PROM gives wrong value for clock freq. so guess */ | |
466 | sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; | |
467 | } else | |
468 | sn_rtc_cycles_per_second = ticks_per_sec; | |
469 | ||
470 | platform_intr_list[ACPI_INTERRUPT_CPEI] = IA64_CPE_VECTOR; | |
471 | ||
d6e56a2a TL |
472 | ia64_printk_clock = ia64_sn2_printk_clock; |
473 | ||
d6e56a2a TL |
474 | printk("SGI SAL version %x.%02x\n", version >> 8, version & 0x00FF); |
475 | ||
1da177e4 LT |
476 | /* |
477 | * we set the default root device to /dev/hda | |
478 | * to make simulation easy | |
479 | */ | |
480 | ROOT_DEV = Root_HDA1; | |
481 | ||
482 | /* | |
483 | * Create the PDAs and NODEPDAs for all the cpus. | |
484 | */ | |
485 | sn_init_pdas(cmdline_p); | |
486 | ||
487 | ia64_mark_idle = &snidle; | |
488 | ||
71a5d027 | 489 | /* |
1da177e4 LT |
490 | * For the bootcpu, we do this here. All other cpus will make the |
491 | * call as part of cpu_init in slave cpu initialization. | |
492 | */ | |
493 | sn_cpu_init(); | |
494 | ||
495 | #ifdef CONFIG_SMP | |
496 | init_smp_config(); | |
497 | #endif | |
498 | screen_info = sn_screen_info; | |
499 | ||
500 | sn_timer_init(); | |
c1298c5c AY |
501 | |
502 | /* | |
503 | * set pm_power_off to a SAL call to allow | |
504 | * sn machines to power off. The SAL call can be replaced | |
505 | * by an ACPI interface call when ACPI is fully implemented | |
506 | * for sn. | |
507 | */ | |
508 | pm_power_off = ia64_sn_power_down; | |
e08e6c52 | 509 | current->thread.flags |= IA64_THREAD_MIGRATION; |
1da177e4 LT |
510 | } |
511 | ||
512 | /** | |
513 | * sn_init_pdas - setup node data areas | |
514 | * | |
515 | * One time setup for Node Data Area. Called by sn_setup(). | |
516 | */ | |
517 | static void __init sn_init_pdas(char **cmdline_p) | |
518 | { | |
519 | cnodeid_t cnode; | |
520 | ||
1da177e4 LT |
521 | /* |
522 | * Allocate & initalize the nodepda for each node. | |
523 | */ | |
524 | for_each_online_node(cnode) { | |
525 | nodepdaindr[cnode] = | |
526 | alloc_bootmem_node(NODE_DATA(cnode), sizeof(nodepda_t)); | |
527 | memset(nodepdaindr[cnode], 0, sizeof(nodepda_t)); | |
71a5d027 | 528 | memset(nodepdaindr[cnode]->phys_cpuid, -1, |
1da177e4 | 529 | sizeof(nodepdaindr[cnode]->phys_cpuid)); |
470ceb05 | 530 | spin_lock_init(&nodepdaindr[cnode]->ptc_lock); |
1da177e4 LT |
531 | } |
532 | ||
533 | /* | |
534 | * Allocate & initialize nodepda for TIOs. For now, put them on node 0. | |
535 | */ | |
24ee0a6d | 536 | for (cnode = num_online_nodes(); cnode < num_cnodes; cnode++) { |
1da177e4 LT |
537 | nodepdaindr[cnode] = |
538 | alloc_bootmem_node(NODE_DATA(0), sizeof(nodepda_t)); | |
539 | memset(nodepdaindr[cnode], 0, sizeof(nodepda_t)); | |
540 | } | |
541 | ||
542 | /* | |
543 | * Now copy the array of nodepda pointers to each nodepda. | |
544 | */ | |
24ee0a6d | 545 | for (cnode = 0; cnode < num_cnodes; cnode++) |
1da177e4 LT |
546 | memcpy(nodepdaindr[cnode]->pernode_pdaindr, nodepdaindr, |
547 | sizeof(nodepdaindr)); | |
548 | ||
549 | /* | |
550 | * Set up IO related platform-dependent nodepda fields. | |
551 | * The following routine actually sets up the hubinfo struct | |
552 | * in nodepda. | |
553 | */ | |
554 | for_each_online_node(cnode) { | |
555 | bte_init_node(nodepdaindr[cnode], cnode); | |
556 | } | |
557 | ||
558 | /* | |
71a5d027 | 559 | * Initialize the per node hubdev. This includes IO Nodes and |
1da177e4 LT |
560 | * headless/memless nodes. |
561 | */ | |
24ee0a6d | 562 | for (cnode = 0; cnode < num_cnodes; cnode++) { |
1da177e4 LT |
563 | hubdev_init_node(nodepdaindr[cnode], cnode); |
564 | } | |
565 | } | |
566 | ||
567 | /** | |
568 | * sn_cpu_init - initialize per-cpu data areas | |
569 | * @cpuid: cpuid of the caller | |
570 | * | |
571 | * Called during cpu initialization on each cpu as it starts. | |
572 | * Currently, initializes the per-cpu data area for SNIA. | |
573 | * Also sets up a few fields in the nodepda. Also known as | |
574 | * platform_cpu_init() by the ia64 machvec code. | |
575 | */ | |
38f5745c | 576 | void __cpuinit sn_cpu_init(void) |
1da177e4 LT |
577 | { |
578 | int cpuid; | |
579 | int cpuphyid; | |
580 | int nasid; | |
581 | int subnode; | |
582 | int slice; | |
583 | int cnode; | |
584 | int i; | |
adf142e3 | 585 | static int wars_have_been_checked, set_cpu0_number; |
1da177e4 | 586 | |
9d56d878 JS |
587 | cpuid = smp_processor_id(); |
588 | if (cpuid == 0 && IS_MEDUSA()) { | |
71a5d027 JS |
589 | if (ia64_sn_is_fake_prom()) |
590 | sn_prom_type = 2; | |
591 | else | |
592 | sn_prom_type = 1; | |
2fcc3db0 JS |
593 | printk(KERN_INFO "Running on medusa with %s PROM\n", |
594 | (sn_prom_type == 1) ? "real" : "fake"); | |
71a5d027 JS |
595 | } |
596 | ||
1da177e4 | 597 | memset(pda, 0, sizeof(pda)); |
2fcc3db0 JS |
598 | if (ia64_sn_get_sn_info(0, &sn_hub_info->shub2, |
599 | &sn_hub_info->nasid_bitmask, | |
600 | &sn_hub_info->nasid_shift, | |
601 | &sn_system_size, &sn_sharing_domain_size, | |
602 | &sn_partition_id, &sn_coherency_id, | |
603 | &sn_region_size)) | |
1da177e4 LT |
604 | BUG(); |
605 | sn_hub_info->as_shift = sn_hub_info->nasid_shift - 2; | |
606 | ||
9d56d878 JS |
607 | /* |
608 | * Don't check status. The SAL call is not supported on all PROMs | |
609 | * but a failure is harmless. | |
adf142e3 JL |
610 | * Architechtuallly, cpu_init is always called twice on cpu 0. We |
611 | * should set cpu_number on cpu 0 once. | |
9d56d878 | 612 | */ |
adf142e3 JL |
613 | if (cpuid == 0) { |
614 | if (!set_cpu0_number) { | |
615 | (void) ia64_sn_set_cpu_number(cpuid); | |
616 | set_cpu0_number = 1; | |
617 | } | |
618 | } else | |
619 | (void) ia64_sn_set_cpu_number(cpuid); | |
9d56d878 | 620 | |
1da177e4 LT |
621 | /* |
622 | * The boot cpu makes this call again after platform initialization is | |
623 | * complete. | |
624 | */ | |
625 | if (nodepdaindr[0] == NULL) | |
626 | return; | |
627 | ||
a1cddb88 JS |
628 | for (i = 0; i < MAX_PROM_FEATURE_SETS; i++) |
629 | if (ia64_sn_get_prom_feature_set(i, &sn_prom_features[i]) != 0) | |
630 | break; | |
631 | ||
1da177e4 LT |
632 | cpuphyid = get_sapicid(); |
633 | ||
634 | if (ia64_sn_get_sapic_info(cpuphyid, &nasid, &subnode, &slice)) | |
635 | BUG(); | |
636 | ||
637 | for (i=0; i < MAX_NUMNODES; i++) { | |
638 | if (nodepdaindr[i]) { | |
639 | nodepdaindr[i]->phys_cpuid[cpuid].nasid = nasid; | |
640 | nodepdaindr[i]->phys_cpuid[cpuid].slice = slice; | |
641 | nodepdaindr[i]->phys_cpuid[cpuid].subnode = subnode; | |
642 | } | |
643 | } | |
644 | ||
645 | cnode = nasid_to_cnodeid(nasid); | |
646 | ||
9b48b466 DN |
647 | sn_nodepda = nodepdaindr[cnode]; |
648 | ||
1da177e4 LT |
649 | pda->led_address = |
650 | (typeof(pda->led_address)) (LED0 + (slice << LED_CPU_SHIFT)); | |
651 | pda->led_state = LED_ALWAYS_SET; | |
652 | pda->hb_count = HZ / 2; | |
653 | pda->hb_state = 0; | |
654 | pda->idle_flag = 0; | |
655 | ||
656 | if (cpuid != 0) { | |
2e34f07f DN |
657 | /* copy cpu 0's sn_cnodeid_to_nasid table to this cpu's */ |
658 | memcpy(sn_cnodeid_to_nasid, | |
659 | (&per_cpu(__sn_cnodeid_to_nasid, 0)), | |
660 | sizeof(__ia64_per_cpu_var(__sn_cnodeid_to_nasid))); | |
1da177e4 LT |
661 | } |
662 | ||
663 | /* | |
664 | * Check for WARs. | |
665 | * Only needs to be done once, on BSP. | |
2e34f07f DN |
666 | * Has to be done after loop above, because it uses this cpu's |
667 | * sn_cnodeid_to_nasid table which was just initialized if this | |
668 | * isn't cpu 0. | |
1da177e4 LT |
669 | * Has to be done before assignment below. |
670 | */ | |
671 | if (!wars_have_been_checked) { | |
672 | sn_check_for_wars(); | |
673 | wars_have_been_checked = 1; | |
674 | } | |
675 | sn_hub_info->shub_1_1_found = shub_1_1_found; | |
676 | ||
677 | /* | |
678 | * Set up addresses of PIO/MEM write status registers. | |
679 | */ | |
680 | { | |
681 | u64 pio1[] = {SH1_PIO_WRITE_STATUS_0, 0, SH1_PIO_WRITE_STATUS_1, 0}; | |
2fdbb590 JS |
682 | u64 pio2[] = {SH2_PIO_WRITE_STATUS_0, SH2_PIO_WRITE_STATUS_2, |
683 | SH2_PIO_WRITE_STATUS_1, SH2_PIO_WRITE_STATUS_3}; | |
1da177e4 LT |
684 | u64 *pio; |
685 | pio = is_shub1() ? pio1 : pio2; | |
e08e6c52 BC |
686 | pda->pio_write_status_addr = |
687 | (volatile unsigned long *)GLOBAL_MMR_ADDR(nasid, pio[slice]); | |
1da177e4 LT |
688 | pda->pio_write_status_val = is_shub1() ? SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK : 0; |
689 | } | |
690 | ||
691 | /* | |
692 | * WAR addresses for SHUB 1.x. | |
693 | */ | |
694 | if (local_node_data->active_cpu_count++ == 0 && is_shub1()) { | |
695 | int buddy_nasid; | |
696 | buddy_nasid = | |
697 | cnodeid_to_nasid(numa_node_id() == | |
698 | num_online_nodes() - 1 ? 0 : numa_node_id() + 1); | |
699 | pda->pio_shub_war_cam_addr = | |
700 | (volatile unsigned long *)GLOBAL_MMR_ADDR(nasid, | |
701 | SH1_PI_CAM_CONTROL); | |
702 | } | |
703 | } | |
704 | ||
705 | /* | |
24ee0a6d | 706 | * Build tables for converting between NASIDs and cnodes. |
1da177e4 | 707 | */ |
24ee0a6d JS |
708 | static inline int __init board_needs_cnode(int type) |
709 | { | |
710 | return (type == KLTYPE_SNIA || type == KLTYPE_TIO); | |
711 | } | |
1da177e4 | 712 | |
24ee0a6d | 713 | void __init build_cnode_tables(void) |
1da177e4 | 714 | { |
24ee0a6d JS |
715 | int nasid; |
716 | int node; | |
1da177e4 LT |
717 | lboard_t *brd; |
718 | ||
24ee0a6d JS |
719 | memset(physical_node_map, -1, sizeof(physical_node_map)); |
720 | memset(sn_cnodeid_to_nasid, -1, | |
721 | sizeof(__ia64_per_cpu_var(__sn_cnodeid_to_nasid))); | |
1da177e4 | 722 | |
24ee0a6d JS |
723 | /* |
724 | * First populate the tables with C/M bricks. This ensures that | |
725 | * cnode == node for all C & M bricks. | |
726 | */ | |
727 | for_each_online_node(node) { | |
762834e8 | 728 | nasid = pxm_to_nasid(node_to_pxm(node)); |
24ee0a6d JS |
729 | sn_cnodeid_to_nasid[node] = nasid; |
730 | physical_node_map[nasid] = node; | |
1da177e4 LT |
731 | } |
732 | ||
24ee0a6d JS |
733 | /* |
734 | * num_cnodes is total number of C/M/TIO bricks. Because of the 256 node | |
735 | * limit on the number of nodes, we can't use the generic node numbers | |
736 | * for this. Note that num_cnodes is incremented below as TIOs or | |
737 | * headless/memoryless nodes are discovered. | |
738 | */ | |
739 | num_cnodes = num_online_nodes(); | |
1da177e4 | 740 | |
24ee0a6d JS |
741 | /* fakeprom does not support klgraph */ |
742 | if (IS_RUNNING_ON_FAKE_PROM()) | |
743 | return; | |
1da177e4 | 744 | |
24ee0a6d JS |
745 | /* Find TIOs & headless/memoryless nodes and add them to the tables */ |
746 | for_each_online_node(node) { | |
747 | kl_config_hdr_t *klgraph_header; | |
748 | nasid = cnodeid_to_nasid(node); | |
2fcc3db0 JS |
749 | klgraph_header = ia64_sn_get_klconfig_addr(nasid); |
750 | if (klgraph_header == NULL) | |
24ee0a6d JS |
751 | BUG(); |
752 | brd = NODE_OFFSET_TO_LBOARD(nasid, klgraph_header->ch_board_info); | |
1da177e4 | 753 | while (brd) { |
24ee0a6d JS |
754 | if (board_needs_cnode(brd->brd_type) && physical_node_map[brd->brd_nasid] < 0) { |
755 | sn_cnodeid_to_nasid[num_cnodes] = brd->brd_nasid; | |
756 | physical_node_map[brd->brd_nasid] = num_cnodes++; | |
757 | } | |
758 | brd = find_lboard_next(brd); | |
1da177e4 LT |
759 | } |
760 | } | |
1da177e4 LT |
761 | } |
762 | ||
763 | int | |
764 | nasid_slice_to_cpuid(int nasid, int slice) | |
765 | { | |
766 | long cpu; | |
71a5d027 | 767 | |
2fcc3db0 | 768 | for (cpu = 0; cpu < NR_CPUS; cpu++) |
9b48b466 DN |
769 | if (cpuid_to_nasid(cpu) == nasid && |
770 | cpuid_to_slice(cpu) == slice) | |
1da177e4 LT |
771 | return cpu; |
772 | ||
773 | return -1; | |
774 | } | |
a1cddb88 JS |
775 | |
776 | int sn_prom_feature_available(int id) | |
777 | { | |
778 | if (id >= BITS_PER_LONG * MAX_PROM_FEATURE_SETS) | |
779 | return 0; | |
780 | return test_bit(id, sn_prom_features); | |
781 | } | |
a7956113 ZN |
782 | |
783 | void | |
784 | sn_kernel_launch_event(void) | |
785 | { | |
786 | /* ignore status until we understand possible failure, if any*/ | |
787 | if (ia64_sn_kernel_launch_event()) | |
788 | printk(KERN_ERR "KEXEC is not supported in this PROM, Please update the PROM.\n"); | |
789 | } | |
a1cddb88 JS |
790 | EXPORT_SYMBOL(sn_prom_feature_available); |
791 |