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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * pci.c - Low-Level PCI Access in IA-64 | |
3 | * | |
4 | * Derived from bios32.c of i386 tree. | |
5 | * | |
6 | * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P. | |
7 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
8 | * Bjorn Helgaas <bjorn.helgaas@hp.com> | |
9 | * Copyright (C) 2004 Silicon Graphics, Inc. | |
10 | * | |
11 | * Note: Above list of copyright holders is incomplete... | |
12 | */ | |
1da177e4 LT |
13 | |
14 | #include <linux/acpi.h> | |
15 | #include <linux/types.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/slab.h> | |
1da177e4 | 21 | #include <linux/spinlock.h> |
175add19 | 22 | #include <linux/bootmem.h> |
1da177e4 LT |
23 | |
24 | #include <asm/machvec.h> | |
25 | #include <asm/page.h> | |
1da177e4 LT |
26 | #include <asm/system.h> |
27 | #include <asm/io.h> | |
28 | #include <asm/sal.h> | |
29 | #include <asm/smp.h> | |
30 | #include <asm/irq.h> | |
31 | #include <asm/hw_irq.h> | |
32 | ||
1da177e4 LT |
33 | /* |
34 | * Low-level SAL-based PCI configuration access functions. Note that SAL | |
35 | * calls are already serialized (via sal_lock), so we don't need another | |
36 | * synchronization mechanism here. | |
37 | */ | |
38 | ||
39 | #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \ | |
40 | (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg)) | |
41 | ||
42 | /* SAL 3.2 adds support for extended config space. */ | |
43 | ||
44 | #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \ | |
45 | (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg)) | |
46 | ||
b6ce068a | 47 | int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn, |
1da177e4 LT |
48 | int reg, int len, u32 *value) |
49 | { | |
50 | u64 addr, data = 0; | |
51 | int mode, result; | |
52 | ||
53 | if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) | |
54 | return -EINVAL; | |
55 | ||
56 | if ((seg | reg) <= 255) { | |
57 | addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); | |
58 | mode = 0; | |
adcd7403 | 59 | } else if (sal_revision >= SAL_VERSION_CODE(3,2)) { |
1da177e4 LT |
60 | addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); |
61 | mode = 1; | |
adcd7403 MW |
62 | } else { |
63 | return -EINVAL; | |
1da177e4 | 64 | } |
adcd7403 | 65 | |
1da177e4 LT |
66 | result = ia64_sal_pci_config_read(addr, mode, len, &data); |
67 | if (result != 0) | |
68 | return -EINVAL; | |
69 | ||
70 | *value = (u32) data; | |
71 | return 0; | |
72 | } | |
73 | ||
b6ce068a | 74 | int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn, |
1da177e4 LT |
75 | int reg, int len, u32 value) |
76 | { | |
77 | u64 addr; | |
78 | int mode, result; | |
79 | ||
80 | if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) | |
81 | return -EINVAL; | |
82 | ||
83 | if ((seg | reg) <= 255) { | |
84 | addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); | |
85 | mode = 0; | |
adcd7403 | 86 | } else if (sal_revision >= SAL_VERSION_CODE(3,2)) { |
1da177e4 LT |
87 | addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); |
88 | mode = 1; | |
adcd7403 MW |
89 | } else { |
90 | return -EINVAL; | |
1da177e4 LT |
91 | } |
92 | result = ia64_sal_pci_config_write(addr, mode, len, value); | |
93 | if (result != 0) | |
94 | return -EINVAL; | |
95 | return 0; | |
96 | } | |
97 | ||
b6ce068a MW |
98 | static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, |
99 | int size, u32 *value) | |
1da177e4 | 100 | { |
b6ce068a | 101 | return raw_pci_read(pci_domain_nr(bus), bus->number, |
1da177e4 LT |
102 | devfn, where, size, value); |
103 | } | |
104 | ||
b6ce068a MW |
105 | static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, |
106 | int size, u32 value) | |
1da177e4 | 107 | { |
b6ce068a | 108 | return raw_pci_write(pci_domain_nr(bus), bus->number, |
1da177e4 LT |
109 | devfn, where, size, value); |
110 | } | |
111 | ||
112 | struct pci_ops pci_root_ops = { | |
113 | .read = pci_read, | |
114 | .write = pci_write, | |
115 | }; | |
116 | ||
1da177e4 LT |
117 | /* Called by ACPI when it finds a new root bus. */ |
118 | ||
119 | static struct pci_controller * __devinit | |
120 | alloc_pci_controller (int seg) | |
121 | { | |
122 | struct pci_controller *controller; | |
123 | ||
52fd9108 | 124 | controller = kzalloc(sizeof(*controller), GFP_KERNEL); |
1da177e4 LT |
125 | if (!controller) |
126 | return NULL; | |
127 | ||
1da177e4 | 128 | controller->segment = seg; |
514604c6 | 129 | controller->node = -1; |
1da177e4 LT |
130 | return controller; |
131 | } | |
132 | ||
4f41d5a4 BH |
133 | struct pci_root_info { |
134 | struct pci_controller *controller; | |
135 | char *name; | |
136 | }; | |
137 | ||
138 | static unsigned int | |
139 | new_space (u64 phys_base, int sparse) | |
1da177e4 | 140 | { |
4f41d5a4 | 141 | u64 mmio_base; |
1da177e4 LT |
142 | int i; |
143 | ||
4f41d5a4 BH |
144 | if (phys_base == 0) |
145 | return 0; /* legacy I/O port space */ | |
1da177e4 | 146 | |
4f41d5a4 | 147 | mmio_base = (u64) ioremap(phys_base, 0); |
1da177e4 | 148 | for (i = 0; i < num_io_spaces; i++) |
4f41d5a4 | 149 | if (io_space[i].mmio_base == mmio_base && |
1da177e4 | 150 | io_space[i].sparse == sparse) |
4f41d5a4 | 151 | return i; |
1da177e4 LT |
152 | |
153 | if (num_io_spaces == MAX_IO_SPACES) { | |
4f41d5a4 BH |
154 | printk(KERN_ERR "PCI: Too many IO port spaces " |
155 | "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES); | |
1da177e4 LT |
156 | return ~0; |
157 | } | |
158 | ||
159 | i = num_io_spaces++; | |
4f41d5a4 | 160 | io_space[i].mmio_base = mmio_base; |
1da177e4 LT |
161 | io_space[i].sparse = sparse; |
162 | ||
4f41d5a4 BH |
163 | return i; |
164 | } | |
165 | ||
166 | static u64 __devinit | |
167 | add_io_space (struct pci_root_info *info, struct acpi_resource_address64 *addr) | |
168 | { | |
169 | struct resource *resource; | |
170 | char *name; | |
e088a4ad | 171 | unsigned long base, min, max, base_port; |
4f41d5a4 BH |
172 | unsigned int sparse = 0, space_nr, len; |
173 | ||
174 | resource = kzalloc(sizeof(*resource), GFP_KERNEL); | |
175 | if (!resource) { | |
176 | printk(KERN_ERR "PCI: No memory for %s I/O port space\n", | |
177 | info->name); | |
178 | goto out; | |
179 | } | |
180 | ||
181 | len = strlen(info->name) + 32; | |
182 | name = kzalloc(len, GFP_KERNEL); | |
183 | if (!name) { | |
184 | printk(KERN_ERR "PCI: No memory for %s I/O port space name\n", | |
185 | info->name); | |
186 | goto free_resource; | |
187 | } | |
188 | ||
50eca3eb | 189 | min = addr->minimum; |
4f41d5a4 | 190 | max = min + addr->address_length - 1; |
0897831b | 191 | if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION) |
4f41d5a4 BH |
192 | sparse = 1; |
193 | ||
50eca3eb | 194 | space_nr = new_space(addr->translation_offset, sparse); |
4f41d5a4 BH |
195 | if (space_nr == ~0) |
196 | goto free_name; | |
197 | ||
198 | base = __pa(io_space[space_nr].mmio_base); | |
199 | base_port = IO_SPACE_BASE(space_nr); | |
200 | snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name, | |
201 | base_port + min, base_port + max); | |
202 | ||
203 | /* | |
204 | * The SDM guarantees the legacy 0-64K space is sparse, but if the | |
205 | * mapping is done by the processor (not the bridge), ACPI may not | |
206 | * mark it as sparse. | |
207 | */ | |
208 | if (space_nr == 0) | |
209 | sparse = 1; | |
210 | ||
211 | resource->name = name; | |
212 | resource->flags = IORESOURCE_MEM; | |
213 | resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min); | |
214 | resource->end = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max); | |
215 | insert_resource(&iomem_resource, resource); | |
216 | ||
217 | return base_port; | |
218 | ||
219 | free_name: | |
220 | kfree(name); | |
221 | free_resource: | |
222 | kfree(resource); | |
223 | out: | |
224 | return ~0; | |
1da177e4 LT |
225 | } |
226 | ||
463eb297 BH |
227 | static acpi_status __devinit resource_to_window(struct acpi_resource *resource, |
228 | struct acpi_resource_address64 *addr) | |
229 | { | |
230 | acpi_status status; | |
231 | ||
232 | /* | |
233 | * We're only interested in _CRS descriptors that are | |
234 | * - address space descriptors for memory or I/O space | |
235 | * - non-zero size | |
236 | * - producers, i.e., the address space is routed downstream, | |
237 | * not consumed by the bridge itself | |
238 | */ | |
239 | status = acpi_resource_to_address64(resource, addr); | |
240 | if (ACPI_SUCCESS(status) && | |
241 | (addr->resource_type == ACPI_MEMORY_RANGE || | |
242 | addr->resource_type == ACPI_IO_RANGE) && | |
243 | addr->address_length && | |
244 | addr->producer_consumer == ACPI_PRODUCER) | |
245 | return AE_OK; | |
246 | ||
247 | return AE_ERROR; | |
248 | } | |
249 | ||
1da177e4 LT |
250 | static acpi_status __devinit |
251 | count_window (struct acpi_resource *resource, void *data) | |
252 | { | |
253 | unsigned int *windows = (unsigned int *) data; | |
254 | struct acpi_resource_address64 addr; | |
255 | acpi_status status; | |
256 | ||
463eb297 | 257 | status = resource_to_window(resource, &addr); |
1da177e4 | 258 | if (ACPI_SUCCESS(status)) |
463eb297 | 259 | (*windows)++; |
1da177e4 LT |
260 | |
261 | return AE_OK; | |
262 | } | |
263 | ||
1da177e4 LT |
264 | static __devinit acpi_status add_window(struct acpi_resource *res, void *data) |
265 | { | |
266 | struct pci_root_info *info = data; | |
267 | struct pci_window *window; | |
268 | struct acpi_resource_address64 addr; | |
269 | acpi_status status; | |
270 | unsigned long flags, offset = 0; | |
271 | struct resource *root; | |
272 | ||
463eb297 BH |
273 | /* Return AE_OK for non-window resources to keep scanning for more */ |
274 | status = resource_to_window(res, &addr); | |
1da177e4 LT |
275 | if (!ACPI_SUCCESS(status)) |
276 | return AE_OK; | |
277 | ||
1da177e4 LT |
278 | if (addr.resource_type == ACPI_MEMORY_RANGE) { |
279 | flags = IORESOURCE_MEM; | |
280 | root = &iomem_resource; | |
50eca3eb | 281 | offset = addr.translation_offset; |
1da177e4 LT |
282 | } else if (addr.resource_type == ACPI_IO_RANGE) { |
283 | flags = IORESOURCE_IO; | |
284 | root = &ioport_resource; | |
4f41d5a4 | 285 | offset = add_io_space(info, &addr); |
1da177e4 LT |
286 | if (offset == ~0) |
287 | return AE_OK; | |
288 | } else | |
289 | return AE_OK; | |
290 | ||
291 | window = &info->controller->window[info->controller->windows++]; | |
292 | window->resource.name = info->name; | |
293 | window->resource.flags = flags; | |
50eca3eb | 294 | window->resource.start = addr.minimum + offset; |
4f41d5a4 | 295 | window->resource.end = window->resource.start + addr.address_length - 1; |
1da177e4 LT |
296 | window->resource.child = NULL; |
297 | window->offset = offset; | |
298 | ||
299 | if (insert_resource(root, &window->resource)) { | |
e088a4ad | 300 | printk(KERN_ERR "alloc 0x%llx-0x%llx from %s for %s failed\n", |
1da177e4 LT |
301 | window->resource.start, window->resource.end, |
302 | root->name, info->name); | |
303 | } | |
304 | ||
305 | return AE_OK; | |
306 | } | |
307 | ||
308 | static void __devinit | |
309 | pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl) | |
310 | { | |
311 | int i, j; | |
312 | ||
313 | j = 0; | |
314 | for (i = 0; i < ctrl->windows; i++) { | |
315 | struct resource *res = &ctrl->window[i].resource; | |
316 | /* HP's firmware has a hack to work around a Windows bug. | |
317 | * Ignore these tiny memory ranges */ | |
318 | if ((res->flags & IORESOURCE_MEM) && | |
319 | (res->end - res->start < 16)) | |
320 | continue; | |
321 | if (j >= PCI_BUS_NUM_RESOURCES) { | |
e088a4ad MW |
322 | printk("Ignoring range [%#llx-%#llx] (%lx)\n", |
323 | res->start, res->end, res->flags); | |
1da177e4 LT |
324 | continue; |
325 | } | |
326 | bus->resource[j++] = res; | |
327 | } | |
328 | } | |
329 | ||
330 | struct pci_bus * __devinit | |
331 | pci_acpi_scan_root(struct acpi_device *device, int domain, int bus) | |
332 | { | |
1da177e4 LT |
333 | struct pci_controller *controller; |
334 | unsigned int windows = 0; | |
335 | struct pci_bus *pbus; | |
336 | char *name; | |
514604c6 | 337 | int pxm; |
1da177e4 LT |
338 | |
339 | controller = alloc_pci_controller(domain); | |
340 | if (!controller) | |
341 | goto out1; | |
342 | ||
343 | controller->acpi_handle = device->handle; | |
344 | ||
514604c6 CL |
345 | pxm = acpi_get_pxm(controller->acpi_handle); |
346 | #ifdef CONFIG_NUMA | |
347 | if (pxm >= 0) | |
762834e8 | 348 | controller->node = pxm_to_node(pxm); |
514604c6 CL |
349 | #endif |
350 | ||
1da177e4 LT |
351 | acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window, |
352 | &windows); | |
a66aa704 | 353 | if (windows) { |
8a20fd52 TL |
354 | struct pci_root_info info; |
355 | ||
a66aa704 KK |
356 | controller->window = |
357 | kmalloc_node(sizeof(*controller->window) * windows, | |
358 | GFP_KERNEL, controller->node); | |
359 | if (!controller->window) | |
360 | goto out2; | |
1da177e4 | 361 | |
8a20fd52 TL |
362 | name = kmalloc(16, GFP_KERNEL); |
363 | if (!name) | |
364 | goto out3; | |
1da177e4 | 365 | |
8a20fd52 TL |
366 | sprintf(name, "PCI Bus %04x:%02x", domain, bus); |
367 | info.controller = controller; | |
368 | info.name = name; | |
369 | acpi_walk_resources(device->handle, METHOD_NAME__CRS, | |
370 | add_window, &info); | |
371 | } | |
b87e81e5 | 372 | /* |
373 | * See arch/x86/pci/acpi.c. | |
374 | * The desired pci bus might already be scanned in a quirk. We | |
375 | * should handle the case here, but it appears that IA64 hasn't | |
376 | * such quirk. So we just ignore the case now. | |
377 | */ | |
c431ada4 | 378 | pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller); |
1da177e4 LT |
379 | |
380 | return pbus; | |
381 | ||
382 | out3: | |
383 | kfree(controller->window); | |
384 | out2: | |
385 | kfree(controller); | |
386 | out1: | |
387 | return NULL; | |
388 | } | |
389 | ||
390 | void pcibios_resource_to_bus(struct pci_dev *dev, | |
391 | struct pci_bus_region *region, struct resource *res) | |
392 | { | |
393 | struct pci_controller *controller = PCI_CONTROLLER(dev); | |
394 | unsigned long offset = 0; | |
395 | int i; | |
396 | ||
397 | for (i = 0; i < controller->windows; i++) { | |
398 | struct pci_window *window = &controller->window[i]; | |
399 | if (!(window->resource.flags & res->flags)) | |
400 | continue; | |
401 | if (window->resource.start > res->start) | |
402 | continue; | |
403 | if (window->resource.end < res->end) | |
404 | continue; | |
405 | offset = window->offset; | |
406 | break; | |
407 | } | |
408 | ||
409 | region->start = res->start - offset; | |
410 | region->end = res->end - offset; | |
411 | } | |
412 | EXPORT_SYMBOL(pcibios_resource_to_bus); | |
413 | ||
414 | void pcibios_bus_to_resource(struct pci_dev *dev, | |
415 | struct resource *res, struct pci_bus_region *region) | |
416 | { | |
417 | struct pci_controller *controller = PCI_CONTROLLER(dev); | |
418 | unsigned long offset = 0; | |
419 | int i; | |
420 | ||
421 | for (i = 0; i < controller->windows; i++) { | |
422 | struct pci_window *window = &controller->window[i]; | |
423 | if (!(window->resource.flags & res->flags)) | |
424 | continue; | |
425 | if (window->resource.start - window->offset > region->start) | |
426 | continue; | |
427 | if (window->resource.end - window->offset < region->end) | |
428 | continue; | |
429 | offset = window->offset; | |
430 | break; | |
431 | } | |
432 | ||
433 | res->start = region->start + offset; | |
434 | res->end = region->end + offset; | |
435 | } | |
41290c14 | 436 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 | 437 | |
71c3511c RS |
438 | static int __devinit is_valid_resource(struct pci_dev *dev, int idx) |
439 | { | |
440 | unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM; | |
441 | struct resource *devr = &dev->resource[idx]; | |
442 | ||
443 | if (!dev->bus) | |
444 | return 0; | |
445 | for (i=0; i<PCI_BUS_NUM_RESOURCES; i++) { | |
446 | struct resource *busr = dev->bus->resource[i]; | |
447 | ||
448 | if (!busr || ((busr->flags ^ devr->flags) & type_mask)) | |
449 | continue; | |
450 | if ((devr->start) && (devr->start >= busr->start) && | |
451 | (devr->end <= busr->end)) | |
452 | return 1; | |
453 | } | |
454 | return 0; | |
455 | } | |
456 | ||
7b9c8ba2 KK |
457 | static void __devinit |
458 | pcibios_fixup_resources(struct pci_dev *dev, int start, int limit) | |
1da177e4 LT |
459 | { |
460 | struct pci_bus_region region; | |
461 | int i; | |
1da177e4 | 462 | |
7b9c8ba2 | 463 | for (i = start; i < limit; i++) { |
1da177e4 LT |
464 | if (!dev->resource[i].flags) |
465 | continue; | |
466 | region.start = dev->resource[i].start; | |
467 | region.end = dev->resource[i].end; | |
468 | pcibios_bus_to_resource(dev, &dev->resource[i], ®ion); | |
71c3511c RS |
469 | if ((is_valid_resource(dev, i))) |
470 | pci_claim_resource(dev, i); | |
1da177e4 LT |
471 | } |
472 | } | |
473 | ||
8ea6091f | 474 | void __devinit pcibios_fixup_device_resources(struct pci_dev *dev) |
7b9c8ba2 KK |
475 | { |
476 | pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES); | |
477 | } | |
8ea6091f | 478 | EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources); |
7b9c8ba2 KK |
479 | |
480 | static void __devinit pcibios_fixup_bridge_resources(struct pci_dev *dev) | |
481 | { | |
482 | pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES); | |
483 | } | |
484 | ||
1da177e4 LT |
485 | /* |
486 | * Called after each bus is probed, but before its children are examined. | |
487 | */ | |
488 | void __devinit | |
489 | pcibios_fixup_bus (struct pci_bus *b) | |
490 | { | |
491 | struct pci_dev *dev; | |
492 | ||
f7d473d9 RS |
493 | if (b->self) { |
494 | pci_read_bridge_bases(b); | |
7b9c8ba2 | 495 | pcibios_fixup_bridge_resources(b->self); |
1d89b30c MW |
496 | } else { |
497 | pcibios_setup_root_windows(b, b->sysdata); | |
f7d473d9 | 498 | } |
1da177e4 LT |
499 | list_for_each_entry(dev, &b->devices, bus_list) |
500 | pcibios_fixup_device_resources(dev); | |
8ea6091f | 501 | platform_pci_fixup_bus(b); |
1da177e4 LT |
502 | |
503 | return; | |
504 | } | |
505 | ||
506 | void __devinit | |
507 | pcibios_update_irq (struct pci_dev *dev, int irq) | |
508 | { | |
509 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); | |
510 | ||
511 | /* ??? FIXME -- record old value for shutdown. */ | |
512 | } | |
513 | ||
1da177e4 LT |
514 | int |
515 | pcibios_enable_device (struct pci_dev *dev, int mask) | |
516 | { | |
517 | int ret; | |
518 | ||
d981f163 | 519 | ret = pci_enable_resources(dev, mask); |
1da177e4 LT |
520 | if (ret < 0) |
521 | return ret; | |
522 | ||
bba6f6fc EB |
523 | if (!dev->msi_enabled) |
524 | return acpi_pci_irq_enable(dev); | |
525 | return 0; | |
1da177e4 LT |
526 | } |
527 | ||
1da177e4 LT |
528 | void |
529 | pcibios_disable_device (struct pci_dev *dev) | |
530 | { | |
c7f570a5 | 531 | BUG_ON(atomic_read(&dev->enable_cnt)); |
bba6f6fc EB |
532 | if (!dev->msi_enabled) |
533 | acpi_pci_irq_disable(dev); | |
1da177e4 | 534 | } |
1da177e4 LT |
535 | |
536 | void | |
537 | pcibios_align_resource (void *data, struct resource *res, | |
e31dd6e4 | 538 | resource_size_t size, resource_size_t align) |
1da177e4 LT |
539 | { |
540 | } | |
541 | ||
542 | /* | |
543 | * PCI BIOS setup, always defaults to SAL interface | |
544 | */ | |
944c54e7 | 545 | char * __init |
1da177e4 LT |
546 | pcibios_setup (char *str) |
547 | { | |
ac311ac2 | 548 | return str; |
1da177e4 LT |
549 | } |
550 | ||
551 | int | |
552 | pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, | |
553 | enum pci_mmap_state mmap_state, int write_combine) | |
554 | { | |
012b7105 AC |
555 | unsigned long size = vma->vm_end - vma->vm_start; |
556 | pgprot_t prot; | |
557 | ||
1da177e4 LT |
558 | /* |
559 | * I/O space cannot be accessed via normal processor loads and | |
560 | * stores on this platform. | |
561 | */ | |
562 | if (mmap_state == pci_mmap_io) | |
563 | /* | |
564 | * XXX we could relax this for I/O spaces for which ACPI | |
565 | * indicates that the space is 1-to-1 mapped. But at the | |
566 | * moment, we don't support multiple PCI address spaces and | |
567 | * the legacy I/O space is not 1-to-1 mapped, so this is moot. | |
568 | */ | |
569 | return -EINVAL; | |
570 | ||
012b7105 AC |
571 | if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size)) |
572 | return -EINVAL; | |
573 | ||
574 | prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size, | |
575 | vma->vm_page_prot); | |
576 | ||
1da177e4 | 577 | /* |
012b7105 AC |
578 | * If the user requested WC, the kernel uses UC or WC for this region, |
579 | * and the chipset supports WC, we can use WC. Otherwise, we have to | |
580 | * use the same attribute the kernel uses. | |
1da177e4 | 581 | */ |
012b7105 AC |
582 | if (write_combine && |
583 | ((pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_UC || | |
584 | (pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_WC) && | |
585 | efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start)) | |
1da177e4 LT |
586 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); |
587 | else | |
012b7105 | 588 | vma->vm_page_prot = prot; |
1da177e4 LT |
589 | |
590 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
591 | vma->vm_end - vma->vm_start, vma->vm_page_prot)) | |
592 | return -EAGAIN; | |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
597 | /** | |
598 | * ia64_pci_get_legacy_mem - generic legacy mem routine | |
599 | * @bus: bus to get legacy memory base address for | |
600 | * | |
601 | * Find the base of legacy memory for @bus. This is typically the first | |
602 | * megabyte of bus address space for @bus or is simply 0 on platforms whose | |
603 | * chipsets support legacy I/O and memory routing. Returns the base address | |
604 | * or an error pointer if an error occurred. | |
605 | * | |
606 | * This is the ia64 generic version of this routine. Other platforms | |
607 | * are free to override it with a machine vector. | |
608 | */ | |
609 | char *ia64_pci_get_legacy_mem(struct pci_bus *bus) | |
610 | { | |
611 | return (char *)__IA64_UNCACHED_OFFSET; | |
612 | } | |
613 | ||
614 | /** | |
615 | * pci_mmap_legacy_page_range - map legacy memory space to userland | |
616 | * @bus: bus whose legacy space we're mapping | |
617 | * @vma: vma passed in by mmap | |
618 | * | |
619 | * Map legacy memory space for this device back to userspace using a machine | |
620 | * vector to get the base address. | |
621 | */ | |
622 | int | |
f19aeb1f BH |
623 | pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma, |
624 | enum pci_mmap_state mmap_state) | |
1da177e4 | 625 | { |
32e62c63 BH |
626 | unsigned long size = vma->vm_end - vma->vm_start; |
627 | pgprot_t prot; | |
1da177e4 LT |
628 | char *addr; |
629 | ||
f19aeb1f BH |
630 | /* We only support mmap'ing of legacy memory space */ |
631 | if (mmap_state != pci_mmap_mem) | |
632 | return -ENOSYS; | |
633 | ||
32e62c63 BH |
634 | /* |
635 | * Avoid attribute aliasing. See Documentation/ia64/aliasing.txt | |
636 | * for more details. | |
637 | */ | |
06c67bef | 638 | if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size)) |
32e62c63 BH |
639 | return -EINVAL; |
640 | prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size, | |
641 | vma->vm_page_prot); | |
32e62c63 | 642 | |
1da177e4 LT |
643 | addr = pci_get_legacy_mem(bus); |
644 | if (IS_ERR(addr)) | |
645 | return PTR_ERR(addr); | |
646 | ||
647 | vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT; | |
32e62c63 | 648 | vma->vm_page_prot = prot; |
1da177e4 LT |
649 | |
650 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
32e62c63 | 651 | size, vma->vm_page_prot)) |
1da177e4 LT |
652 | return -EAGAIN; |
653 | ||
654 | return 0; | |
655 | } | |
656 | ||
657 | /** | |
658 | * ia64_pci_legacy_read - read from legacy I/O space | |
659 | * @bus: bus to read | |
660 | * @port: legacy port value | |
661 | * @val: caller allocated storage for returned value | |
662 | * @size: number of bytes to read | |
663 | * | |
664 | * Simply reads @size bytes from @port and puts the result in @val. | |
665 | * | |
666 | * Again, this (and the write routine) are generic versions that can be | |
667 | * overridden by the platform. This is necessary on platforms that don't | |
668 | * support legacy I/O routing or that hard fail on legacy I/O timeouts. | |
669 | */ | |
670 | int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size) | |
671 | { | |
672 | int ret = size; | |
673 | ||
674 | switch (size) { | |
675 | case 1: | |
676 | *val = inb(port); | |
677 | break; | |
678 | case 2: | |
679 | *val = inw(port); | |
680 | break; | |
681 | case 4: | |
682 | *val = inl(port); | |
683 | break; | |
684 | default: | |
685 | ret = -EINVAL; | |
686 | break; | |
687 | } | |
688 | ||
689 | return ret; | |
690 | } | |
691 | ||
692 | /** | |
693 | * ia64_pci_legacy_write - perform a legacy I/O write | |
694 | * @bus: bus pointer | |
695 | * @port: port to write | |
696 | * @val: value to write | |
697 | * @size: number of bytes to write from @val | |
698 | * | |
699 | * Simply writes @size bytes of @val to @port. | |
700 | */ | |
a72391e4 | 701 | int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size) |
1da177e4 | 702 | { |
408045af | 703 | int ret = size; |
1da177e4 LT |
704 | |
705 | switch (size) { | |
706 | case 1: | |
707 | outb(val, port); | |
708 | break; | |
709 | case 2: | |
710 | outw(val, port); | |
711 | break; | |
712 | case 4: | |
713 | outl(val, port); | |
714 | break; | |
715 | default: | |
716 | ret = -EINVAL; | |
717 | break; | |
718 | } | |
719 | ||
720 | return ret; | |
721 | } | |
722 | ||
723 | /** | |
3efe2d84 | 724 | * set_pci_cacheline_size - determine cacheline size for PCI devices |
1da177e4 LT |
725 | * |
726 | * We want to use the line-size of the outer-most cache. We assume | |
727 | * that this line-size is the same for all CPUs. | |
728 | * | |
729 | * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info(). | |
1da177e4 | 730 | */ |
ac1aa47b | 731 | static void __init set_pci_dfl_cacheline_size(void) |
1da177e4 | 732 | { |
e088a4ad MW |
733 | unsigned long levels, unique_caches; |
734 | long status; | |
1da177e4 | 735 | pal_cache_config_info_t cci; |
1da177e4 LT |
736 | |
737 | status = ia64_pal_cache_summary(&levels, &unique_caches); | |
738 | if (status != 0) { | |
3efe2d84 | 739 | printk(KERN_ERR "%s: ia64_pal_cache_summary() failed " |
d4ed8084 | 740 | "(status=%ld)\n", __func__, status); |
3efe2d84 | 741 | return; |
1da177e4 LT |
742 | } |
743 | ||
3efe2d84 MW |
744 | status = ia64_pal_cache_config_info(levels - 1, |
745 | /* cache_type (data_or_unified)= */ 2, &cci); | |
1da177e4 | 746 | if (status != 0) { |
3efe2d84 | 747 | printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed " |
d4ed8084 | 748 | "(status=%ld)\n", __func__, status); |
3efe2d84 | 749 | return; |
1da177e4 | 750 | } |
ac1aa47b | 751 | pci_dfl_cache_line_size = (1 << cci.pcci_line_size) / 4; |
1da177e4 LT |
752 | } |
753 | ||
175add19 JK |
754 | u64 ia64_dma_get_required_mask(struct device *dev) |
755 | { | |
756 | u32 low_totalram = ((max_pfn - 1) << PAGE_SHIFT); | |
757 | u32 high_totalram = ((max_pfn - 1) >> (32 - PAGE_SHIFT)); | |
758 | u64 mask; | |
759 | ||
760 | if (!high_totalram) { | |
761 | /* convert to mask just covering totalram */ | |
762 | low_totalram = (1 << (fls(low_totalram) - 1)); | |
763 | low_totalram += low_totalram - 1; | |
764 | mask = low_totalram; | |
765 | } else { | |
766 | high_totalram = (1 << (fls(high_totalram) - 1)); | |
767 | high_totalram += high_totalram - 1; | |
768 | mask = (((u64)high_totalram) << 32) + 0xffffffff; | |
769 | } | |
770 | return mask; | |
771 | } | |
772 | EXPORT_SYMBOL_GPL(ia64_dma_get_required_mask); | |
773 | ||
774 | u64 dma_get_required_mask(struct device *dev) | |
775 | { | |
776 | return platform_dma_get_required_mask(dev); | |
777 | } | |
778 | EXPORT_SYMBOL_GPL(dma_get_required_mask); | |
779 | ||
3efe2d84 MW |
780 | static int __init pcibios_init(void) |
781 | { | |
ac1aa47b | 782 | set_pci_dfl_cacheline_size(); |
3efe2d84 | 783 | return 0; |
1da177e4 | 784 | } |
3efe2d84 MW |
785 | |
786 | subsys_initcall(pcibios_init); |