[net-next-2.6.git] / arch / i386 / kernel / tsc.c

/*
 * This code largely moved from arch/i386/kernel/timer/timer_tsc.c
 * which was originally moved from arch/i386/kernel/time.c.
 * See comments there for proper credits.
 */

#include <linux/clocksource.h>
#include <linux/workqueue.h>
#include <linux/cpufreq.h>
#include <linux/jiffies.h>
#include <linux/init.h>
#include <linux/dmi.h>

#include <asm/delay.h>
#include <asm/tsc.h>
#include <asm/io.h>
#include <asm/timer.h>

#include "mach_timer.h"

/*
 * On some systems the TSC frequency does not
 * change with the cpu frequency. So we need
 * an extra value to store the TSC freq
 */
unsigned int tsc_khz;
unsigned long long (*custom_sched_clock)(void);

int tsc_disable;

#ifdef CONFIG_X86_TSC
static int __init tsc_setup(char *str)
{
	printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
				"cannot disable TSC.\n");
	return 1;
}
#else
/*
 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
 * in cpu/common.c
 */
static int __init tsc_setup(char *str)
{
	tsc_disable = 1;

	return 1;
}
#endif

__setup("notsc", tsc_setup);

/*
 * code to mark and check if the TSC is unstable
 * due to cpufreq or due to unsynced TSCs
 */
static int tsc_unstable;

static inline int check_tsc_unstable(void)
{
	return tsc_unstable;
}

/* Accellerators for sched_clock()
 * convert from cycles(64bits) => nanoseconds (64bits)
 *  basic equation:
 *		ns = cycles / (freq / ns_per_sec)
 *		ns = cycles * (ns_per_sec / freq)
 *		ns = cycles * (10^9 / (cpu_khz * 10^3))
 *		ns = cycles * (10^6 / cpu_khz)
 *
 *	Then we use scaling math (suggested by george@mvista.com) to get:
 *		ns = cycles * (10^6 * SC / cpu_khz) / SC
 *		ns = cycles * cyc2ns_scale / SC
 *
 *	And since SC is a constant power of two, we can convert the div
 *  into a shift.
 *
 *  We can use khz divisor instead of mhz to keep a better percision, since
 *  cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
 *  (mathieu.desnoyers@polymtl.ca)
 *
 *			-johnstul@us.ibm.com "math is hard, lets go shopping!"
 */
static unsigned long cyc2ns_scale __read_mostly;

#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */

static inline void set_cyc2ns_scale(unsigned long cpu_khz)
{
	cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz;
}

static inline unsigned long long cycles_2_ns(unsigned long long cyc)
{
	return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
}

/*
 * Scheduler clock - returns current time in nanosec units.
 */
unsigned long long sched_clock(void)
{
	unsigned long long this_offset;

	/*
	 * Fall back to jiffies if there's no TSC available:
	 */
	if (unlikely(tsc_disable))
		/* No locking but a rare wrong value is not a big deal: */
		return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);

	/* read the Time Stamp Counter: */
	get_scheduled_cycles(this_offset);

	/* return the value in ns */
	return cycles_2_ns(this_offset);
}

unsigned long native_calculate_cpu_khz(void)
{
	unsigned long long start, end;
	unsigned long count;
	u64 delta64;
	int i;
	unsigned long flags;

	local_irq_save(flags);

	/* run 3 times to ensure the cache is warm */
	for (i = 0; i < 3; i++) {
		mach_prepare_counter();
		rdtscll(start);
		mach_countup(&count);
		rdtscll(end);
	}
	/*
	 * Error: ECTCNEVERSET
	 * The CTC wasn't reliable: we got a hit on the very first read,
	 * or the CPU was so fast/slow that the quotient wouldn't fit in
	 * 32 bits..
	 */
	if (count <= 1)
		goto err;

	delta64 = end - start;

	/* cpu freq too fast: */
	if (delta64 > (1ULL<<32))
		goto err;

	/* cpu freq too slow: */
	if (delta64 <= CALIBRATE_TIME_MSEC)
		goto err;

	delta64 += CALIBRATE_TIME_MSEC/2; /* round for do_div */
	do_div(delta64,CALIBRATE_TIME_MSEC);

	local_irq_restore(flags);
	return (unsigned long)delta64;
err:
	local_irq_restore(flags);
	return 0;
}

int recalibrate_cpu_khz(void)
{
#ifndef CONFIG_SMP
	unsigned long cpu_khz_old = cpu_khz;

	if (cpu_has_tsc) {
		cpu_khz = calculate_cpu_khz();
		tsc_khz = cpu_khz;
		cpu_data[0].loops_per_jiffy =
			cpufreq_scale(cpu_data[0].loops_per_jiffy,
					cpu_khz_old, cpu_khz);
		return 0;
	} else
		return -ENODEV;
#else
	return -ENODEV;
#endif
}

EXPORT_SYMBOL(recalibrate_cpu_khz);

void __init tsc_init(void)
{
	if (!cpu_has_tsc || tsc_disable)
		goto out_no_tsc;

	cpu_khz = calculate_cpu_khz();
	tsc_khz = cpu_khz;

	if (!cpu_khz)
		goto out_no_tsc;

	printk("Detected %lu.%03lu MHz processor.\n",
				(unsigned long)cpu_khz / 1000,
				(unsigned long)cpu_khz % 1000);

	set_cyc2ns_scale(cpu_khz);
	use_tsc_delay();
	return;

out_no_tsc:
	/*
	 * Set the tsc_disable flag if there's no TSC support, this
	 * makes it a fast flag for the kernel to see whether it
	 * should be using the TSC.
	 */
	tsc_disable = 1;
}

#ifdef CONFIG_CPU_FREQ

/*
 * if the CPU frequency is scaled, TSC-based delays will need a different
 * loops_per_jiffy value to function properly.
 */
static unsigned int ref_freq = 0;
static unsigned long loops_per_jiffy_ref = 0;
static unsigned long cpu_khz_ref = 0;

static int
time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data)
{
	struct cpufreq_freqs *freq = data;

	if (val != CPUFREQ_RESUMECHANGE && val != CPUFREQ_SUSPENDCHANGE)
		write_seqlock_irq(&xtime_lock);

	if (!ref_freq) {
		if (!freq->old){
			ref_freq = freq->new;
			goto end;
		}
		ref_freq = freq->old;
		loops_per_jiffy_ref = cpu_data[freq->cpu].loops_per_jiffy;
		cpu_khz_ref = cpu_khz;
	}

	if ((val == CPUFREQ_PRECHANGE  && freq->old < freq->new) ||
	    (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
	    (val == CPUFREQ_RESUMECHANGE)) {
		if (!(freq->flags & CPUFREQ_CONST_LOOPS))
			cpu_data[freq->cpu].loops_per_jiffy =
				cpufreq_scale(loops_per_jiffy_ref,
						ref_freq, freq->new);

		if (cpu_khz) {

			if (num_online_cpus() == 1)
				cpu_khz = cpufreq_scale(cpu_khz_ref,
						ref_freq, freq->new);
			if (!(freq->flags & CPUFREQ_CONST_LOOPS)) {
				tsc_khz = cpu_khz;
				set_cyc2ns_scale(cpu_khz);
				/*
				 * TSC based sched_clock turns
				 * to junk w/ cpufreq
				 */
				mark_tsc_unstable();
			}
		}
	}
end:
	if (val != CPUFREQ_RESUMECHANGE && val != CPUFREQ_SUSPENDCHANGE)
		write_sequnlock_irq(&xtime_lock);

	return 0;
}

static struct notifier_block time_cpufreq_notifier_block = {
	.notifier_call	= time_cpufreq_notifier
};

static int __init cpufreq_tsc(void)
{
	return cpufreq_register_notifier(&time_cpufreq_notifier_block,
					 CPUFREQ_TRANSITION_NOTIFIER);
}
core_initcall(cpufreq_tsc);

#endif

/* clock source code */

static unsigned long current_tsc_khz = 0;

static cycle_t read_tsc(void)
{
	cycle_t ret;

	rdtscll(ret);

	return ret;
}

static struct clocksource clocksource_tsc = {
	.name			= "tsc",
	.rating			= 300,
	.read			= read_tsc,
	.mask			= CLOCKSOURCE_MASK(64),
	.mult			= 0, /* to be set */
	.shift			= 22,
	.flags			= CLOCK_SOURCE_IS_CONTINUOUS |
				  CLOCK_SOURCE_MUST_VERIFY,
};

void mark_tsc_unstable(void)
{
	if (!tsc_unstable) {
		tsc_unstable = 1;
		/* Can be called before registration */
		if (clocksource_tsc.mult)
			clocksource_change_rating(&clocksource_tsc, 0);
		else
			clocksource_tsc.rating = 0;
	}
}
EXPORT_SYMBOL_GPL(mark_tsc_unstable);

static int __init dmi_mark_tsc_unstable(struct dmi_system_id *d)
{
	printk(KERN_NOTICE "%s detected: marking TSC unstable.\n",
		       d->ident);
	tsc_unstable = 1;
	return 0;
}

/* List of systems that have known TSC problems */
static struct dmi_system_id __initdata bad_tsc_dmi_table[] = {
	{
	 .callback = dmi_mark_tsc_unstable,
	 .ident = "IBM Thinkpad 380XD",
	 .matches = {
		     DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
		     DMI_MATCH(DMI_BOARD_NAME, "2635FA0"),
		     },
	 },
	 {}
};

/*
 * Make an educated guess if the TSC is trustworthy and synchronized
 * over all CPUs.
 */
__cpuinit int unsynchronized_tsc(void)
{
	if (!cpu_has_tsc || tsc_unstable)
		return 1;
	/*
	 * Intel systems are normally all synchronized.
	 * Exceptions must mark TSC as unstable:
	 */
	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
		/* assume multi socket systems are not synchronized: */
		if (num_possible_cpus() > 1)
			tsc_unstable = 1;
	}
	return tsc_unstable;
}

/*
 * Geode_LX - the OLPC CPU has a possibly a very reliable TSC
 */
#ifdef CONFIG_MGEODE_LX
/* RTSC counts during suspend */
#define RTSC_SUSP 0x100

static void __init check_geode_tsc_reliable(void)
{
	unsigned long val;

	rdmsrl(MSR_GEODE_BUSCONT_CONF0, val);
	if ((val & RTSC_SUSP))
		clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
}
#else
static inline void check_geode_tsc_reliable(void) { }
#endif

static int __init init_tsc_clocksource(void)
{

	if (cpu_has_tsc && tsc_khz && !tsc_disable) {
		/* check blacklist */
		dmi_check_system(bad_tsc_dmi_table);

		unsynchronized_tsc();
		check_geode_tsc_reliable();
		current_tsc_khz = tsc_khz;
		clocksource_tsc.mult = clocksource_khz2mult(current_tsc_khz,
							clocksource_tsc.shift);
		/* lower the rating if we already know its unstable: */
		if (check_tsc_unstable()) {
			clocksource_tsc.rating = 0;
			clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
		}

		return clocksource_register(&clocksource_tsc);
	}

	return 0;
}

module_init(init_tsc_clocksource);
Commit	Line	Data
539eb11e JS	1	/*
	2	* This code largely moved from arch/i386/kernel/timer/timer_tsc.c
	3	* which was originally moved from arch/i386/kernel/time.c.
	4	* See comments there for proper credits.
	5	*/
	6
5d0cf410	7	#include <linux/clocksource.h>
539eb11e JS	8	#include <linux/workqueue.h>
	9	#include <linux/cpufreq.h>
	10	#include <linux/jiffies.h>
	11	#include <linux/init.h>
5d0cf410	12	#include <linux/dmi.h>
539eb11e	13
5d0cf410	14	#include <asm/delay.h>
539eb11e JS	15	#include <asm/tsc.h>
539eb11e JS	16	#include <asm/io.h>
6cb9a835	17	#include <asm/timer.h>
539eb11e JS	18
	19	#include "mach_timer.h"
	20
	21	/*
	22	* On some systems the TSC frequency does not
	23	* change with the cpu frequency. So we need
	24	* an extra value to store the TSC freq
	25	*/
	26	unsigned int tsc_khz;
bbab4f3b	27	unsigned long long (*custom_sched_clock)(void);
539eb11e	28
664c0d3d	29	int tsc_disable;
539eb11e JS	30
	31	#ifdef CONFIG_X86_TSC
	32	static int __init tsc_setup(char *str)
	33	{
	34	printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
	35	"cannot disable TSC.\n");
	36	return 1;
	37	}
	38	#else
	39	/*
	40	* disable flag for tsc. Takes effect by clearing the TSC cpu flag
	41	* in cpu/common.c
	42	*/
	43	static int __init tsc_setup(char *str)
	44	{
	45	tsc_disable = 1;
	46
	47	return 1;
	48	}
	49	#endif
	50
	51	__setup("notsc", tsc_setup);
	52
539eb11e JS	53	/*
	54	* code to mark and check if the TSC is unstable
	55	* due to cpufreq or due to unsynced TSCs
	56	*/
	57	static int tsc_unstable;
	58
	59	static inline int check_tsc_unstable(void)
	60	{
	61	return tsc_unstable;
	62	}
	63
539eb11e JS	64	/* Accellerators for sched_clock()
	65	* convert from cycles(64bits) => nanoseconds (64bits)
	66	* basic equation:
	67	* ns = cycles / (freq / ns_per_sec)
	68	* ns = cycles * (ns_per_sec / freq)
	69	* ns = cycles * (10^9 / (cpu_khz * 10^3))
	70	* ns = cycles * (10^6 / cpu_khz)
	71	*
	72	* Then we use scaling math (suggested by george@mvista.com) to get:
	73	* ns = cycles * (10^6 * SC / cpu_khz) / SC
	74	* ns = cycles * cyc2ns_scale / SC
	75	*
	76	* And since SC is a constant power of two, we can convert the div
	77	* into a shift.
	78	*
	79	* We can use khz divisor instead of mhz to keep a better percision, since
	80	* cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
	81	* (mathieu.desnoyers@polymtl.ca)
	82	*
	83	* -johnstul@us.ibm.com "math is hard, lets go shopping!"
	84	*/
	85	static unsigned long cyc2ns_scale __read_mostly;
	86
	87	#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
	88
	89	static inline void set_cyc2ns_scale(unsigned long cpu_khz)
	90	{
	91	cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz;
	92	}
	93
	94	static inline unsigned long long cycles_2_ns(unsigned long long cyc)
	95	{
	96	return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
	97	}
	98
	99	/*
	100	* Scheduler clock - returns current time in nanosec units.
	101	*/
	102	unsigned long long sched_clock(void)
	103	{
	104	unsigned long long this_offset;
	105
	106	/*
f9690982	107	* Fall back to jiffies if there's no TSC available:
539eb11e	108	*/
f9690982 IM	109	if (unlikely(tsc_disable))
f9690982 IM	110	/* No locking but a rare wrong value is not a big deal: */
539eb11e JS	111	return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
	112
	113	/* read the Time Stamp Counter: */
6cb9a835	114	get_scheduled_cycles(this_offset);
539eb11e JS	115
	116	/* return the value in ns */
	117	return cycles_2_ns(this_offset);
	118	}
	119
1182d852	120	unsigned long native_calculate_cpu_khz(void)
539eb11e JS	121	{
	122	unsigned long long start, end;
	123	unsigned long count;
	124	u64 delta64;
	125	int i;
	126	unsigned long flags;
	127
	128	local_irq_save(flags);
	129
	130	/* run 3 times to ensure the cache is warm */
	131	for (i = 0; i < 3; i++) {
	132	mach_prepare_counter();
	133	rdtscll(start);
	134	mach_countup(&count);
	135	rdtscll(end);
	136	}
	137	/*
	138	* Error: ECTCNEVERSET
	139	* The CTC wasn't reliable: we got a hit on the very first read,
	140	* or the CPU was so fast/slow that the quotient wouldn't fit in
	141	* 32 bits..
	142	*/
	143	if (count <= 1)
	144	goto err;
	145
	146	delta64 = end - start;
	147
	148	/* cpu freq too fast: */
	149	if (delta64 > (1ULL<<32))
	150	goto err;
	151
	152	/* cpu freq too slow: */
	153	if (delta64 <= CALIBRATE_TIME_MSEC)
	154	goto err;
	155
	156	delta64 += CALIBRATE_TIME_MSEC/2; /* round for do_div */
	157	do_div(delta64,CALIBRATE_TIME_MSEC);
	158
	159	local_irq_restore(flags);
	160	return (unsigned long)delta64;
	161	err:
	162	local_irq_restore(flags);
	163	return 0;
	164	}
	165
	166	int recalibrate_cpu_khz(void)
	167	{
	168	#ifndef CONFIG_SMP
	169	unsigned long cpu_khz_old = cpu_khz;
	170
	171	if (cpu_has_tsc) {
	172	cpu_khz = calculate_cpu_khz();
	173	tsc_khz = cpu_khz;
	174	cpu_data[0].loops_per_jiffy =
	175	cpufreq_scale(cpu_data[0].loops_per_jiffy,
	176	cpu_khz_old, cpu_khz);
	177	return 0;
	178	} else
	179	return -ENODEV;
	180	#else
	181	return -ENODEV;
	182	#endif
	183	}
	184
185	EXPORT_SYMBOL(recalibrate_cpu_khz);
186
c0d83745	187	void __init tsc_init(void)
539eb11e JS	188	{
539eb11e JS	189	if (!cpu_has_tsc \|\| tsc_disable)
f9690982	190	goto out_no_tsc;
539eb11e JS	191
	192	cpu_khz = calculate_cpu_khz();
	193	tsc_khz = cpu_khz;
	194
	195	if (!cpu_khz)
f9690982	196	goto out_no_tsc;
539eb11e JS	197
	198	printk("Detected %lu.%03lu MHz processor.\n",
	199	(unsigned long)cpu_khz / 1000,
	200	(unsigned long)cpu_khz % 1000);
	201
	202	set_cyc2ns_scale(cpu_khz);
6f84fa2f	203	use_tsc_delay();
f9690982 IM	204	return;
	205
	206	out_no_tsc:
	207	/*
	208	* Set the tsc_disable flag if there's no TSC support, this
	209	* makes it a fast flag for the kernel to see whether it
	210	* should be using the TSC.
	211	*/
	212	tsc_disable = 1;
539eb11e JS	213	}
	214
	215	#ifdef CONFIG_CPU_FREQ
	216
539eb11e JS	217	/*
	218	* if the CPU frequency is scaled, TSC-based delays will need a different
	219	* loops_per_jiffy value to function properly.
	220	*/
	221	static unsigned int ref_freq = 0;
	222	static unsigned long loops_per_jiffy_ref = 0;
	223	static unsigned long cpu_khz_ref = 0;
	224
	225	static int
	226	time_cpufreq_notifier(struct notifier_block nb, unsigned long val, void data)
	227	{
	228	struct cpufreq_freqs *freq = data;
	229
	230	if (val != CPUFREQ_RESUMECHANGE && val != CPUFREQ_SUSPENDCHANGE)
	231	write_seqlock_irq(&xtime_lock);
	232
	233	if (!ref_freq) {
	234	if (!freq->old){
	235	ref_freq = freq->new;
	236	goto end;
	237	}
	238	ref_freq = freq->old;
	239	loops_per_jiffy_ref = cpu_data[freq->cpu].loops_per_jiffy;
	240	cpu_khz_ref = cpu_khz;
	241	}
	242
	243	if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) \|\|
	244	(val == CPUFREQ_POSTCHANGE && freq->old > freq->new) \|\|
	245	(val == CPUFREQ_RESUMECHANGE)) {
	246	if (!(freq->flags & CPUFREQ_CONST_LOOPS))
	247	cpu_data[freq->cpu].loops_per_jiffy =
	248	cpufreq_scale(loops_per_jiffy_ref,
	249	ref_freq, freq->new);
	250
	251	if (cpu_khz) {
	252
	253	if (num_online_cpus() == 1)
	254	cpu_khz = cpufreq_scale(cpu_khz_ref,
	255	ref_freq, freq->new);
	256	if (!(freq->flags & CPUFREQ_CONST_LOOPS)) {
	257	tsc_khz = cpu_khz;
	258	set_cyc2ns_scale(cpu_khz);
	259	/*
	260	* TSC based sched_clock turns
	261	* to junk w/ cpufreq
	262	*/
	263	mark_tsc_unstable();
	264	}
	265	}
	266	}
	267	end:
	268	if (val != CPUFREQ_RESUMECHANGE && val != CPUFREQ_SUSPENDCHANGE)
	269	write_sequnlock_irq(&xtime_lock);
	270
	271	return 0;
	272	}
	273
	274	static struct notifier_block time_cpufreq_notifier_block = {
	275	.notifier_call = time_cpufreq_notifier
	276	};
	277
	278	static int __init cpufreq_tsc(void)
	279	{
26a08eb3 TG	280	return cpufreq_register_notifier(&time_cpufreq_notifier_block,
26a08eb3 TG	281	CPUFREQ_TRANSITION_NOTIFIER);
539eb11e	282	}
539eb11e JS	283	core_initcall(cpufreq_tsc);
	284
	285	#endif
5d0cf410 JS	286
	287	/* clock source code */
	288
	289	static unsigned long current_tsc_khz = 0;
5d0cf410 JS	290
	291	static cycle_t read_tsc(void)
	292	{
	293	cycle_t ret;
	294
	295	rdtscll(ret);
	296
	297	return ret;
	298	}
	299
	300	static struct clocksource clocksource_tsc = {
	301	.name = "tsc",
	302	.rating = 300,
	303	.read = read_tsc,
7f9f303a	304	.mask = CLOCKSOURCE_MASK(64),
5d0cf410 JS	305	.mult = 0, /* to be set */
5d0cf410 JS	306	.shift = 22,
73b08d2a TG	307	.flags = CLOCK_SOURCE_IS_CONTINUOUS \|
73b08d2a TG	308	CLOCK_SOURCE_MUST_VERIFY,
5d0cf410 JS	309	};
5d0cf410 JS	310
7e69f2b1	311	void mark_tsc_unstable(void)
5d0cf410	312	{
7e69f2b1 TG	313	if (!tsc_unstable) {
	314	tsc_unstable = 1;
	315	/* Can be called before registration */
	316	if (clocksource_tsc.mult)
	317	clocksource_change_rating(&clocksource_tsc, 0);
	318	else
	319	clocksource_tsc.rating = 0;
5d0cf410	320	}
5d0cf410	321	}
7e69f2b1	322	EXPORT_SYMBOL_GPL(mark_tsc_unstable);
5d0cf410 JS	323
	324	static int __init dmi_mark_tsc_unstable(struct dmi_system_id *d)
	325	{
	326	printk(KERN_NOTICE "%s detected: marking TSC unstable.\n",
	327	d->ident);
7e69f2b1	328	tsc_unstable = 1;
5d0cf410 JS	329	return 0;
	330	}
	331
	332	/* List of systems that have known TSC problems */
	333	static struct dmi_system_id __initdata bad_tsc_dmi_table[] = {
	334	{
	335	.callback = dmi_mark_tsc_unstable,
	336	.ident = "IBM Thinkpad 380XD",
	337	.matches = {
	338	DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
	339	DMI_MATCH(DMI_BOARD_NAME, "2635FA0"),
	340	},
	341	},
	342	{}
	343	};
	344
5d0cf410 JS	345	/*
	346	* Make an educated guess if the TSC is trustworthy and synchronized
	347	* over all CPUs.
	348	*/
95492e46	349	__cpuinit int unsynchronized_tsc(void)
5d0cf410	350	{
95492e46 IM	351	if (!cpu_has_tsc \|\| tsc_unstable)
95492e46 IM	352	return 1;
5d0cf410 JS	353	/*
	354	* Intel systems are normally all synchronized.
	355	* Exceptions must mark TSC as unstable:
	356	*/
7e69f2b1 TG	357	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
	358	/* assume multi socket systems are not synchronized: */
	359	if (num_possible_cpus() > 1)
	360	tsc_unstable = 1;
	361	}
	362	return tsc_unstable;
5d0cf410 JS	363	}
5d0cf410 JS	364
07190a08 MT	365	/*
	366	* Geode_LX - the OLPC CPU has a possibly a very reliable TSC
	367	*/
	368	#ifdef CONFIG_MGEODE_LX
	369	/* RTSC counts during suspend */
	370	#define RTSC_SUSP 0x100
	371
	372	static void __init check_geode_tsc_reliable(void)
	373	{
	374	unsigned long val;
	375
	376	rdmsrl(MSR_GEODE_BUSCONT_CONF0, val);
	377	if ((val & RTSC_SUSP))
	378	clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
	379	}
	380	#else
	381	static inline void check_geode_tsc_reliable(void) { }
	382	#endif
	383
5d0cf410 JS	384	static int __init init_tsc_clocksource(void)
	385	{
	386
	387	if (cpu_has_tsc && tsc_khz && !tsc_disable) {
	388	/* check blacklist */
	389	dmi_check_system(bad_tsc_dmi_table);
	390
7e69f2b1	391	unsynchronized_tsc();
07190a08	392	check_geode_tsc_reliable();
5d0cf410 JS	393	current_tsc_khz = tsc_khz;
	394	clocksource_tsc.mult = clocksource_khz2mult(current_tsc_khz,
	395	clocksource_tsc.shift);
	396	/* lower the rating if we already know its unstable: */
73b08d2a	397	if (check_tsc_unstable()) {
3f4a0b91	398	clocksource_tsc.rating = 0;
73b08d2a TG	399	clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
73b08d2a TG	400	}
5d0cf410	401
a2752549	402	return clocksource_register(&clocksource_tsc);
5d0cf410 JS	403	}
	404
	405	return 0;
	406	}
	407
	408	module_init(init_tsc_clocksource);