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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * | |
7 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
8 | * whom a great many thanks are extended. | |
9 | * | |
10 | * Thanks to Intel for making available several different Pentium, | |
11 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
12 | * Original development of Linux SMP code supported by Caldera. | |
13 | * | |
14 | * This code is released under the GNU General Public License version 2 or | |
15 | * later. | |
16 | * | |
17 | * Fixes | |
18 | * Felix Koop : NR_CPUS used properly | |
19 | * Jose Renau : Handle single CPU case. | |
20 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
21 | * Greg Wright : Fix for kernel stacks panic. | |
22 | * Erich Boleyn : MP v1.4 and additional changes. | |
23 | * Matthias Sattler : Changes for 2.1 kernel map. | |
24 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
25 | * Michael Chastain : Change trampoline.S to gnu as. | |
26 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
27 | * Ingo Molnar : Added APIC timers, based on code | |
28 | * from Jose Renau | |
29 | * Ingo Molnar : various cleanups and rewrites | |
30 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
31 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
32 | * Martin J. Bligh : Added support for multi-quad systems | |
33 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
34 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. */ | |
35 | ||
36 | #include <linux/module.h> | |
1da177e4 LT |
37 | #include <linux/init.h> |
38 | #include <linux/kernel.h> | |
39 | ||
40 | #include <linux/mm.h> | |
41 | #include <linux/sched.h> | |
42 | #include <linux/kernel_stat.h> | |
43 | #include <linux/smp_lock.h> | |
1da177e4 | 44 | #include <linux/bootmem.h> |
f3705136 ZM |
45 | #include <linux/notifier.h> |
46 | #include <linux/cpu.h> | |
47 | #include <linux/percpu.h> | |
1da177e4 LT |
48 | |
49 | #include <linux/delay.h> | |
50 | #include <linux/mc146818rtc.h> | |
51 | #include <asm/tlbflush.h> | |
52 | #include <asm/desc.h> | |
53 | #include <asm/arch_hooks.h> | |
3e4ff115 | 54 | #include <asm/nmi.h> |
62111195 | 55 | #include <asm/pda.h> |
b0d0a4ba | 56 | #include <asm/genapic.h> |
1da177e4 LT |
57 | |
58 | #include <mach_apic.h> | |
59 | #include <mach_wakecpu.h> | |
60 | #include <smpboot_hooks.h> | |
7ce0bcfd | 61 | #include <asm/vmi.h> |
1da177e4 LT |
62 | |
63 | /* Set if we find a B stepping CPU */ | |
0bb3184d | 64 | static int __devinitdata smp_b_stepping; |
1da177e4 LT |
65 | |
66 | /* Number of siblings per CPU package */ | |
67 | int smp_num_siblings = 1; | |
129f6946 | 68 | EXPORT_SYMBOL(smp_num_siblings); |
d720803a | 69 | |
1e9f28fa SS |
70 | /* Last level cache ID of each logical CPU */ |
71 | int cpu_llc_id[NR_CPUS] __cpuinitdata = {[0 ... NR_CPUS-1] = BAD_APICID}; | |
72 | ||
94605eff | 73 | /* representing HT siblings of each logical CPU */ |
6c036527 | 74 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; |
d720803a LS |
75 | EXPORT_SYMBOL(cpu_sibling_map); |
76 | ||
94605eff | 77 | /* representing HT and core siblings of each logical CPU */ |
6c036527 | 78 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly; |
d720803a LS |
79 | EXPORT_SYMBOL(cpu_core_map); |
80 | ||
1da177e4 | 81 | /* bitmap of online cpus */ |
6c036527 | 82 | cpumask_t cpu_online_map __read_mostly; |
129f6946 | 83 | EXPORT_SYMBOL(cpu_online_map); |
1da177e4 LT |
84 | |
85 | cpumask_t cpu_callin_map; | |
86 | cpumask_t cpu_callout_map; | |
129f6946 | 87 | EXPORT_SYMBOL(cpu_callout_map); |
4ad8d383 ZM |
88 | cpumask_t cpu_possible_map; |
89 | EXPORT_SYMBOL(cpu_possible_map); | |
1da177e4 LT |
90 | static cpumask_t smp_commenced_mask; |
91 | ||
92 | /* Per CPU bogomips and other parameters */ | |
93 | struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned; | |
129f6946 | 94 | EXPORT_SYMBOL(cpu_data); |
1da177e4 | 95 | |
6c036527 | 96 | u8 x86_cpu_to_apicid[NR_CPUS] __read_mostly = |
1da177e4 LT |
97 | { [0 ... NR_CPUS-1] = 0xff }; |
98 | EXPORT_SYMBOL(x86_cpu_to_apicid); | |
99 | ||
3b08606d | 100 | u8 apicid_2_node[MAX_APICID]; |
101 | ||
1da177e4 LT |
102 | /* |
103 | * Trampoline 80x86 program as an array. | |
104 | */ | |
105 | ||
106 | extern unsigned char trampoline_data []; | |
107 | extern unsigned char trampoline_end []; | |
108 | static unsigned char *trampoline_base; | |
109 | static int trampoline_exec; | |
110 | ||
111 | static void map_cpu_to_logical_apicid(void); | |
112 | ||
f3705136 ZM |
113 | /* State of each CPU. */ |
114 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
115 | ||
1da177e4 LT |
116 | /* |
117 | * Currently trivial. Write the real->protected mode | |
118 | * bootstrap into the page concerned. The caller | |
119 | * has made sure it's suitably aligned. | |
120 | */ | |
121 | ||
0bb3184d | 122 | static unsigned long __devinit setup_trampoline(void) |
1da177e4 LT |
123 | { |
124 | memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data); | |
125 | return virt_to_phys(trampoline_base); | |
126 | } | |
127 | ||
128 | /* | |
129 | * We are called very early to get the low memory for the | |
130 | * SMP bootup trampoline page. | |
131 | */ | |
132 | void __init smp_alloc_memory(void) | |
133 | { | |
134 | trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE); | |
135 | /* | |
136 | * Has to be in very low memory so we can execute | |
137 | * real-mode AP code. | |
138 | */ | |
139 | if (__pa(trampoline_base) >= 0x9F000) | |
140 | BUG(); | |
141 | /* | |
142 | * Make the SMP trampoline executable: | |
143 | */ | |
144 | trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1); | |
145 | } | |
146 | ||
147 | /* | |
148 | * The bootstrap kernel entry code has set these up. Save them for | |
149 | * a given CPU | |
150 | */ | |
151 | ||
4a5d107a | 152 | static void __cpuinit smp_store_cpu_info(int id) |
1da177e4 LT |
153 | { |
154 | struct cpuinfo_x86 *c = cpu_data + id; | |
155 | ||
156 | *c = boot_cpu_data; | |
157 | if (id!=0) | |
158 | identify_cpu(c); | |
159 | /* | |
160 | * Mask B, Pentium, but not Pentium MMX | |
161 | */ | |
162 | if (c->x86_vendor == X86_VENDOR_INTEL && | |
163 | c->x86 == 5 && | |
164 | c->x86_mask >= 1 && c->x86_mask <= 4 && | |
165 | c->x86_model <= 3) | |
166 | /* | |
167 | * Remember we have B step Pentia with bugs | |
168 | */ | |
169 | smp_b_stepping = 1; | |
170 | ||
171 | /* | |
172 | * Certain Athlons might work (for various values of 'work') in SMP | |
173 | * but they are not certified as MP capable. | |
174 | */ | |
175 | if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { | |
176 | ||
3ca113ea DJ |
177 | if (num_possible_cpus() == 1) |
178 | goto valid_k7; | |
179 | ||
1da177e4 LT |
180 | /* Athlon 660/661 is valid. */ |
181 | if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1))) | |
182 | goto valid_k7; | |
183 | ||
184 | /* Duron 670 is valid */ | |
185 | if ((c->x86_model==7) && (c->x86_mask==0)) | |
186 | goto valid_k7; | |
187 | ||
188 | /* | |
189 | * Athlon 662, Duron 671, and Athlon >model 7 have capability bit. | |
190 | * It's worth noting that the A5 stepping (662) of some Athlon XP's | |
191 | * have the MP bit set. | |
192 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more. | |
193 | */ | |
194 | if (((c->x86_model==6) && (c->x86_mask>=2)) || | |
195 | ((c->x86_model==7) && (c->x86_mask>=1)) || | |
196 | (c->x86_model> 7)) | |
197 | if (cpu_has_mp) | |
198 | goto valid_k7; | |
199 | ||
200 | /* If we get here, it's not a certified SMP capable AMD system. */ | |
9f158333 | 201 | add_taint(TAINT_UNSAFE_SMP); |
1da177e4 LT |
202 | } |
203 | ||
204 | valid_k7: | |
205 | ; | |
206 | } | |
207 | ||
1da177e4 LT |
208 | extern void calibrate_delay(void); |
209 | ||
210 | static atomic_t init_deasserted; | |
211 | ||
4a5d107a | 212 | static void __cpuinit smp_callin(void) |
1da177e4 LT |
213 | { |
214 | int cpuid, phys_id; | |
215 | unsigned long timeout; | |
216 | ||
217 | /* | |
218 | * If waken up by an INIT in an 82489DX configuration | |
219 | * we may get here before an INIT-deassert IPI reaches | |
220 | * our local APIC. We have to wait for the IPI or we'll | |
221 | * lock up on an APIC access. | |
222 | */ | |
223 | wait_for_init_deassert(&init_deasserted); | |
224 | ||
225 | /* | |
226 | * (This works even if the APIC is not enabled.) | |
227 | */ | |
228 | phys_id = GET_APIC_ID(apic_read(APIC_ID)); | |
229 | cpuid = smp_processor_id(); | |
230 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
231 | printk("huh, phys CPU#%d, CPU#%d already present??\n", | |
232 | phys_id, cpuid); | |
233 | BUG(); | |
234 | } | |
235 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
236 | ||
237 | /* | |
238 | * STARTUP IPIs are fragile beasts as they might sometimes | |
239 | * trigger some glue motherboard logic. Complete APIC bus | |
240 | * silence for 1 second, this overestimates the time the | |
241 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
242 | * by a factor of two. This should be enough. | |
243 | */ | |
244 | ||
245 | /* | |
246 | * Waiting 2s total for startup (udelay is not yet working) | |
247 | */ | |
248 | timeout = jiffies + 2*HZ; | |
249 | while (time_before(jiffies, timeout)) { | |
250 | /* | |
251 | * Has the boot CPU finished it's STARTUP sequence? | |
252 | */ | |
253 | if (cpu_isset(cpuid, cpu_callout_map)) | |
254 | break; | |
255 | rep_nop(); | |
256 | } | |
257 | ||
258 | if (!time_before(jiffies, timeout)) { | |
259 | printk("BUG: CPU%d started up but did not get a callout!\n", | |
260 | cpuid); | |
261 | BUG(); | |
262 | } | |
263 | ||
264 | /* | |
265 | * the boot CPU has finished the init stage and is spinning | |
266 | * on callin_map until we finish. We are free to set up this | |
267 | * CPU, first the APIC. (this is probably redundant on most | |
268 | * boards) | |
269 | */ | |
270 | ||
271 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
272 | smp_callin_clear_local_apic(); | |
273 | setup_local_APIC(); | |
274 | map_cpu_to_logical_apicid(); | |
275 | ||
276 | /* | |
277 | * Get our bogomips. | |
278 | */ | |
279 | calibrate_delay(); | |
280 | Dprintk("Stack at about %p\n",&cpuid); | |
281 | ||
282 | /* | |
283 | * Save our processor parameters | |
284 | */ | |
e9e2cdb4 | 285 | smp_store_cpu_info(cpuid); |
1da177e4 LT |
286 | |
287 | /* | |
288 | * Allow the master to continue. | |
289 | */ | |
290 | cpu_set(cpuid, cpu_callin_map); | |
1da177e4 LT |
291 | } |
292 | ||
293 | static int cpucount; | |
294 | ||
1e9f28fa SS |
295 | /* maps the cpu to the sched domain representing multi-core */ |
296 | cpumask_t cpu_coregroup_map(int cpu) | |
297 | { | |
298 | struct cpuinfo_x86 *c = cpu_data + cpu; | |
299 | /* | |
300 | * For perf, we return last level cache shared map. | |
5c45bf27 | 301 | * And for power savings, we return cpu_core_map |
1e9f28fa | 302 | */ |
5c45bf27 SS |
303 | if (sched_mc_power_savings || sched_smt_power_savings) |
304 | return cpu_core_map[cpu]; | |
305 | else | |
306 | return c->llc_shared_map; | |
1e9f28fa SS |
307 | } |
308 | ||
94605eff SS |
309 | /* representing cpus for which sibling maps can be computed */ |
310 | static cpumask_t cpu_sibling_setup_map; | |
311 | ||
d720803a LS |
312 | static inline void |
313 | set_cpu_sibling_map(int cpu) | |
314 | { | |
315 | int i; | |
94605eff SS |
316 | struct cpuinfo_x86 *c = cpu_data; |
317 | ||
318 | cpu_set(cpu, cpu_sibling_setup_map); | |
d720803a LS |
319 | |
320 | if (smp_num_siblings > 1) { | |
94605eff | 321 | for_each_cpu_mask(i, cpu_sibling_setup_map) { |
4b89aff9 RS |
322 | if (c[cpu].phys_proc_id == c[i].phys_proc_id && |
323 | c[cpu].cpu_core_id == c[i].cpu_core_id) { | |
d720803a LS |
324 | cpu_set(i, cpu_sibling_map[cpu]); |
325 | cpu_set(cpu, cpu_sibling_map[i]); | |
94605eff SS |
326 | cpu_set(i, cpu_core_map[cpu]); |
327 | cpu_set(cpu, cpu_core_map[i]); | |
1e9f28fa SS |
328 | cpu_set(i, c[cpu].llc_shared_map); |
329 | cpu_set(cpu, c[i].llc_shared_map); | |
d720803a LS |
330 | } |
331 | } | |
332 | } else { | |
333 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
334 | } | |
335 | ||
1e9f28fa SS |
336 | cpu_set(cpu, c[cpu].llc_shared_map); |
337 | ||
94605eff | 338 | if (current_cpu_data.x86_max_cores == 1) { |
d720803a | 339 | cpu_core_map[cpu] = cpu_sibling_map[cpu]; |
94605eff SS |
340 | c[cpu].booted_cores = 1; |
341 | return; | |
342 | } | |
343 | ||
344 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
1e9f28fa SS |
345 | if (cpu_llc_id[cpu] != BAD_APICID && |
346 | cpu_llc_id[cpu] == cpu_llc_id[i]) { | |
347 | cpu_set(i, c[cpu].llc_shared_map); | |
348 | cpu_set(cpu, c[i].llc_shared_map); | |
349 | } | |
4b89aff9 | 350 | if (c[cpu].phys_proc_id == c[i].phys_proc_id) { |
94605eff SS |
351 | cpu_set(i, cpu_core_map[cpu]); |
352 | cpu_set(cpu, cpu_core_map[i]); | |
353 | /* | |
354 | * Does this new cpu bringup a new core? | |
355 | */ | |
356 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) { | |
357 | /* | |
358 | * for each core in package, increment | |
359 | * the booted_cores for this new cpu | |
360 | */ | |
361 | if (first_cpu(cpu_sibling_map[i]) == i) | |
362 | c[cpu].booted_cores++; | |
363 | /* | |
364 | * increment the core count for all | |
365 | * the other cpus in this package | |
366 | */ | |
367 | if (i != cpu) | |
368 | c[i].booted_cores++; | |
369 | } else if (i != cpu && !c[cpu].booted_cores) | |
370 | c[cpu].booted_cores = c[i].booted_cores; | |
371 | } | |
d720803a LS |
372 | } |
373 | } | |
374 | ||
1da177e4 LT |
375 | /* |
376 | * Activate a secondary processor. | |
377 | */ | |
4a5d107a | 378 | static void __cpuinit start_secondary(void *unused) |
1da177e4 LT |
379 | { |
380 | /* | |
62111195 | 381 | * Don't put *anything* before secondary_cpu_init(), SMP |
1da177e4 LT |
382 | * booting is too fragile that we want to limit the |
383 | * things done here to the most necessary things. | |
384 | */ | |
7ce0bcfd ZA |
385 | #ifdef CONFIG_VMI |
386 | vmi_bringup(); | |
387 | #endif | |
62111195 | 388 | secondary_cpu_init(); |
5bfb5d69 | 389 | preempt_disable(); |
1da177e4 LT |
390 | smp_callin(); |
391 | while (!cpu_isset(smp_processor_id(), smp_commenced_mask)) | |
392 | rep_nop(); | |
95492e46 IM |
393 | /* |
394 | * Check TSC synchronization with the BP: | |
395 | */ | |
396 | check_tsc_sync_target(); | |
397 | ||
bbab4f3b | 398 | setup_secondary_clock(); |
1da177e4 LT |
399 | if (nmi_watchdog == NMI_IO_APIC) { |
400 | disable_8259A_irq(0); | |
401 | enable_NMI_through_LVT0(NULL); | |
402 | enable_8259A_irq(0); | |
403 | } | |
1da177e4 LT |
404 | /* |
405 | * low-memory mappings have been cleared, flush them from | |
406 | * the local TLBs too. | |
407 | */ | |
408 | local_flush_tlb(); | |
6fe940d6 | 409 | |
d720803a LS |
410 | /* This must be done before setting cpu_online_map */ |
411 | set_cpu_sibling_map(raw_smp_processor_id()); | |
412 | wmb(); | |
413 | ||
6fe940d6 LS |
414 | /* |
415 | * We need to hold call_lock, so there is no inconsistency | |
416 | * between the time smp_call_function() determines number of | |
417 | * IPI receipients, and the time when the determination is made | |
418 | * for which cpus receive the IPI. Holding this | |
419 | * lock helps us to not include this cpu in a currently in progress | |
420 | * smp_call_function(). | |
421 | */ | |
422 | lock_ipi_call_lock(); | |
1da177e4 | 423 | cpu_set(smp_processor_id(), cpu_online_map); |
6fe940d6 | 424 | unlock_ipi_call_lock(); |
e1367daf | 425 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
1da177e4 LT |
426 | |
427 | /* We can take interrupts now: we're officially "up". */ | |
428 | local_irq_enable(); | |
429 | ||
430 | wmb(); | |
431 | cpu_idle(); | |
432 | } | |
433 | ||
434 | /* | |
435 | * Everything has been set up for the secondary | |
436 | * CPUs - they just need to reload everything | |
437 | * from the task structure | |
438 | * This function must not return. | |
439 | */ | |
0bb3184d | 440 | void __devinit initialize_secondary(void) |
1da177e4 | 441 | { |
9ee79a3d JB |
442 | /* |
443 | * switch to the per CPU GDT we already set up | |
444 | * in do_boot_cpu() | |
445 | */ | |
446 | cpu_set_gdt(current_thread_info()->cpu); | |
447 | ||
1da177e4 LT |
448 | /* |
449 | * We don't actually need to load the full TSS, | |
450 | * basically just the stack pointer and the eip. | |
451 | */ | |
452 | ||
453 | asm volatile( | |
454 | "movl %0,%%esp\n\t" | |
455 | "jmp *%1" | |
456 | : | |
62111195 | 457 | :"m" (current->thread.esp),"m" (current->thread.eip)); |
1da177e4 LT |
458 | } |
459 | ||
62111195 | 460 | /* Static state in head.S used to set up a CPU */ |
1da177e4 LT |
461 | extern struct { |
462 | void * esp; | |
463 | unsigned short ss; | |
464 | } stack_start; | |
62111195 | 465 | extern struct i386_pda *start_pda; |
1da177e4 LT |
466 | |
467 | #ifdef CONFIG_NUMA | |
468 | ||
469 | /* which logical CPUs are on which nodes */ | |
6c036527 | 470 | cpumask_t node_2_cpu_mask[MAX_NUMNODES] __read_mostly = |
1da177e4 | 471 | { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; |
a406c366 | 472 | EXPORT_SYMBOL(node_2_cpu_mask); |
1da177e4 | 473 | /* which node each logical CPU is on */ |
6c036527 | 474 | int cpu_2_node[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; |
1da177e4 LT |
475 | EXPORT_SYMBOL(cpu_2_node); |
476 | ||
477 | /* set up a mapping between cpu and node. */ | |
478 | static inline void map_cpu_to_node(int cpu, int node) | |
479 | { | |
480 | printk("Mapping cpu %d to node %d\n", cpu, node); | |
481 | cpu_set(cpu, node_2_cpu_mask[node]); | |
482 | cpu_2_node[cpu] = node; | |
483 | } | |
484 | ||
485 | /* undo a mapping between cpu and node. */ | |
486 | static inline void unmap_cpu_to_node(int cpu) | |
487 | { | |
488 | int node; | |
489 | ||
490 | printk("Unmapping cpu %d from all nodes\n", cpu); | |
491 | for (node = 0; node < MAX_NUMNODES; node ++) | |
492 | cpu_clear(cpu, node_2_cpu_mask[node]); | |
493 | cpu_2_node[cpu] = 0; | |
494 | } | |
495 | #else /* !CONFIG_NUMA */ | |
496 | ||
497 | #define map_cpu_to_node(cpu, node) ({}) | |
498 | #define unmap_cpu_to_node(cpu) ({}) | |
499 | ||
500 | #endif /* CONFIG_NUMA */ | |
501 | ||
6c036527 | 502 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID }; |
1da177e4 LT |
503 | |
504 | static void map_cpu_to_logical_apicid(void) | |
505 | { | |
506 | int cpu = smp_processor_id(); | |
507 | int apicid = logical_smp_processor_id(); | |
78b656b8 | 508 | int node = apicid_to_node(apicid); |
bfa0e9a0 | 509 | |
510 | if (!node_online(node)) | |
511 | node = first_online_node; | |
1da177e4 LT |
512 | |
513 | cpu_2_logical_apicid[cpu] = apicid; | |
bfa0e9a0 | 514 | map_cpu_to_node(cpu, node); |
1da177e4 LT |
515 | } |
516 | ||
517 | static void unmap_cpu_to_logical_apicid(int cpu) | |
518 | { | |
519 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
520 | unmap_cpu_to_node(cpu); | |
521 | } | |
522 | ||
523 | #if APIC_DEBUG | |
524 | static inline void __inquire_remote_apic(int apicid) | |
525 | { | |
526 | int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
527 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
528 | int timeout, status; | |
529 | ||
530 | printk("Inquiring remote APIC #%d...\n", apicid); | |
531 | ||
38e548ee | 532 | for (i = 0; i < ARRAY_SIZE(regs); i++) { |
1da177e4 LT |
533 | printk("... APIC #%d %s: ", apicid, names[i]); |
534 | ||
535 | /* | |
536 | * Wait for idle. | |
537 | */ | |
538 | apic_wait_icr_idle(); | |
539 | ||
540 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); | |
541 | apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
542 | ||
543 | timeout = 0; | |
544 | do { | |
545 | udelay(100); | |
546 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
547 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
548 | ||
549 | switch (status) { | |
550 | case APIC_ICR_RR_VALID: | |
551 | status = apic_read(APIC_RRR); | |
552 | printk("%08x\n", status); | |
553 | break; | |
554 | default: | |
555 | printk("failed\n"); | |
556 | } | |
557 | } | |
558 | } | |
559 | #endif | |
560 | ||
561 | #ifdef WAKE_SECONDARY_VIA_NMI | |
562 | /* | |
563 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
564 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
565 | * won't ... remember to clear down the APIC, etc later. | |
566 | */ | |
0bb3184d | 567 | static int __devinit |
1da177e4 LT |
568 | wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip) |
569 | { | |
570 | unsigned long send_status = 0, accept_status = 0; | |
571 | int timeout, maxlvt; | |
572 | ||
573 | /* Target chip */ | |
574 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid)); | |
575 | ||
576 | /* Boot on the stack */ | |
577 | /* Kick the second */ | |
578 | apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL); | |
579 | ||
580 | Dprintk("Waiting for send to finish...\n"); | |
581 | timeout = 0; | |
582 | do { | |
583 | Dprintk("+"); | |
584 | udelay(100); | |
585 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
586 | } while (send_status && (timeout++ < 1000)); | |
587 | ||
588 | /* | |
589 | * Give the other CPU some time to accept the IPI. | |
590 | */ | |
591 | udelay(200); | |
592 | /* | |
593 | * Due to the Pentium erratum 3AP. | |
594 | */ | |
e05d723f | 595 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
596 | if (maxlvt > 3) { |
597 | apic_read_around(APIC_SPIV); | |
598 | apic_write(APIC_ESR, 0); | |
599 | } | |
600 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
601 | Dprintk("NMI sent.\n"); | |
602 | ||
603 | if (send_status) | |
604 | printk("APIC never delivered???\n"); | |
605 | if (accept_status) | |
606 | printk("APIC delivery error (%lx).\n", accept_status); | |
607 | ||
608 | return (send_status | accept_status); | |
609 | } | |
610 | #endif /* WAKE_SECONDARY_VIA_NMI */ | |
611 | ||
612 | #ifdef WAKE_SECONDARY_VIA_INIT | |
0bb3184d | 613 | static int __devinit |
1da177e4 LT |
614 | wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip) |
615 | { | |
616 | unsigned long send_status = 0, accept_status = 0; | |
617 | int maxlvt, timeout, num_starts, j; | |
618 | ||
619 | /* | |
620 | * Be paranoid about clearing APIC errors. | |
621 | */ | |
622 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
623 | apic_read_around(APIC_SPIV); | |
624 | apic_write(APIC_ESR, 0); | |
625 | apic_read(APIC_ESR); | |
626 | } | |
627 | ||
628 | Dprintk("Asserting INIT.\n"); | |
629 | ||
630 | /* | |
631 | * Turn INIT on target chip | |
632 | */ | |
633 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
634 | ||
635 | /* | |
636 | * Send IPI | |
637 | */ | |
638 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | |
639 | | APIC_DM_INIT); | |
640 | ||
641 | Dprintk("Waiting for send to finish...\n"); | |
642 | timeout = 0; | |
643 | do { | |
644 | Dprintk("+"); | |
645 | udelay(100); | |
646 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
647 | } while (send_status && (timeout++ < 1000)); | |
648 | ||
649 | mdelay(10); | |
650 | ||
651 | Dprintk("Deasserting INIT.\n"); | |
652 | ||
653 | /* Target chip */ | |
654 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
655 | ||
656 | /* Send IPI */ | |
657 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
658 | ||
659 | Dprintk("Waiting for send to finish...\n"); | |
660 | timeout = 0; | |
661 | do { | |
662 | Dprintk("+"); | |
663 | udelay(100); | |
664 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
665 | } while (send_status && (timeout++ < 1000)); | |
666 | ||
667 | atomic_set(&init_deasserted, 1); | |
668 | ||
669 | /* | |
670 | * Should we send STARTUP IPIs ? | |
671 | * | |
672 | * Determine this based on the APIC version. | |
673 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
674 | */ | |
675 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
676 | num_starts = 2; | |
677 | else | |
678 | num_starts = 0; | |
679 | ||
ae5da273 ZA |
680 | /* |
681 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
682 | * target processor state. | |
683 | */ | |
684 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
685 | (unsigned long) stack_start.esp); | |
686 | ||
1da177e4 LT |
687 | /* |
688 | * Run STARTUP IPI loop. | |
689 | */ | |
690 | Dprintk("#startup loops: %d.\n", num_starts); | |
691 | ||
e05d723f | 692 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
693 | |
694 | for (j = 1; j <= num_starts; j++) { | |
695 | Dprintk("Sending STARTUP #%d.\n",j); | |
696 | apic_read_around(APIC_SPIV); | |
697 | apic_write(APIC_ESR, 0); | |
698 | apic_read(APIC_ESR); | |
699 | Dprintk("After apic_write.\n"); | |
700 | ||
701 | /* | |
702 | * STARTUP IPI | |
703 | */ | |
704 | ||
705 | /* Target chip */ | |
706 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
707 | ||
708 | /* Boot on the stack */ | |
709 | /* Kick the second */ | |
710 | apic_write_around(APIC_ICR, APIC_DM_STARTUP | |
711 | | (start_eip >> 12)); | |
712 | ||
713 | /* | |
714 | * Give the other CPU some time to accept the IPI. | |
715 | */ | |
716 | udelay(300); | |
717 | ||
718 | Dprintk("Startup point 1.\n"); | |
719 | ||
720 | Dprintk("Waiting for send to finish...\n"); | |
721 | timeout = 0; | |
722 | do { | |
723 | Dprintk("+"); | |
724 | udelay(100); | |
725 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
726 | } while (send_status && (timeout++ < 1000)); | |
727 | ||
728 | /* | |
729 | * Give the other CPU some time to accept the IPI. | |
730 | */ | |
731 | udelay(200); | |
732 | /* | |
733 | * Due to the Pentium erratum 3AP. | |
734 | */ | |
735 | if (maxlvt > 3) { | |
736 | apic_read_around(APIC_SPIV); | |
737 | apic_write(APIC_ESR, 0); | |
738 | } | |
739 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
740 | if (send_status || accept_status) | |
741 | break; | |
742 | } | |
743 | Dprintk("After Startup.\n"); | |
744 | ||
745 | if (send_status) | |
746 | printk("APIC never delivered???\n"); | |
747 | if (accept_status) | |
748 | printk("APIC delivery error (%lx).\n", accept_status); | |
749 | ||
750 | return (send_status | accept_status); | |
751 | } | |
752 | #endif /* WAKE_SECONDARY_VIA_INIT */ | |
753 | ||
754 | extern cpumask_t cpu_initialized; | |
e1367daf LS |
755 | static inline int alloc_cpu_id(void) |
756 | { | |
757 | cpumask_t tmp_map; | |
758 | int cpu; | |
759 | cpus_complement(tmp_map, cpu_present_map); | |
760 | cpu = first_cpu(tmp_map); | |
761 | if (cpu >= NR_CPUS) | |
762 | return -ENODEV; | |
763 | return cpu; | |
764 | } | |
765 | ||
766 | #ifdef CONFIG_HOTPLUG_CPU | |
767 | static struct task_struct * __devinitdata cpu_idle_tasks[NR_CPUS]; | |
768 | static inline struct task_struct * alloc_idle_task(int cpu) | |
769 | { | |
770 | struct task_struct *idle; | |
771 | ||
772 | if ((idle = cpu_idle_tasks[cpu]) != NULL) { | |
773 | /* initialize thread_struct. we really want to avoid destroy | |
774 | * idle tread | |
775 | */ | |
07b047fc | 776 | idle->thread.esp = (unsigned long)task_pt_regs(idle); |
e1367daf LS |
777 | init_idle(idle, cpu); |
778 | return idle; | |
779 | } | |
780 | idle = fork_idle(cpu); | |
781 | ||
782 | if (!IS_ERR(idle)) | |
783 | cpu_idle_tasks[cpu] = idle; | |
784 | return idle; | |
785 | } | |
786 | #else | |
787 | #define alloc_idle_task(cpu) fork_idle(cpu) | |
788 | #endif | |
1da177e4 | 789 | |
4a5d107a | 790 | static int __cpuinit do_boot_cpu(int apicid, int cpu) |
1da177e4 LT |
791 | /* |
792 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
793 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
794 | * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu. | |
795 | */ | |
796 | { | |
797 | struct task_struct *idle; | |
798 | unsigned long boot_error; | |
e1367daf | 799 | int timeout; |
1da177e4 LT |
800 | unsigned long start_eip; |
801 | unsigned short nmi_high = 0, nmi_low = 0; | |
802 | ||
1da177e4 LT |
803 | /* |
804 | * We can't use kernel_thread since we must avoid to | |
805 | * reschedule the child. | |
806 | */ | |
e1367daf | 807 | idle = alloc_idle_task(cpu); |
1da177e4 LT |
808 | if (IS_ERR(idle)) |
809 | panic("failed fork for CPU %d", cpu); | |
62111195 JF |
810 | |
811 | /* Pre-allocate and initialize the CPU's GDT and PDA so it | |
812 | doesn't have to do any memory allocation during the | |
813 | delicate CPU-bringup phase. */ | |
814 | if (!init_gdt(cpu, idle)) { | |
815 | printk(KERN_INFO "Couldn't allocate GDT/PDA for CPU %d\n", cpu); | |
816 | return -1; /* ? */ | |
817 | } | |
818 | ||
1da177e4 LT |
819 | idle->thread.eip = (unsigned long) start_secondary; |
820 | /* start_eip had better be page-aligned! */ | |
821 | start_eip = setup_trampoline(); | |
822 | ||
62111195 JF |
823 | ++cpucount; |
824 | alternatives_smp_switch(1); | |
825 | ||
1da177e4 LT |
826 | /* So we see what's up */ |
827 | printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip); | |
828 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
829 | stack_start.esp = (void *) idle->thread.esp; | |
830 | ||
831 | irq_ctx_init(cpu); | |
832 | ||
3b08606d | 833 | x86_cpu_to_apicid[cpu] = apicid; |
1da177e4 LT |
834 | /* |
835 | * This grunge runs the startup process for | |
836 | * the targeted processor. | |
837 | */ | |
838 | ||
839 | atomic_set(&init_deasserted, 0); | |
840 | ||
841 | Dprintk("Setting warm reset code and vector.\n"); | |
842 | ||
843 | store_NMI_vector(&nmi_high, &nmi_low); | |
844 | ||
845 | smpboot_setup_warm_reset_vector(start_eip); | |
846 | ||
847 | /* | |
848 | * Starting actual IPI sequence... | |
849 | */ | |
850 | boot_error = wakeup_secondary_cpu(apicid, start_eip); | |
851 | ||
852 | if (!boot_error) { | |
853 | /* | |
854 | * allow APs to start initializing. | |
855 | */ | |
856 | Dprintk("Before Callout %d.\n", cpu); | |
857 | cpu_set(cpu, cpu_callout_map); | |
858 | Dprintk("After Callout %d.\n", cpu); | |
859 | ||
860 | /* | |
861 | * Wait 5s total for a response | |
862 | */ | |
863 | for (timeout = 0; timeout < 50000; timeout++) { | |
864 | if (cpu_isset(cpu, cpu_callin_map)) | |
865 | break; /* It has booted */ | |
866 | udelay(100); | |
867 | } | |
868 | ||
869 | if (cpu_isset(cpu, cpu_callin_map)) { | |
870 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
871 | Dprintk("OK.\n"); | |
872 | printk("CPU%d: ", cpu); | |
873 | print_cpu_info(&cpu_data[cpu]); | |
874 | Dprintk("CPU has booted.\n"); | |
875 | } else { | |
876 | boot_error= 1; | |
877 | if (*((volatile unsigned char *)trampoline_base) | |
878 | == 0xA5) | |
879 | /* trampoline started but...? */ | |
880 | printk("Stuck ??\n"); | |
881 | else | |
882 | /* trampoline code not run */ | |
883 | printk("Not responding.\n"); | |
884 | inquire_remote_apic(apicid); | |
885 | } | |
886 | } | |
e1367daf | 887 | |
1da177e4 LT |
888 | if (boot_error) { |
889 | /* Try to put things back the way they were before ... */ | |
890 | unmap_cpu_to_logical_apicid(cpu); | |
891 | cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */ | |
892 | cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */ | |
893 | cpucount--; | |
e1367daf LS |
894 | } else { |
895 | x86_cpu_to_apicid[cpu] = apicid; | |
896 | cpu_set(cpu, cpu_present_map); | |
1da177e4 LT |
897 | } |
898 | ||
899 | /* mark "stuck" area as not stuck */ | |
900 | *((volatile unsigned long *)trampoline_base) = 0; | |
901 | ||
902 | return boot_error; | |
903 | } | |
904 | ||
e1367daf LS |
905 | #ifdef CONFIG_HOTPLUG_CPU |
906 | void cpu_exit_clear(void) | |
907 | { | |
908 | int cpu = raw_smp_processor_id(); | |
909 | ||
910 | idle_task_exit(); | |
911 | ||
912 | cpucount --; | |
913 | cpu_uninit(); | |
914 | irq_ctx_exit(cpu); | |
915 | ||
916 | cpu_clear(cpu, cpu_callout_map); | |
917 | cpu_clear(cpu, cpu_callin_map); | |
e1367daf LS |
918 | |
919 | cpu_clear(cpu, smp_commenced_mask); | |
920 | unmap_cpu_to_logical_apicid(cpu); | |
921 | } | |
922 | ||
923 | struct warm_boot_cpu_info { | |
924 | struct completion *complete; | |
c4028958 | 925 | struct work_struct task; |
e1367daf LS |
926 | int apicid; |
927 | int cpu; | |
928 | }; | |
929 | ||
c4028958 | 930 | static void __cpuinit do_warm_boot_cpu(struct work_struct *work) |
e1367daf | 931 | { |
c4028958 DH |
932 | struct warm_boot_cpu_info *info = |
933 | container_of(work, struct warm_boot_cpu_info, task); | |
e1367daf LS |
934 | do_boot_cpu(info->apicid, info->cpu); |
935 | complete(info->complete); | |
936 | } | |
937 | ||
34f361ad | 938 | static int __cpuinit __smp_prepare_cpu(int cpu) |
e1367daf | 939 | { |
6e9a4738 | 940 | DECLARE_COMPLETION_ONSTACK(done); |
e1367daf | 941 | struct warm_boot_cpu_info info; |
e1367daf | 942 | int apicid, ret; |
bd9e0b74 | 943 | struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu); |
e1367daf | 944 | |
e1367daf LS |
945 | apicid = x86_cpu_to_apicid[cpu]; |
946 | if (apicid == BAD_APICID) { | |
947 | ret = -ENODEV; | |
948 | goto exit; | |
949 | } | |
950 | ||
bd9e0b74 SL |
951 | /* |
952 | * the CPU isn't initialized at boot time, allocate gdt table here. | |
953 | * cpu_init will initialize it | |
954 | */ | |
955 | if (!cpu_gdt_descr->address) { | |
956 | cpu_gdt_descr->address = get_zeroed_page(GFP_KERNEL); | |
957 | if (!cpu_gdt_descr->address) | |
958 | printk(KERN_CRIT "CPU%d failed to allocate GDT\n", cpu); | |
959 | ret = -ENOMEM; | |
960 | goto exit; | |
961 | } | |
962 | ||
e1367daf LS |
963 | info.complete = &done; |
964 | info.apicid = apicid; | |
965 | info.cpu = cpu; | |
c4028958 | 966 | INIT_WORK(&info.task, do_warm_boot_cpu); |
e1367daf | 967 | |
e1367daf | 968 | /* init low mem mapping */ |
d7271b14 | 969 | clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS, |
3b1bdf4e | 970 | min_t(unsigned long, KERNEL_PGD_PTRS, USER_PGD_PTRS)); |
e1367daf | 971 | flush_tlb_all(); |
c4028958 | 972 | schedule_work(&info.task); |
e1367daf LS |
973 | wait_for_completion(&done); |
974 | ||
e1367daf LS |
975 | zap_low_mappings(); |
976 | ret = 0; | |
977 | exit: | |
e1367daf LS |
978 | return ret; |
979 | } | |
980 | #endif | |
981 | ||
d9408cef | 982 | static void smp_tune_scheduling(void) |
1da177e4 LT |
983 | { |
984 | unsigned long cachesize; /* kB */ | |
1da177e4 | 985 | |
d9408cef | 986 | if (cpu_khz) { |
1da177e4 | 987 | cachesize = boot_cpu_data.x86_cache_size; |
d9408cef AB |
988 | |
989 | if (cachesize > 0) | |
990 | max_cache_size = cachesize * 1024; | |
1da177e4 LT |
991 | } |
992 | } | |
993 | ||
994 | /* | |
995 | * Cycle through the processors sending APIC IPIs to boot each. | |
996 | */ | |
997 | ||
998 | static int boot_cpu_logical_apicid; | |
999 | /* Where the IO area was mapped on multiquad, always 0 otherwise */ | |
1000 | void *xquad_portio; | |
129f6946 AD |
1001 | #ifdef CONFIG_X86_NUMAQ |
1002 | EXPORT_SYMBOL(xquad_portio); | |
1003 | #endif | |
1da177e4 | 1004 | |
1da177e4 LT |
1005 | static void __init smp_boot_cpus(unsigned int max_cpus) |
1006 | { | |
1007 | int apicid, cpu, bit, kicked; | |
1008 | unsigned long bogosum = 0; | |
1009 | ||
1010 | /* | |
1011 | * Setup boot CPU information | |
1012 | */ | |
1013 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1014 | printk("CPU%d: ", 0); | |
1015 | print_cpu_info(&cpu_data[0]); | |
1016 | ||
1e4c85f9 | 1017 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); |
1da177e4 LT |
1018 | boot_cpu_logical_apicid = logical_smp_processor_id(); |
1019 | x86_cpu_to_apicid[0] = boot_cpu_physical_apicid; | |
1020 | ||
1021 | current_thread_info()->cpu = 0; | |
1022 | smp_tune_scheduling(); | |
1da177e4 | 1023 | |
94605eff | 1024 | set_cpu_sibling_map(0); |
3dd9d514 | 1025 | |
1da177e4 LT |
1026 | /* |
1027 | * If we couldn't find an SMP configuration at boot time, | |
1028 | * get out of here now! | |
1029 | */ | |
1030 | if (!smp_found_config && !acpi_lapic) { | |
1031 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); | |
1e4c85f9 LT |
1032 | smpboot_clear_io_apic_irqs(); |
1033 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1034 | if (APIC_init_uniprocessor()) | |
1035 | printk(KERN_NOTICE "Local APIC not detected." | |
1036 | " Using dummy APIC emulation.\n"); | |
1037 | map_cpu_to_logical_apicid(); | |
1038 | cpu_set(0, cpu_sibling_map[0]); | |
1039 | cpu_set(0, cpu_core_map[0]); | |
1040 | return; | |
1041 | } | |
1042 | ||
1043 | /* | |
1044 | * Should not be necessary because the MP table should list the boot | |
1045 | * CPU too, but we do it for the sake of robustness anyway. | |
1046 | * Makes no sense to do this check in clustered apic mode, so skip it | |
1047 | */ | |
1048 | if (!check_phys_apicid_present(boot_cpu_physical_apicid)) { | |
1049 | printk("weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1050 | boot_cpu_physical_apicid); | |
1051 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1052 | } | |
1053 | ||
1054 | /* | |
1055 | * If we couldn't find a local APIC, then get out of here now! | |
1056 | */ | |
1057 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) { | |
1058 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1059 | boot_cpu_physical_apicid); | |
1060 | printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n"); | |
1061 | smpboot_clear_io_apic_irqs(); | |
1062 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1063 | cpu_set(0, cpu_sibling_map[0]); | |
1064 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 LT |
1065 | return; |
1066 | } | |
1067 | ||
1e4c85f9 LT |
1068 | verify_local_APIC(); |
1069 | ||
1da177e4 LT |
1070 | /* |
1071 | * If SMP should be disabled, then really disable it! | |
1072 | */ | |
1e4c85f9 LT |
1073 | if (!max_cpus) { |
1074 | smp_found_config = 0; | |
1075 | printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n"); | |
1076 | smpboot_clear_io_apic_irqs(); | |
1077 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1078 | cpu_set(0, cpu_sibling_map[0]); | |
1079 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 LT |
1080 | return; |
1081 | } | |
1082 | ||
1e4c85f9 LT |
1083 | connect_bsp_APIC(); |
1084 | setup_local_APIC(); | |
1085 | map_cpu_to_logical_apicid(); | |
1086 | ||
1087 | ||
1da177e4 LT |
1088 | setup_portio_remap(); |
1089 | ||
1090 | /* | |
1091 | * Scan the CPU present map and fire up the other CPUs via do_boot_cpu | |
1092 | * | |
1093 | * In clustered apic mode, phys_cpu_present_map is a constructed thus: | |
1094 | * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the | |
1095 | * clustered apic ID. | |
1096 | */ | |
1097 | Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map)); | |
1098 | ||
1099 | kicked = 1; | |
1100 | for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) { | |
1101 | apicid = cpu_present_to_apicid(bit); | |
1102 | /* | |
1103 | * Don't even attempt to start the boot CPU! | |
1104 | */ | |
1105 | if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID)) | |
1106 | continue; | |
1107 | ||
1108 | if (!check_apicid_present(bit)) | |
1109 | continue; | |
1110 | if (max_cpus <= cpucount+1) | |
1111 | continue; | |
1112 | ||
e1367daf | 1113 | if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu)) |
1da177e4 LT |
1114 | printk("CPU #%d not responding - cannot use it.\n", |
1115 | apicid); | |
1116 | else | |
1117 | ++kicked; | |
1118 | } | |
1119 | ||
1120 | /* | |
1121 | * Cleanup possible dangling ends... | |
1122 | */ | |
1123 | smpboot_restore_warm_reset_vector(); | |
1124 | ||
1125 | /* | |
1126 | * Allow the user to impress friends. | |
1127 | */ | |
1128 | Dprintk("Before bogomips.\n"); | |
1129 | for (cpu = 0; cpu < NR_CPUS; cpu++) | |
1130 | if (cpu_isset(cpu, cpu_callout_map)) | |
1131 | bogosum += cpu_data[cpu].loops_per_jiffy; | |
1132 | printk(KERN_INFO | |
1133 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
1134 | cpucount+1, | |
1135 | bogosum/(500000/HZ), | |
1136 | (bogosum/(5000/HZ))%100); | |
1137 | ||
1138 | Dprintk("Before bogocount - setting activated=1.\n"); | |
1139 | ||
1140 | if (smp_b_stepping) | |
1141 | printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n"); | |
1142 | ||
1143 | /* | |
1144 | * Don't taint if we are running SMP kernel on a single non-MP | |
1145 | * approved Athlon | |
1146 | */ | |
1147 | if (tainted & TAINT_UNSAFE_SMP) { | |
1148 | if (cpucount) | |
1149 | printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n"); | |
1150 | else | |
1151 | tainted &= ~TAINT_UNSAFE_SMP; | |
1152 | } | |
1153 | ||
1154 | Dprintk("Boot done.\n"); | |
1155 | ||
1156 | /* | |
1157 | * construct cpu_sibling_map[], so that we can tell sibling CPUs | |
1158 | * efficiently. | |
1159 | */ | |
3dd9d514 | 1160 | for (cpu = 0; cpu < NR_CPUS; cpu++) { |
1da177e4 | 1161 | cpus_clear(cpu_sibling_map[cpu]); |
3dd9d514 AK |
1162 | cpus_clear(cpu_core_map[cpu]); |
1163 | } | |
1da177e4 | 1164 | |
d720803a LS |
1165 | cpu_set(0, cpu_sibling_map[0]); |
1166 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 | 1167 | |
1e4c85f9 LT |
1168 | smpboot_setup_io_apic(); |
1169 | ||
bbab4f3b | 1170 | setup_boot_clock(); |
1da177e4 LT |
1171 | } |
1172 | ||
1173 | /* These are wrappers to interface to the new boot process. Someone | |
1174 | who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */ | |
1175 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
1176 | { | |
f3705136 ZM |
1177 | smp_commenced_mask = cpumask_of_cpu(0); |
1178 | cpu_callin_map = cpumask_of_cpu(0); | |
1179 | mb(); | |
1da177e4 LT |
1180 | smp_boot_cpus(max_cpus); |
1181 | } | |
1182 | ||
1183 | void __devinit smp_prepare_boot_cpu(void) | |
1184 | { | |
1185 | cpu_set(smp_processor_id(), cpu_online_map); | |
1186 | cpu_set(smp_processor_id(), cpu_callout_map); | |
e1367daf | 1187 | cpu_set(smp_processor_id(), cpu_present_map); |
4ad8d383 | 1188 | cpu_set(smp_processor_id(), cpu_possible_map); |
e1367daf | 1189 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
1da177e4 LT |
1190 | } |
1191 | ||
f3705136 | 1192 | #ifdef CONFIG_HOTPLUG_CPU |
e1367daf LS |
1193 | static void |
1194 | remove_siblinginfo(int cpu) | |
1da177e4 | 1195 | { |
e1367daf | 1196 | int sibling; |
94605eff | 1197 | struct cpuinfo_x86 *c = cpu_data; |
e1367daf | 1198 | |
94605eff SS |
1199 | for_each_cpu_mask(sibling, cpu_core_map[cpu]) { |
1200 | cpu_clear(cpu, cpu_core_map[sibling]); | |
1201 | /* | |
1202 | * last thread sibling in this cpu core going down | |
1203 | */ | |
1204 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) | |
1205 | c[sibling].booted_cores--; | |
1206 | } | |
1207 | ||
e1367daf LS |
1208 | for_each_cpu_mask(sibling, cpu_sibling_map[cpu]) |
1209 | cpu_clear(cpu, cpu_sibling_map[sibling]); | |
e1367daf LS |
1210 | cpus_clear(cpu_sibling_map[cpu]); |
1211 | cpus_clear(cpu_core_map[cpu]); | |
4b89aff9 RS |
1212 | c[cpu].phys_proc_id = 0; |
1213 | c[cpu].cpu_core_id = 0; | |
94605eff | 1214 | cpu_clear(cpu, cpu_sibling_setup_map); |
f3705136 ZM |
1215 | } |
1216 | ||
1217 | int __cpu_disable(void) | |
1218 | { | |
1219 | cpumask_t map = cpu_online_map; | |
1220 | int cpu = smp_processor_id(); | |
1221 | ||
1222 | /* | |
1223 | * Perhaps use cpufreq to drop frequency, but that could go | |
1224 | * into generic code. | |
1225 | * | |
1226 | * We won't take down the boot processor on i386 due to some | |
1227 | * interrupts only being able to be serviced by the BSP. | |
1228 | * Especially so if we're not using an IOAPIC -zwane | |
1229 | */ | |
1230 | if (cpu == 0) | |
1231 | return -EBUSY; | |
4038f901 SL |
1232 | if (nmi_watchdog == NMI_LOCAL_APIC) |
1233 | stop_apic_nmi_watchdog(NULL); | |
5e9ef02e | 1234 | clear_local_APIC(); |
f3705136 ZM |
1235 | /* Allow any queued timer interrupts to get serviced */ |
1236 | local_irq_enable(); | |
1237 | mdelay(1); | |
1238 | local_irq_disable(); | |
1239 | ||
e1367daf LS |
1240 | remove_siblinginfo(cpu); |
1241 | ||
f3705136 ZM |
1242 | cpu_clear(cpu, map); |
1243 | fixup_irqs(map); | |
1244 | /* It's now safe to remove this processor from the online map */ | |
1245 | cpu_clear(cpu, cpu_online_map); | |
1246 | return 0; | |
1247 | } | |
1248 | ||
1249 | void __cpu_die(unsigned int cpu) | |
1250 | { | |
1251 | /* We don't do anything here: idle task is faking death itself. */ | |
1252 | unsigned int i; | |
1253 | ||
1254 | for (i = 0; i < 10; i++) { | |
1255 | /* They ack this in play_dead by setting CPU_DEAD */ | |
e1367daf LS |
1256 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { |
1257 | printk ("CPU %d is now offline\n", cpu); | |
9a0b5817 GH |
1258 | if (1 == num_online_cpus()) |
1259 | alternatives_smp_switch(0); | |
f3705136 | 1260 | return; |
e1367daf | 1261 | } |
aeb8397b | 1262 | msleep(100); |
1da177e4 | 1263 | } |
f3705136 ZM |
1264 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); |
1265 | } | |
1266 | #else /* ... !CONFIG_HOTPLUG_CPU */ | |
1267 | int __cpu_disable(void) | |
1268 | { | |
1269 | return -ENOSYS; | |
1270 | } | |
1da177e4 | 1271 | |
f3705136 ZM |
1272 | void __cpu_die(unsigned int cpu) |
1273 | { | |
1274 | /* We said "no" in __cpu_disable */ | |
1275 | BUG(); | |
1276 | } | |
1277 | #endif /* CONFIG_HOTPLUG_CPU */ | |
1278 | ||
4a5d107a | 1279 | int __cpuinit __cpu_up(unsigned int cpu) |
f3705136 | 1280 | { |
34f361ad AR |
1281 | #ifdef CONFIG_HOTPLUG_CPU |
1282 | int ret=0; | |
1283 | ||
1284 | /* | |
1285 | * We do warm boot only on cpus that had booted earlier | |
1286 | * Otherwise cold boot is all handled from smp_boot_cpus(). | |
1287 | * cpu_callin_map is set during AP kickstart process. Its reset | |
1288 | * when a cpu is taken offline from cpu_exit_clear(). | |
1289 | */ | |
1290 | if (!cpu_isset(cpu, cpu_callin_map)) | |
1291 | ret = __smp_prepare_cpu(cpu); | |
1292 | ||
1293 | if (ret) | |
1294 | return -EIO; | |
1295 | #endif | |
1296 | ||
1da177e4 LT |
1297 | /* In case one didn't come up */ |
1298 | if (!cpu_isset(cpu, cpu_callin_map)) { | |
f3705136 | 1299 | printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu); |
1da177e4 LT |
1300 | local_irq_enable(); |
1301 | return -EIO; | |
1302 | } | |
1303 | ||
1304 | local_irq_enable(); | |
95492e46 | 1305 | |
e1367daf | 1306 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; |
1da177e4 LT |
1307 | /* Unleash the CPU! */ |
1308 | cpu_set(cpu, smp_commenced_mask); | |
95492e46 IM |
1309 | |
1310 | /* | |
1311 | * Check TSC synchronization with the AP: | |
1312 | */ | |
1313 | check_tsc_sync_source(cpu); | |
1314 | ||
1da177e4 | 1315 | while (!cpu_isset(cpu, cpu_online_map)) |
18698917 | 1316 | cpu_relax(); |
b0d0a4ba SS |
1317 | |
1318 | #ifdef CONFIG_X86_GENERICARCH | |
1319 | if (num_online_cpus() > 8 && genapic == &apic_default) | |
1320 | panic("Default flat APIC routing can't be used with > 8 cpus\n"); | |
1321 | #endif | |
1322 | ||
1da177e4 LT |
1323 | return 0; |
1324 | } | |
1325 | ||
1326 | void __init smp_cpus_done(unsigned int max_cpus) | |
1327 | { | |
1328 | #ifdef CONFIG_X86_IO_APIC | |
1329 | setup_ioapic_dest(); | |
1330 | #endif | |
1331 | zap_low_mappings(); | |
e1367daf | 1332 | #ifndef CONFIG_HOTPLUG_CPU |
1da177e4 LT |
1333 | /* |
1334 | * Disable executability of the SMP trampoline: | |
1335 | */ | |
1336 | set_kernel_exec((unsigned long)trampoline_base, trampoline_exec); | |
e1367daf | 1337 | #endif |
1da177e4 LT |
1338 | } |
1339 | ||
1340 | void __init smp_intr_init(void) | |
1341 | { | |
1342 | /* | |
1343 | * IRQ0 must be given a fixed assignment and initialized, | |
1344 | * because it's used before the IO-APIC is set up. | |
1345 | */ | |
1346 | set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]); | |
1347 | ||
1348 | /* | |
1349 | * The reschedule interrupt is a CPU-to-CPU reschedule-helper | |
1350 | * IPI, driven by wakeup. | |
1351 | */ | |
1352 | set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt); | |
1353 | ||
1354 | /* IPI for invalidation */ | |
1355 | set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt); | |
1356 | ||
1357 | /* IPI for generic function call */ | |
1358 | set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); | |
1359 | } | |
1a3f239d RR |
1360 | |
1361 | /* | |
1362 | * If the BIOS enumerates physical processors before logical, | |
1363 | * maxcpus=N at enumeration-time can be used to disable HT. | |
1364 | */ | |
1365 | static int __init parse_maxcpus(char *arg) | |
1366 | { | |
1367 | extern unsigned int maxcpus; | |
1368 | ||
1369 | maxcpus = simple_strtoul(arg, NULL, 0); | |
1370 | return 0; | |
1371 | } | |
1372 | early_param("maxcpus", parse_maxcpus); |