]>
Commit | Line | Data |
---|---|---|
58d08319 JN |
1 | #ifndef __iop_sw_cpu_defs_asm_h |
2 | #define __iop_sw_cpu_defs_asm_h | |
3 | ||
4 | /* | |
5 | * This file is autogenerated from | |
6 | * file: iop_sw_cpu.r | |
7 | * | |
8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cpu_defs_asm.h iop_sw_cpu.r | |
9 | * Any changes here will be lost. | |
10 | * | |
11 | * -*- buffer-read-only: t -*- | |
12 | */ | |
13 | ||
14 | #ifndef REG_FIELD | |
15 | #define REG_FIELD( scope, reg, field, value ) \ | |
16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | |
17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | |
18 | #endif | |
19 | ||
20 | #ifndef REG_STATE | |
21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | |
22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | |
23 | #define REG_STATE_X_( k, shift ) (k << shift) | |
24 | #endif | |
25 | ||
26 | #ifndef REG_MASK | |
27 | #define REG_MASK( scope, reg, field ) \ | |
28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | |
29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | |
30 | #endif | |
31 | ||
32 | #ifndef REG_LSB | |
33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | |
34 | #endif | |
35 | ||
36 | #ifndef REG_BIT | |
37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | |
38 | #endif | |
39 | ||
40 | #ifndef REG_ADDR | |
41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | |
42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | |
43 | #endif | |
44 | ||
45 | #ifndef REG_ADDR_VECT | |
46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | |
48 | STRIDE_##scope##_##reg ) | |
49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | |
50 | ((inst) + offs + (index) * stride) | |
51 | #endif | |
52 | ||
53 | /* Register r_mpu_trace, scope iop_sw_cpu, type r */ | |
54 | #define reg_iop_sw_cpu_r_mpu_trace_offset 0 | |
55 | ||
56 | /* Register r_spu_trace, scope iop_sw_cpu, type r */ | |
57 | #define reg_iop_sw_cpu_r_spu_trace_offset 4 | |
58 | ||
59 | /* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ | |
60 | #define reg_iop_sw_cpu_r_spu_fsm_trace_offset 8 | |
61 | ||
62 | /* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ | |
63 | #define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0 | |
64 | #define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1 | |
65 | #define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0 | |
66 | #define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1 | |
67 | #define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2 | |
68 | #define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3 | |
69 | #define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3 | |
70 | #define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___lsb 6 | |
71 | #define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___width 1 | |
72 | #define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___bit 6 | |
73 | #define reg_iop_sw_cpu_rw_mc_ctrl_offset 12 | |
74 | ||
75 | /* Register rw_mc_data, scope iop_sw_cpu, type rw */ | |
76 | #define reg_iop_sw_cpu_rw_mc_data___val___lsb 0 | |
77 | #define reg_iop_sw_cpu_rw_mc_data___val___width 32 | |
78 | #define reg_iop_sw_cpu_rw_mc_data_offset 16 | |
79 | ||
80 | /* Register rw_mc_addr, scope iop_sw_cpu, type rw */ | |
81 | #define reg_iop_sw_cpu_rw_mc_addr_offset 20 | |
82 | ||
83 | /* Register rs_mc_data, scope iop_sw_cpu, type rs */ | |
84 | #define reg_iop_sw_cpu_rs_mc_data_offset 24 | |
85 | ||
86 | /* Register r_mc_data, scope iop_sw_cpu, type r */ | |
87 | #define reg_iop_sw_cpu_r_mc_data_offset 28 | |
88 | ||
89 | /* Register r_mc_stat, scope iop_sw_cpu, type r */ | |
90 | #define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0 | |
91 | #define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1 | |
92 | #define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0 | |
93 | #define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1 | |
94 | #define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1 | |
95 | #define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1 | |
96 | #define reg_iop_sw_cpu_r_mc_stat___busy_spu___lsb 2 | |
97 | #define reg_iop_sw_cpu_r_mc_stat___busy_spu___width 1 | |
98 | #define reg_iop_sw_cpu_r_mc_stat___busy_spu___bit 2 | |
99 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 3 | |
100 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1 | |
101 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 3 | |
102 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 4 | |
103 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1 | |
104 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 4 | |
105 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___lsb 5 | |
106 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___width 1 | |
107 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___bit 5 | |
108 | #define reg_iop_sw_cpu_r_mc_stat_offset 32 | |
109 | ||
110 | /* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ | |
111 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___lsb 0 | |
112 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___width 8 | |
113 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___lsb 8 | |
114 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___width 8 | |
115 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___lsb 16 | |
116 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___width 8 | |
117 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___lsb 24 | |
118 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___width 8 | |
119 | #define reg_iop_sw_cpu_rw_bus_clr_mask_offset 36 | |
120 | ||
121 | /* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ | |
122 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte0___lsb 0 | |
123 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte0___width 8 | |
124 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte1___lsb 8 | |
125 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte1___width 8 | |
126 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte2___lsb 16 | |
127 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte2___width 8 | |
128 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte3___lsb 24 | |
129 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte3___width 8 | |
130 | #define reg_iop_sw_cpu_rw_bus_set_mask_offset 40 | |
131 | ||
132 | /* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ | |
133 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___lsb 0 | |
134 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___width 1 | |
135 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___bit 0 | |
136 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___lsb 1 | |
137 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___width 1 | |
138 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___bit 1 | |
139 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___lsb 2 | |
140 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___width 1 | |
141 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___bit 2 | |
142 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___lsb 3 | |
143 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___width 1 | |
144 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___bit 3 | |
145 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask_offset 44 | |
146 | ||
147 | /* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ | |
148 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___lsb 0 | |
149 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___width 1 | |
150 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___bit 0 | |
151 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___lsb 1 | |
152 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___width 1 | |
153 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___bit 1 | |
154 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___lsb 2 | |
155 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___width 1 | |
156 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___bit 2 | |
157 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___lsb 3 | |
158 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___width 1 | |
159 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___bit 3 | |
160 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask_offset 48 | |
161 | ||
162 | /* Register r_bus_in, scope iop_sw_cpu, type r */ | |
163 | #define reg_iop_sw_cpu_r_bus_in_offset 52 | |
164 | ||
165 | /* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ | |
166 | #define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0 | |
167 | #define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32 | |
168 | #define reg_iop_sw_cpu_rw_gio_clr_mask_offset 56 | |
169 | ||
170 | /* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ | |
171 | #define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0 | |
172 | #define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32 | |
173 | #define reg_iop_sw_cpu_rw_gio_set_mask_offset 60 | |
174 | ||
175 | /* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ | |
176 | #define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0 | |
177 | #define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32 | |
178 | #define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 64 | |
179 | ||
180 | /* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ | |
181 | #define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0 | |
182 | #define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32 | |
183 | #define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 68 | |
184 | ||
185 | /* Register r_gio_in, scope iop_sw_cpu, type r */ | |
186 | #define reg_iop_sw_cpu_r_gio_in_offset 72 | |
187 | ||
188 | /* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ | |
189 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0 | |
190 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1 | |
191 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0 | |
192 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1 | |
193 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1 | |
194 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1 | |
195 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2 | |
196 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1 | |
197 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2 | |
198 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3 | |
199 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1 | |
200 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3 | |
201 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4 | |
202 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1 | |
203 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4 | |
204 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5 | |
205 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1 | |
206 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5 | |
207 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6 | |
208 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1 | |
209 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6 | |
210 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7 | |
211 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1 | |
212 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7 | |
213 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8 | |
214 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1 | |
215 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8 | |
216 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9 | |
217 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1 | |
218 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9 | |
219 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10 | |
220 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1 | |
221 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10 | |
222 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11 | |
223 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1 | |
224 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11 | |
225 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12 | |
226 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1 | |
227 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12 | |
228 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13 | |
229 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1 | |
230 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13 | |
231 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14 | |
232 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1 | |
233 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14 | |
234 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15 | |
235 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1 | |
236 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15 | |
237 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_0___lsb 16 | |
238 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_0___width 1 | |
239 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_0___bit 16 | |
240 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_1___lsb 17 | |
241 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_1___width 1 | |
242 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_1___bit 17 | |
243 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_2___lsb 18 | |
244 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_2___width 1 | |
245 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_2___bit 18 | |
246 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_3___lsb 19 | |
247 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_3___width 1 | |
248 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_3___bit 19 | |
249 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_4___lsb 20 | |
250 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_4___width 1 | |
251 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_4___bit 20 | |
252 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_5___lsb 21 | |
253 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_5___width 1 | |
254 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_5___bit 21 | |
255 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_6___lsb 22 | |
256 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_6___width 1 | |
257 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_6___bit 22 | |
258 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_7___lsb 23 | |
259 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_7___width 1 | |
260 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_7___bit 23 | |
261 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_8___lsb 24 | |
262 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_8___width 1 | |
263 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_8___bit 24 | |
264 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_9___lsb 25 | |
265 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_9___width 1 | |
266 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_9___bit 25 | |
267 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_10___lsb 26 | |
268 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_10___width 1 | |
269 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_10___bit 26 | |
270 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_11___lsb 27 | |
271 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_11___width 1 | |
272 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_11___bit 27 | |
273 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_12___lsb 28 | |
274 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_12___width 1 | |
275 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_12___bit 28 | |
276 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_13___lsb 29 | |
277 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_13___width 1 | |
278 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_13___bit 29 | |
279 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_14___lsb 30 | |
280 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_14___width 1 | |
281 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_14___bit 30 | |
282 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_15___lsb 31 | |
283 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_15___width 1 | |
284 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_15___bit 31 | |
285 | #define reg_iop_sw_cpu_rw_intr0_mask_offset 76 | |
286 | ||
287 | /* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ | |
288 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0 | |
289 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1 | |
290 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0 | |
291 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1 | |
292 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1 | |
293 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1 | |
294 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2 | |
295 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1 | |
296 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2 | |
297 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3 | |
298 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1 | |
299 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3 | |
300 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4 | |
301 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1 | |
302 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4 | |
303 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5 | |
304 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1 | |
305 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5 | |
306 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6 | |
307 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1 | |
308 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6 | |
309 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7 | |
310 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1 | |
311 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7 | |
312 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8 | |
313 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1 | |
314 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8 | |
315 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9 | |
316 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1 | |
317 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9 | |
318 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10 | |
319 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1 | |
320 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10 | |
321 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11 | |
322 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1 | |
323 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11 | |
324 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12 | |
325 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1 | |
326 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12 | |
327 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13 | |
328 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1 | |
329 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13 | |
330 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14 | |
331 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1 | |
332 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14 | |
333 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15 | |
334 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1 | |
335 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15 | |
336 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_0___lsb 16 | |
337 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_0___width 1 | |
338 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_0___bit 16 | |
339 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_1___lsb 17 | |
340 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_1___width 1 | |
341 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_1___bit 17 | |
342 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_2___lsb 18 | |
343 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_2___width 1 | |
344 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_2___bit 18 | |
345 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_3___lsb 19 | |
346 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_3___width 1 | |
347 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_3___bit 19 | |
348 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_4___lsb 20 | |
349 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_4___width 1 | |
350 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_4___bit 20 | |
351 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_5___lsb 21 | |
352 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_5___width 1 | |
353 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_5___bit 21 | |
354 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_6___lsb 22 | |
355 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_6___width 1 | |
356 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_6___bit 22 | |
357 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_7___lsb 23 | |
358 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_7___width 1 | |
359 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_7___bit 23 | |
360 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_8___lsb 24 | |
361 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_8___width 1 | |
362 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_8___bit 24 | |
363 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_9___lsb 25 | |
364 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_9___width 1 | |
365 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_9___bit 25 | |
366 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_10___lsb 26 | |
367 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_10___width 1 | |
368 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_10___bit 26 | |
369 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_11___lsb 27 | |
370 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_11___width 1 | |
371 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_11___bit 27 | |
372 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_12___lsb 28 | |
373 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_12___width 1 | |
374 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_12___bit 28 | |
375 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_13___lsb 29 | |
376 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_13___width 1 | |
377 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_13___bit 29 | |
378 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_14___lsb 30 | |
379 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_14___width 1 | |
380 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_14___bit 30 | |
381 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_15___lsb 31 | |
382 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_15___width 1 | |
383 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_15___bit 31 | |
384 | #define reg_iop_sw_cpu_rw_ack_intr0_offset 80 | |
385 | ||
386 | /* Register r_intr0, scope iop_sw_cpu, type r */ | |
387 | #define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0 | |
388 | #define reg_iop_sw_cpu_r_intr0___mpu_0___width 1 | |
389 | #define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0 | |
390 | #define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1 | |
391 | #define reg_iop_sw_cpu_r_intr0___mpu_1___width 1 | |
392 | #define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1 | |
393 | #define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2 | |
394 | #define reg_iop_sw_cpu_r_intr0___mpu_2___width 1 | |
395 | #define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2 | |
396 | #define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3 | |
397 | #define reg_iop_sw_cpu_r_intr0___mpu_3___width 1 | |
398 | #define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3 | |
399 | #define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4 | |
400 | #define reg_iop_sw_cpu_r_intr0___mpu_4___width 1 | |
401 | #define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4 | |
402 | #define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5 | |
403 | #define reg_iop_sw_cpu_r_intr0___mpu_5___width 1 | |
404 | #define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5 | |
405 | #define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6 | |
406 | #define reg_iop_sw_cpu_r_intr0___mpu_6___width 1 | |
407 | #define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6 | |
408 | #define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7 | |
409 | #define reg_iop_sw_cpu_r_intr0___mpu_7___width 1 | |
410 | #define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7 | |
411 | #define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8 | |
412 | #define reg_iop_sw_cpu_r_intr0___mpu_8___width 1 | |
413 | #define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8 | |
414 | #define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9 | |
415 | #define reg_iop_sw_cpu_r_intr0___mpu_9___width 1 | |
416 | #define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9 | |
417 | #define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10 | |
418 | #define reg_iop_sw_cpu_r_intr0___mpu_10___width 1 | |
419 | #define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10 | |
420 | #define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11 | |
421 | #define reg_iop_sw_cpu_r_intr0___mpu_11___width 1 | |
422 | #define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11 | |
423 | #define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12 | |
424 | #define reg_iop_sw_cpu_r_intr0___mpu_12___width 1 | |
425 | #define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12 | |
426 | #define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13 | |
427 | #define reg_iop_sw_cpu_r_intr0___mpu_13___width 1 | |
428 | #define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13 | |
429 | #define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14 | |
430 | #define reg_iop_sw_cpu_r_intr0___mpu_14___width 1 | |
431 | #define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14 | |
432 | #define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15 | |
433 | #define reg_iop_sw_cpu_r_intr0___mpu_15___width 1 | |
434 | #define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15 | |
435 | #define reg_iop_sw_cpu_r_intr0___spu_0___lsb 16 | |
436 | #define reg_iop_sw_cpu_r_intr0___spu_0___width 1 | |
437 | #define reg_iop_sw_cpu_r_intr0___spu_0___bit 16 | |
438 | #define reg_iop_sw_cpu_r_intr0___spu_1___lsb 17 | |
439 | #define reg_iop_sw_cpu_r_intr0___spu_1___width 1 | |
440 | #define reg_iop_sw_cpu_r_intr0___spu_1___bit 17 | |
441 | #define reg_iop_sw_cpu_r_intr0___spu_2___lsb 18 | |
442 | #define reg_iop_sw_cpu_r_intr0___spu_2___width 1 | |
443 | #define reg_iop_sw_cpu_r_intr0___spu_2___bit 18 | |
444 | #define reg_iop_sw_cpu_r_intr0___spu_3___lsb 19 | |
445 | #define reg_iop_sw_cpu_r_intr0___spu_3___width 1 | |
446 | #define reg_iop_sw_cpu_r_intr0___spu_3___bit 19 | |
447 | #define reg_iop_sw_cpu_r_intr0___spu_4___lsb 20 | |
448 | #define reg_iop_sw_cpu_r_intr0___spu_4___width 1 | |
449 | #define reg_iop_sw_cpu_r_intr0___spu_4___bit 20 | |
450 | #define reg_iop_sw_cpu_r_intr0___spu_5___lsb 21 | |
451 | #define reg_iop_sw_cpu_r_intr0___spu_5___width 1 | |
452 | #define reg_iop_sw_cpu_r_intr0___spu_5___bit 21 | |
453 | #define reg_iop_sw_cpu_r_intr0___spu_6___lsb 22 | |
454 | #define reg_iop_sw_cpu_r_intr0___spu_6___width 1 | |
455 | #define reg_iop_sw_cpu_r_intr0___spu_6___bit 22 | |
456 | #define reg_iop_sw_cpu_r_intr0___spu_7___lsb 23 | |
457 | #define reg_iop_sw_cpu_r_intr0___spu_7___width 1 | |
458 | #define reg_iop_sw_cpu_r_intr0___spu_7___bit 23 | |
459 | #define reg_iop_sw_cpu_r_intr0___spu_8___lsb 24 | |
460 | #define reg_iop_sw_cpu_r_intr0___spu_8___width 1 | |
461 | #define reg_iop_sw_cpu_r_intr0___spu_8___bit 24 | |
462 | #define reg_iop_sw_cpu_r_intr0___spu_9___lsb 25 | |
463 | #define reg_iop_sw_cpu_r_intr0___spu_9___width 1 | |
464 | #define reg_iop_sw_cpu_r_intr0___spu_9___bit 25 | |
465 | #define reg_iop_sw_cpu_r_intr0___spu_10___lsb 26 | |
466 | #define reg_iop_sw_cpu_r_intr0___spu_10___width 1 | |
467 | #define reg_iop_sw_cpu_r_intr0___spu_10___bit 26 | |
468 | #define reg_iop_sw_cpu_r_intr0___spu_11___lsb 27 | |
469 | #define reg_iop_sw_cpu_r_intr0___spu_11___width 1 | |
470 | #define reg_iop_sw_cpu_r_intr0___spu_11___bit 27 | |
471 | #define reg_iop_sw_cpu_r_intr0___spu_12___lsb 28 | |
472 | #define reg_iop_sw_cpu_r_intr0___spu_12___width 1 | |
473 | #define reg_iop_sw_cpu_r_intr0___spu_12___bit 28 | |
474 | #define reg_iop_sw_cpu_r_intr0___spu_13___lsb 29 | |
475 | #define reg_iop_sw_cpu_r_intr0___spu_13___width 1 | |
476 | #define reg_iop_sw_cpu_r_intr0___spu_13___bit 29 | |
477 | #define reg_iop_sw_cpu_r_intr0___spu_14___lsb 30 | |
478 | #define reg_iop_sw_cpu_r_intr0___spu_14___width 1 | |
479 | #define reg_iop_sw_cpu_r_intr0___spu_14___bit 30 | |
480 | #define reg_iop_sw_cpu_r_intr0___spu_15___lsb 31 | |
481 | #define reg_iop_sw_cpu_r_intr0___spu_15___width 1 | |
482 | #define reg_iop_sw_cpu_r_intr0___spu_15___bit 31 | |
483 | #define reg_iop_sw_cpu_r_intr0_offset 84 | |
484 | ||
485 | /* Register r_masked_intr0, scope iop_sw_cpu, type r */ | |
486 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0 | |
487 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1 | |
488 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0 | |
489 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1 | |
490 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1 | |
491 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1 | |
492 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2 | |
493 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1 | |
494 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2 | |
495 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3 | |
496 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1 | |
497 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3 | |
498 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4 | |
499 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1 | |
500 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4 | |
501 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5 | |
502 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1 | |
503 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5 | |
504 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6 | |
505 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1 | |
506 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6 | |
507 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7 | |
508 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1 | |
509 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7 | |
510 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8 | |
511 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1 | |
512 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8 | |
513 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9 | |
514 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1 | |
515 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9 | |
516 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10 | |
517 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1 | |
518 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10 | |
519 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11 | |
520 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1 | |
521 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11 | |
522 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12 | |
523 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1 | |
524 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12 | |
525 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13 | |
526 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1 | |
527 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13 | |
528 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14 | |
529 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1 | |
530 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14 | |
531 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15 | |
532 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1 | |
533 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15 | |
534 | #define reg_iop_sw_cpu_r_masked_intr0___spu_0___lsb 16 | |
535 | #define reg_iop_sw_cpu_r_masked_intr0___spu_0___width 1 | |
536 | #define reg_iop_sw_cpu_r_masked_intr0___spu_0___bit 16 | |
537 | #define reg_iop_sw_cpu_r_masked_intr0___spu_1___lsb 17 | |
538 | #define reg_iop_sw_cpu_r_masked_intr0___spu_1___width 1 | |
539 | #define reg_iop_sw_cpu_r_masked_intr0___spu_1___bit 17 | |
540 | #define reg_iop_sw_cpu_r_masked_intr0___spu_2___lsb 18 | |
541 | #define reg_iop_sw_cpu_r_masked_intr0___spu_2___width 1 | |
542 | #define reg_iop_sw_cpu_r_masked_intr0___spu_2___bit 18 | |
543 | #define reg_iop_sw_cpu_r_masked_intr0___spu_3___lsb 19 | |
544 | #define reg_iop_sw_cpu_r_masked_intr0___spu_3___width 1 | |
545 | #define reg_iop_sw_cpu_r_masked_intr0___spu_3___bit 19 | |
546 | #define reg_iop_sw_cpu_r_masked_intr0___spu_4___lsb 20 | |
547 | #define reg_iop_sw_cpu_r_masked_intr0___spu_4___width 1 | |
548 | #define reg_iop_sw_cpu_r_masked_intr0___spu_4___bit 20 | |
549 | #define reg_iop_sw_cpu_r_masked_intr0___spu_5___lsb 21 | |
550 | #define reg_iop_sw_cpu_r_masked_intr0___spu_5___width 1 | |
551 | #define reg_iop_sw_cpu_r_masked_intr0___spu_5___bit 21 | |
552 | #define reg_iop_sw_cpu_r_masked_intr0___spu_6___lsb 22 | |
553 | #define reg_iop_sw_cpu_r_masked_intr0___spu_6___width 1 | |
554 | #define reg_iop_sw_cpu_r_masked_intr0___spu_6___bit 22 | |
555 | #define reg_iop_sw_cpu_r_masked_intr0___spu_7___lsb 23 | |
556 | #define reg_iop_sw_cpu_r_masked_intr0___spu_7___width 1 | |
557 | #define reg_iop_sw_cpu_r_masked_intr0___spu_7___bit 23 | |
558 | #define reg_iop_sw_cpu_r_masked_intr0___spu_8___lsb 24 | |
559 | #define reg_iop_sw_cpu_r_masked_intr0___spu_8___width 1 | |
560 | #define reg_iop_sw_cpu_r_masked_intr0___spu_8___bit 24 | |
561 | #define reg_iop_sw_cpu_r_masked_intr0___spu_9___lsb 25 | |
562 | #define reg_iop_sw_cpu_r_masked_intr0___spu_9___width 1 | |
563 | #define reg_iop_sw_cpu_r_masked_intr0___spu_9___bit 25 | |
564 | #define reg_iop_sw_cpu_r_masked_intr0___spu_10___lsb 26 | |
565 | #define reg_iop_sw_cpu_r_masked_intr0___spu_10___width 1 | |
566 | #define reg_iop_sw_cpu_r_masked_intr0___spu_10___bit 26 | |
567 | #define reg_iop_sw_cpu_r_masked_intr0___spu_11___lsb 27 | |
568 | #define reg_iop_sw_cpu_r_masked_intr0___spu_11___width 1 | |
569 | #define reg_iop_sw_cpu_r_masked_intr0___spu_11___bit 27 | |
570 | #define reg_iop_sw_cpu_r_masked_intr0___spu_12___lsb 28 | |
571 | #define reg_iop_sw_cpu_r_masked_intr0___spu_12___width 1 | |
572 | #define reg_iop_sw_cpu_r_masked_intr0___spu_12___bit 28 | |
573 | #define reg_iop_sw_cpu_r_masked_intr0___spu_13___lsb 29 | |
574 | #define reg_iop_sw_cpu_r_masked_intr0___spu_13___width 1 | |
575 | #define reg_iop_sw_cpu_r_masked_intr0___spu_13___bit 29 | |
576 | #define reg_iop_sw_cpu_r_masked_intr0___spu_14___lsb 30 | |
577 | #define reg_iop_sw_cpu_r_masked_intr0___spu_14___width 1 | |
578 | #define reg_iop_sw_cpu_r_masked_intr0___spu_14___bit 30 | |
579 | #define reg_iop_sw_cpu_r_masked_intr0___spu_15___lsb 31 | |
580 | #define reg_iop_sw_cpu_r_masked_intr0___spu_15___width 1 | |
581 | #define reg_iop_sw_cpu_r_masked_intr0___spu_15___bit 31 | |
582 | #define reg_iop_sw_cpu_r_masked_intr0_offset 88 | |
583 | ||
584 | /* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ | |
585 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0 | |
586 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1 | |
587 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0 | |
588 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1 | |
589 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1 | |
590 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1 | |
591 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2 | |
592 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1 | |
593 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2 | |
594 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3 | |
595 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1 | |
596 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3 | |
597 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4 | |
598 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1 | |
599 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4 | |
600 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5 | |
601 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1 | |
602 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5 | |
603 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6 | |
604 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1 | |
605 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6 | |
606 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7 | |
607 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1 | |
608 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7 | |
609 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8 | |
610 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1 | |
611 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8 | |
612 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9 | |
613 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1 | |
614 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9 | |
615 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10 | |
616 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1 | |
617 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10 | |
618 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11 | |
619 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1 | |
620 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11 | |
621 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12 | |
622 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1 | |
623 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12 | |
624 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13 | |
625 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1 | |
626 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13 | |
627 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14 | |
628 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1 | |
629 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14 | |
630 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15 | |
631 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1 | |
632 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15 | |
633 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___lsb 16 | |
634 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___width 1 | |
635 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___bit 16 | |
636 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___lsb 17 | |
637 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___width 1 | |
638 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___bit 17 | |
639 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___lsb 18 | |
640 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___width 1 | |
641 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___bit 18 | |
642 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___lsb 19 | |
643 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___width 1 | |
644 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___bit 19 | |
645 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___lsb 20 | |
646 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___width 1 | |
647 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___bit 20 | |
648 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___lsb 21 | |
649 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___width 1 | |
650 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___bit 21 | |
651 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___lsb 22 | |
652 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___width 1 | |
653 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___bit 22 | |
654 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___lsb 23 | |
655 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___width 1 | |
656 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___bit 23 | |
657 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___lsb 24 | |
658 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___width 1 | |
659 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___bit 24 | |
660 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___lsb 25 | |
661 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___width 1 | |
662 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___bit 25 | |
663 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___lsb 26 | |
664 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___width 1 | |
665 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___bit 26 | |
666 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___lsb 27 | |
667 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___width 1 | |
668 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___bit 27 | |
669 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___lsb 28 | |
670 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___width 1 | |
671 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___bit 28 | |
672 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___lsb 29 | |
673 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___width 1 | |
674 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___bit 29 | |
675 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___lsb 30 | |
676 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___width 1 | |
677 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___bit 30 | |
678 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___lsb 31 | |
679 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___width 1 | |
680 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___bit 31 | |
681 | #define reg_iop_sw_cpu_rw_intr1_mask_offset 92 | |
682 | ||
683 | /* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ | |
684 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0 | |
685 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1 | |
686 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0 | |
687 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1 | |
688 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1 | |
689 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1 | |
690 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2 | |
691 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1 | |
692 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2 | |
693 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3 | |
694 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1 | |
695 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3 | |
696 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4 | |
697 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1 | |
698 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4 | |
699 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5 | |
700 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1 | |
701 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5 | |
702 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6 | |
703 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1 | |
704 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6 | |
705 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7 | |
706 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1 | |
707 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7 | |
708 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8 | |
709 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1 | |
710 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8 | |
711 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9 | |
712 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1 | |
713 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9 | |
714 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10 | |
715 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1 | |
716 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10 | |
717 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11 | |
718 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1 | |
719 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11 | |
720 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12 | |
721 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1 | |
722 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12 | |
723 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13 | |
724 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1 | |
725 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13 | |
726 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14 | |
727 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1 | |
728 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14 | |
729 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15 | |
730 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1 | |
731 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15 | |
732 | #define reg_iop_sw_cpu_rw_ack_intr1_offset 96 | |
733 | ||
734 | /* Register r_intr1, scope iop_sw_cpu, type r */ | |
735 | #define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0 | |
736 | #define reg_iop_sw_cpu_r_intr1___mpu_16___width 1 | |
737 | #define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0 | |
738 | #define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1 | |
739 | #define reg_iop_sw_cpu_r_intr1___mpu_17___width 1 | |
740 | #define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1 | |
741 | #define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2 | |
742 | #define reg_iop_sw_cpu_r_intr1___mpu_18___width 1 | |
743 | #define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2 | |
744 | #define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3 | |
745 | #define reg_iop_sw_cpu_r_intr1___mpu_19___width 1 | |
746 | #define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3 | |
747 | #define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4 | |
748 | #define reg_iop_sw_cpu_r_intr1___mpu_20___width 1 | |
749 | #define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4 | |
750 | #define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5 | |
751 | #define reg_iop_sw_cpu_r_intr1___mpu_21___width 1 | |
752 | #define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5 | |
753 | #define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6 | |
754 | #define reg_iop_sw_cpu_r_intr1___mpu_22___width 1 | |
755 | #define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6 | |
756 | #define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7 | |
757 | #define reg_iop_sw_cpu_r_intr1___mpu_23___width 1 | |
758 | #define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7 | |
759 | #define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8 | |
760 | #define reg_iop_sw_cpu_r_intr1___mpu_24___width 1 | |
761 | #define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8 | |
762 | #define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9 | |
763 | #define reg_iop_sw_cpu_r_intr1___mpu_25___width 1 | |
764 | #define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9 | |
765 | #define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10 | |
766 | #define reg_iop_sw_cpu_r_intr1___mpu_26___width 1 | |
767 | #define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10 | |
768 | #define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11 | |
769 | #define reg_iop_sw_cpu_r_intr1___mpu_27___width 1 | |
770 | #define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11 | |
771 | #define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12 | |
772 | #define reg_iop_sw_cpu_r_intr1___mpu_28___width 1 | |
773 | #define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12 | |
774 | #define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13 | |
775 | #define reg_iop_sw_cpu_r_intr1___mpu_29___width 1 | |
776 | #define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13 | |
777 | #define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14 | |
778 | #define reg_iop_sw_cpu_r_intr1___mpu_30___width 1 | |
779 | #define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14 | |
780 | #define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15 | |
781 | #define reg_iop_sw_cpu_r_intr1___mpu_31___width 1 | |
782 | #define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15 | |
783 | #define reg_iop_sw_cpu_r_intr1___dmc_in___lsb 16 | |
784 | #define reg_iop_sw_cpu_r_intr1___dmc_in___width 1 | |
785 | #define reg_iop_sw_cpu_r_intr1___dmc_in___bit 16 | |
786 | #define reg_iop_sw_cpu_r_intr1___dmc_out___lsb 17 | |
787 | #define reg_iop_sw_cpu_r_intr1___dmc_out___width 1 | |
788 | #define reg_iop_sw_cpu_r_intr1___dmc_out___bit 17 | |
789 | #define reg_iop_sw_cpu_r_intr1___fifo_in___lsb 18 | |
790 | #define reg_iop_sw_cpu_r_intr1___fifo_in___width 1 | |
791 | #define reg_iop_sw_cpu_r_intr1___fifo_in___bit 18 | |
792 | #define reg_iop_sw_cpu_r_intr1___fifo_out___lsb 19 | |
793 | #define reg_iop_sw_cpu_r_intr1___fifo_out___width 1 | |
794 | #define reg_iop_sw_cpu_r_intr1___fifo_out___bit 19 | |
795 | #define reg_iop_sw_cpu_r_intr1___fifo_in_extra___lsb 20 | |
796 | #define reg_iop_sw_cpu_r_intr1___fifo_in_extra___width 1 | |
797 | #define reg_iop_sw_cpu_r_intr1___fifo_in_extra___bit 20 | |
798 | #define reg_iop_sw_cpu_r_intr1___fifo_out_extra___lsb 21 | |
799 | #define reg_iop_sw_cpu_r_intr1___fifo_out_extra___width 1 | |
800 | #define reg_iop_sw_cpu_r_intr1___fifo_out_extra___bit 21 | |
801 | #define reg_iop_sw_cpu_r_intr1___trigger_grp0___lsb 22 | |
802 | #define reg_iop_sw_cpu_r_intr1___trigger_grp0___width 1 | |
803 | #define reg_iop_sw_cpu_r_intr1___trigger_grp0___bit 22 | |
804 | #define reg_iop_sw_cpu_r_intr1___trigger_grp1___lsb 23 | |
805 | #define reg_iop_sw_cpu_r_intr1___trigger_grp1___width 1 | |
806 | #define reg_iop_sw_cpu_r_intr1___trigger_grp1___bit 23 | |
807 | #define reg_iop_sw_cpu_r_intr1___trigger_grp2___lsb 24 | |
808 | #define reg_iop_sw_cpu_r_intr1___trigger_grp2___width 1 | |
809 | #define reg_iop_sw_cpu_r_intr1___trigger_grp2___bit 24 | |
810 | #define reg_iop_sw_cpu_r_intr1___trigger_grp3___lsb 25 | |
811 | #define reg_iop_sw_cpu_r_intr1___trigger_grp3___width 1 | |
812 | #define reg_iop_sw_cpu_r_intr1___trigger_grp3___bit 25 | |
813 | #define reg_iop_sw_cpu_r_intr1___trigger_grp4___lsb 26 | |
814 | #define reg_iop_sw_cpu_r_intr1___trigger_grp4___width 1 | |
815 | #define reg_iop_sw_cpu_r_intr1___trigger_grp4___bit 26 | |
816 | #define reg_iop_sw_cpu_r_intr1___trigger_grp5___lsb 27 | |
817 | #define reg_iop_sw_cpu_r_intr1___trigger_grp5___width 1 | |
818 | #define reg_iop_sw_cpu_r_intr1___trigger_grp5___bit 27 | |
819 | #define reg_iop_sw_cpu_r_intr1___trigger_grp6___lsb 28 | |
820 | #define reg_iop_sw_cpu_r_intr1___trigger_grp6___width 1 | |
821 | #define reg_iop_sw_cpu_r_intr1___trigger_grp6___bit 28 | |
822 | #define reg_iop_sw_cpu_r_intr1___trigger_grp7___lsb 29 | |
823 | #define reg_iop_sw_cpu_r_intr1___trigger_grp7___width 1 | |
824 | #define reg_iop_sw_cpu_r_intr1___trigger_grp7___bit 29 | |
825 | #define reg_iop_sw_cpu_r_intr1___timer_grp0___lsb 30 | |
826 | #define reg_iop_sw_cpu_r_intr1___timer_grp0___width 1 | |
827 | #define reg_iop_sw_cpu_r_intr1___timer_grp0___bit 30 | |
828 | #define reg_iop_sw_cpu_r_intr1___timer_grp1___lsb 31 | |
829 | #define reg_iop_sw_cpu_r_intr1___timer_grp1___width 1 | |
830 | #define reg_iop_sw_cpu_r_intr1___timer_grp1___bit 31 | |
831 | #define reg_iop_sw_cpu_r_intr1_offset 100 | |
832 | ||
833 | /* Register r_masked_intr1, scope iop_sw_cpu, type r */ | |
834 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0 | |
835 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1 | |
836 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0 | |
837 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1 | |
838 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1 | |
839 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1 | |
840 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2 | |
841 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1 | |
842 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2 | |
843 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3 | |
844 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1 | |
845 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3 | |
846 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4 | |
847 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1 | |
848 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4 | |
849 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5 | |
850 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1 | |
851 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5 | |
852 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6 | |
853 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1 | |
854 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6 | |
855 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7 | |
856 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1 | |
857 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7 | |
858 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8 | |
859 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1 | |
860 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8 | |
861 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9 | |
862 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1 | |
863 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9 | |
864 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10 | |
865 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1 | |
866 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10 | |
867 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11 | |
868 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1 | |
869 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11 | |
870 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12 | |
871 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1 | |
872 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12 | |
873 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13 | |
874 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1 | |
875 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13 | |
876 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14 | |
877 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1 | |
878 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14 | |
879 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15 | |
880 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1 | |
881 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15 | |
882 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_in___lsb 16 | |
883 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_in___width 1 | |
884 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_in___bit 16 | |
885 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_out___lsb 17 | |
886 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_out___width 1 | |
887 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_out___bit 17 | |
888 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in___lsb 18 | |
889 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in___width 1 | |
890 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in___bit 18 | |
891 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out___lsb 19 | |
892 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out___width 1 | |
893 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out___bit 19 | |
894 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___lsb 20 | |
895 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___width 1 | |
896 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___bit 20 | |
897 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___lsb 21 | |
898 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___width 1 | |
899 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___bit 21 | |
900 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___lsb 22 | |
901 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___width 1 | |
902 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___bit 22 | |
903 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___lsb 23 | |
904 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___width 1 | |
905 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___bit 23 | |
906 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___lsb 24 | |
907 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___width 1 | |
908 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___bit 24 | |
909 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___lsb 25 | |
910 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___width 1 | |
911 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___bit 25 | |
912 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___lsb 26 | |
913 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___width 1 | |
914 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___bit 26 | |
915 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___lsb 27 | |
916 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___width 1 | |
917 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___bit 27 | |
918 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___lsb 28 | |
919 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___width 1 | |
920 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___bit 28 | |
921 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___lsb 29 | |
922 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___width 1 | |
923 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___bit 29 | |
924 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___lsb 30 | |
925 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___width 1 | |
926 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___bit 30 | |
927 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___lsb 31 | |
928 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___width 1 | |
929 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___bit 31 | |
930 | #define reg_iop_sw_cpu_r_masked_intr1_offset 104 | |
931 | ||
932 | ||
933 | /* Constants */ | |
934 | #define regk_iop_sw_cpu_copy 0x00000000 | |
935 | #define regk_iop_sw_cpu_no 0x00000000 | |
936 | #define regk_iop_sw_cpu_rd 0x00000002 | |
937 | #define regk_iop_sw_cpu_reg_copy 0x00000001 | |
938 | #define regk_iop_sw_cpu_rw_bus_clr_mask_default 0x00000000 | |
939 | #define regk_iop_sw_cpu_rw_bus_oe_clr_mask_default 0x00000000 | |
940 | #define regk_iop_sw_cpu_rw_bus_oe_set_mask_default 0x00000000 | |
941 | #define regk_iop_sw_cpu_rw_bus_set_mask_default 0x00000000 | |
942 | #define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000 | |
943 | #define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000 | |
944 | #define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000 | |
945 | #define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000 | |
946 | #define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000 | |
947 | #define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000 | |
948 | #define regk_iop_sw_cpu_wr 0x00000003 | |
949 | #define regk_iop_sw_cpu_yes 0x00000001 | |
950 | #endif /* __iop_sw_cpu_defs_asm_h */ |