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58d08319 JN |
1 | #ifndef __iop_sw_cfg_defs_asm_h |
2 | #define __iop_sw_cfg_defs_asm_h | |
3 | ||
4 | /* | |
5 | * This file is autogenerated from | |
6 | * file: iop_sw_cfg.r | |
7 | * | |
8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cfg_defs_asm.h iop_sw_cfg.r | |
9 | * Any changes here will be lost. | |
10 | * | |
11 | * -*- buffer-read-only: t -*- | |
12 | */ | |
13 | ||
14 | #ifndef REG_FIELD | |
15 | #define REG_FIELD( scope, reg, field, value ) \ | |
16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | |
17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | |
18 | #endif | |
19 | ||
20 | #ifndef REG_STATE | |
21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | |
22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | |
23 | #define REG_STATE_X_( k, shift ) (k << shift) | |
24 | #endif | |
25 | ||
26 | #ifndef REG_MASK | |
27 | #define REG_MASK( scope, reg, field ) \ | |
28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | |
29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | |
30 | #endif | |
31 | ||
32 | #ifndef REG_LSB | |
33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | |
34 | #endif | |
35 | ||
36 | #ifndef REG_BIT | |
37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | |
38 | #endif | |
39 | ||
40 | #ifndef REG_ADDR | |
41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | |
42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | |
43 | #endif | |
44 | ||
45 | #ifndef REG_ADDR_VECT | |
46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | |
48 | STRIDE_##scope##_##reg ) | |
49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | |
50 | ((inst) + offs + (index) * stride) | |
51 | #endif | |
52 | ||
53 | /* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ | |
54 | #define reg_iop_sw_cfg_rw_crc_par_owner___cfg___lsb 0 | |
55 | #define reg_iop_sw_cfg_rw_crc_par_owner___cfg___width 2 | |
56 | #define reg_iop_sw_cfg_rw_crc_par_owner_offset 0 | |
57 | ||
58 | /* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ | |
59 | #define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___lsb 0 | |
60 | #define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___width 2 | |
61 | #define reg_iop_sw_cfg_rw_dmc_in_owner_offset 4 | |
62 | ||
63 | /* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ | |
64 | #define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___lsb 0 | |
65 | #define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___width 2 | |
66 | #define reg_iop_sw_cfg_rw_dmc_out_owner_offset 8 | |
67 | ||
68 | /* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ | |
69 | #define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___lsb 0 | |
70 | #define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___width 2 | |
71 | #define reg_iop_sw_cfg_rw_fifo_in_owner_offset 12 | |
72 | ||
73 | /* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ | |
74 | #define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___lsb 0 | |
75 | #define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___width 2 | |
76 | #define reg_iop_sw_cfg_rw_fifo_in_extra_owner_offset 16 | |
77 | ||
78 | /* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ | |
79 | #define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___lsb 0 | |
80 | #define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___width 2 | |
81 | #define reg_iop_sw_cfg_rw_fifo_out_owner_offset 20 | |
82 | ||
83 | /* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ | |
84 | #define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___lsb 0 | |
85 | #define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___width 2 | |
86 | #define reg_iop_sw_cfg_rw_fifo_out_extra_owner_offset 24 | |
87 | ||
88 | /* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ | |
89 | #define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0 | |
90 | #define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2 | |
91 | #define reg_iop_sw_cfg_rw_sap_in_owner_offset 28 | |
92 | ||
93 | /* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ | |
94 | #define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0 | |
95 | #define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2 | |
96 | #define reg_iop_sw_cfg_rw_sap_out_owner_offset 32 | |
97 | ||
98 | /* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ | |
99 | #define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___lsb 0 | |
100 | #define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___width 2 | |
101 | #define reg_iop_sw_cfg_rw_scrc_in_owner_offset 36 | |
102 | ||
103 | /* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ | |
104 | #define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___lsb 0 | |
105 | #define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___width 2 | |
106 | #define reg_iop_sw_cfg_rw_scrc_out_owner_offset 40 | |
107 | ||
108 | /* Register rw_spu_owner, scope iop_sw_cfg, type rw */ | |
109 | #define reg_iop_sw_cfg_rw_spu_owner___cfg___lsb 0 | |
110 | #define reg_iop_sw_cfg_rw_spu_owner___cfg___width 1 | |
111 | #define reg_iop_sw_cfg_rw_spu_owner___cfg___bit 0 | |
112 | #define reg_iop_sw_cfg_rw_spu_owner_offset 44 | |
113 | ||
114 | /* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ | |
115 | #define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0 | |
116 | #define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2 | |
117 | #define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 48 | |
118 | ||
119 | /* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ | |
120 | #define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0 | |
121 | #define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2 | |
122 | #define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 52 | |
123 | ||
124 | /* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ | |
125 | #define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0 | |
126 | #define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2 | |
127 | #define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 56 | |
128 | ||
129 | /* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ | |
130 | #define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0 | |
131 | #define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2 | |
132 | #define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 60 | |
133 | ||
134 | /* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ | |
135 | #define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0 | |
136 | #define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2 | |
137 | #define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 64 | |
138 | ||
139 | /* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ | |
140 | #define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0 | |
141 | #define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2 | |
142 | #define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 68 | |
143 | ||
144 | /* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ | |
145 | #define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0 | |
146 | #define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2 | |
147 | #define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 72 | |
148 | ||
149 | /* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ | |
150 | #define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0 | |
151 | #define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2 | |
152 | #define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 76 | |
153 | ||
154 | /* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ | |
155 | #define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0 | |
156 | #define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2 | |
157 | #define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 80 | |
158 | ||
159 | /* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ | |
160 | #define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0 | |
161 | #define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2 | |
162 | #define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 84 | |
163 | ||
164 | /* Register rw_bus_mask, scope iop_sw_cfg, type rw */ | |
165 | #define reg_iop_sw_cfg_rw_bus_mask___byte0___lsb 0 | |
166 | #define reg_iop_sw_cfg_rw_bus_mask___byte0___width 8 | |
167 | #define reg_iop_sw_cfg_rw_bus_mask___byte1___lsb 8 | |
168 | #define reg_iop_sw_cfg_rw_bus_mask___byte1___width 8 | |
169 | #define reg_iop_sw_cfg_rw_bus_mask___byte2___lsb 16 | |
170 | #define reg_iop_sw_cfg_rw_bus_mask___byte2___width 8 | |
171 | #define reg_iop_sw_cfg_rw_bus_mask___byte3___lsb 24 | |
172 | #define reg_iop_sw_cfg_rw_bus_mask___byte3___width 8 | |
173 | #define reg_iop_sw_cfg_rw_bus_mask_offset 88 | |
174 | ||
175 | /* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ | |
176 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___lsb 0 | |
177 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___width 1 | |
178 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___bit 0 | |
179 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___lsb 1 | |
180 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___width 1 | |
181 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___bit 1 | |
182 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___lsb 2 | |
183 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___width 1 | |
184 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___bit 2 | |
185 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___lsb 3 | |
186 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___width 1 | |
187 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___bit 3 | |
188 | #define reg_iop_sw_cfg_rw_bus_oe_mask_offset 92 | |
189 | ||
190 | /* Register rw_gio_mask, scope iop_sw_cfg, type rw */ | |
191 | #define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0 | |
192 | #define reg_iop_sw_cfg_rw_gio_mask___val___width 32 | |
193 | #define reg_iop_sw_cfg_rw_gio_mask_offset 96 | |
194 | ||
195 | /* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ | |
196 | #define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0 | |
197 | #define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32 | |
198 | #define reg_iop_sw_cfg_rw_gio_oe_mask_offset 100 | |
199 | ||
200 | /* Register rw_pinmapping, scope iop_sw_cfg, type rw */ | |
201 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___lsb 0 | |
202 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___width 2 | |
203 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___lsb 2 | |
204 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___width 2 | |
205 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___lsb 4 | |
206 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___width 2 | |
207 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___lsb 6 | |
208 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___width 2 | |
209 | #define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 8 | |
210 | #define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2 | |
211 | #define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 10 | |
212 | #define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2 | |
213 | #define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 12 | |
214 | #define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2 | |
215 | #define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 14 | |
216 | #define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2 | |
217 | #define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 16 | |
218 | #define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2 | |
219 | #define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 18 | |
220 | #define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2 | |
221 | #define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 20 | |
222 | #define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2 | |
223 | #define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 22 | |
224 | #define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2 | |
225 | #define reg_iop_sw_cfg_rw_pinmapping_offset 104 | |
226 | ||
227 | /* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ | |
228 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___lsb 0 | |
229 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___width 2 | |
230 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___lsb 2 | |
231 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___width 2 | |
232 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___lsb 4 | |
233 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___width 2 | |
234 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___lsb 6 | |
235 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___width 2 | |
236 | #define reg_iop_sw_cfg_rw_bus_out_cfg_offset 108 | |
237 | ||
238 | /* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ | |
239 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0 | |
240 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 3 | |
241 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 3 | |
242 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 1 | |
243 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___bit 3 | |
244 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 4 | |
245 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 3 | |
246 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 7 | |
247 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 1 | |
248 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___bit 7 | |
249 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 8 | |
250 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 3 | |
251 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 11 | |
252 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 1 | |
253 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___bit 11 | |
254 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 12 | |
255 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 3 | |
256 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 15 | |
257 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 1 | |
258 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___bit 15 | |
259 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 112 | |
260 | ||
261 | /* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ | |
262 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0 | |
263 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 3 | |
264 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 3 | |
265 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 1 | |
266 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___bit 3 | |
267 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 4 | |
268 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 3 | |
269 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 7 | |
270 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 1 | |
271 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___bit 7 | |
272 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 8 | |
273 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 3 | |
274 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 11 | |
275 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 1 | |
276 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___bit 11 | |
277 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 12 | |
278 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 3 | |
279 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 15 | |
280 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 1 | |
281 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___bit 15 | |
282 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 116 | |
283 | ||
284 | /* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ | |
285 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0 | |
286 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 3 | |
287 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 3 | |
288 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 1 | |
289 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___bit 3 | |
290 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 4 | |
291 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 3 | |
292 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 7 | |
293 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 1 | |
294 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___bit 7 | |
295 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 8 | |
296 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 3 | |
297 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 11 | |
298 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 1 | |
299 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___bit 11 | |
300 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 12 | |
301 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 3 | |
302 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 15 | |
303 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 1 | |
304 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___bit 15 | |
305 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 120 | |
306 | ||
307 | /* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ | |
308 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0 | |
309 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 3 | |
310 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 3 | |
311 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 1 | |
312 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___bit 3 | |
313 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 4 | |
314 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 3 | |
315 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 7 | |
316 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 1 | |
317 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___bit 7 | |
318 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 8 | |
319 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 3 | |
320 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 11 | |
321 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 1 | |
322 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___bit 11 | |
323 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 12 | |
324 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 3 | |
325 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 15 | |
326 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 1 | |
327 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___bit 15 | |
328 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 124 | |
329 | ||
330 | /* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ | |
331 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0 | |
332 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 3 | |
333 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 3 | |
334 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 1 | |
335 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___bit 3 | |
336 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 4 | |
337 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 3 | |
338 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 7 | |
339 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 1 | |
340 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___bit 7 | |
341 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 8 | |
342 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 3 | |
343 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 11 | |
344 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 1 | |
345 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___bit 11 | |
346 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 12 | |
347 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 3 | |
348 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 15 | |
349 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 1 | |
350 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___bit 15 | |
351 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 128 | |
352 | ||
353 | /* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ | |
354 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0 | |
355 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 3 | |
356 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 3 | |
357 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 1 | |
358 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___bit 3 | |
359 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 4 | |
360 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 3 | |
361 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 7 | |
362 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 1 | |
363 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___bit 7 | |
364 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 8 | |
365 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 3 | |
366 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 11 | |
367 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 1 | |
368 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___bit 11 | |
369 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 12 | |
370 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 3 | |
371 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 15 | |
372 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 1 | |
373 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___bit 15 | |
374 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 132 | |
375 | ||
376 | /* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ | |
377 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0 | |
378 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 3 | |
379 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 3 | |
380 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 1 | |
381 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___bit 3 | |
382 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 4 | |
383 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 3 | |
384 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 7 | |
385 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 1 | |
386 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___bit 7 | |
387 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 8 | |
388 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 3 | |
389 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 11 | |
390 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 1 | |
391 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___bit 11 | |
392 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 12 | |
393 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 3 | |
394 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 15 | |
395 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 1 | |
396 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___bit 15 | |
397 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 136 | |
398 | ||
399 | /* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ | |
400 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0 | |
401 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 3 | |
402 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 3 | |
403 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 1 | |
404 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___bit 3 | |
405 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 4 | |
406 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 3 | |
407 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 7 | |
408 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 1 | |
409 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___bit 7 | |
410 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 8 | |
411 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 3 | |
412 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 11 | |
413 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 1 | |
414 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___bit 11 | |
415 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 12 | |
416 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 3 | |
417 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 15 | |
418 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 1 | |
419 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___bit 15 | |
420 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 140 | |
421 | ||
422 | /* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ | |
423 | #define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___lsb 0 | |
424 | #define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___width 1 | |
425 | #define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___bit 0 | |
426 | #define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___lsb 1 | |
427 | #define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___width 1 | |
428 | #define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___bit 1 | |
429 | #define reg_iop_sw_cfg_rw_spu_cfg_offset 144 | |
430 | ||
431 | /* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ | |
432 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0 | |
433 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3 | |
434 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3 | |
435 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 2 | |
436 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 5 | |
437 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 2 | |
438 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 7 | |
439 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 2 | |
440 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 9 | |
441 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 2 | |
442 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 11 | |
443 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 2 | |
444 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 13 | |
445 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 2 | |
446 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 15 | |
447 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 2 | |
448 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 17 | |
449 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 2 | |
450 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 148 | |
451 | ||
452 | /* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ | |
453 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0 | |
454 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3 | |
455 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3 | |
456 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 2 | |
457 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 5 | |
458 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 2 | |
459 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 7 | |
460 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 2 | |
461 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 9 | |
462 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 2 | |
463 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 11 | |
464 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 2 | |
465 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 13 | |
466 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 2 | |
467 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 15 | |
468 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 2 | |
469 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 17 | |
470 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 2 | |
471 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 152 | |
472 | ||
473 | /* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ | |
474 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0 | |
475 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1 | |
476 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0 | |
477 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1 | |
478 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1 | |
479 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1 | |
480 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2 | |
481 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1 | |
482 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2 | |
483 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3 | |
484 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1 | |
485 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3 | |
486 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4 | |
487 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1 | |
488 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4 | |
489 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5 | |
490 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1 | |
491 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5 | |
492 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6 | |
493 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1 | |
494 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6 | |
495 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7 | |
496 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1 | |
497 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7 | |
498 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8 | |
499 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1 | |
500 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8 | |
501 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9 | |
502 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1 | |
503 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9 | |
504 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10 | |
505 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1 | |
506 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10 | |
507 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11 | |
508 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1 | |
509 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11 | |
510 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12 | |
511 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1 | |
512 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12 | |
513 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13 | |
514 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1 | |
515 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13 | |
516 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14 | |
517 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1 | |
518 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14 | |
519 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15 | |
520 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1 | |
521 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15 | |
522 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 156 | |
523 | ||
524 | /* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ | |
525 | #define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___lsb 0 | |
526 | #define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___width 4 | |
527 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_src___lsb 4 | |
528 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_src___width 2 | |
529 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_size___lsb 6 | |
530 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_size___width 3 | |
531 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_last___lsb 9 | |
532 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_last___width 2 | |
533 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___lsb 11 | |
534 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___width 4 | |
535 | #define reg_iop_sw_cfg_rw_pdp_cfg_offset 160 | |
536 | ||
537 | /* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ | |
538 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___lsb 0 | |
539 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___width 3 | |
540 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___lsb 3 | |
541 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___width 3 | |
542 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___lsb 6 | |
543 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___width 2 | |
544 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___lsb 8 | |
545 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___width 3 | |
546 | #define reg_iop_sw_cfg_rw_sdp_cfg_offset 164 | |
547 | ||
548 | ||
549 | /* Constants */ | |
550 | #define regk_iop_sw_cfg_a 0x00000001 | |
551 | #define regk_iop_sw_cfg_b 0x00000002 | |
552 | #define regk_iop_sw_cfg_bus 0x00000000 | |
553 | #define regk_iop_sw_cfg_bus_rot16 0x00000002 | |
554 | #define regk_iop_sw_cfg_bus_rot24 0x00000003 | |
555 | #define regk_iop_sw_cfg_bus_rot8 0x00000001 | |
556 | #define regk_iop_sw_cfg_clk12 0x00000000 | |
557 | #define regk_iop_sw_cfg_cpu 0x00000000 | |
558 | #define regk_iop_sw_cfg_gated_clk0 0x0000000e | |
559 | #define regk_iop_sw_cfg_gated_clk1 0x0000000f | |
560 | #define regk_iop_sw_cfg_gio0 0x00000004 | |
561 | #define regk_iop_sw_cfg_gio1 0x00000001 | |
562 | #define regk_iop_sw_cfg_gio2 0x00000005 | |
563 | #define regk_iop_sw_cfg_gio3 0x00000002 | |
564 | #define regk_iop_sw_cfg_gio4 0x00000006 | |
565 | #define regk_iop_sw_cfg_gio5 0x00000003 | |
566 | #define regk_iop_sw_cfg_gio6 0x00000007 | |
567 | #define regk_iop_sw_cfg_gio7 0x00000004 | |
568 | #define regk_iop_sw_cfg_gio_in18 0x00000002 | |
569 | #define regk_iop_sw_cfg_gio_in19 0x00000003 | |
570 | #define regk_iop_sw_cfg_gio_in20 0x00000004 | |
571 | #define regk_iop_sw_cfg_gio_in21 0x00000005 | |
572 | #define regk_iop_sw_cfg_gio_in26 0x00000006 | |
573 | #define regk_iop_sw_cfg_gio_in27 0x00000007 | |
574 | #define regk_iop_sw_cfg_gio_in4 0x00000000 | |
575 | #define regk_iop_sw_cfg_gio_in5 0x00000001 | |
576 | #define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001 | |
577 | #define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000002 | |
578 | #define regk_iop_sw_cfg_last_timer_grp1_tmr3 0x00000003 | |
579 | #define regk_iop_sw_cfg_mpu 0x00000001 | |
580 | #define regk_iop_sw_cfg_none 0x00000000 | |
581 | #define regk_iop_sw_cfg_pdp_out 0x00000001 | |
582 | #define regk_iop_sw_cfg_pdp_out_hi 0x00000001 | |
583 | #define regk_iop_sw_cfg_pdp_out_lo 0x00000000 | |
584 | #define regk_iop_sw_cfg_rw_bus_mask_default 0x00000000 | |
585 | #define regk_iop_sw_cfg_rw_bus_oe_mask_default 0x00000000 | |
586 | #define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000 | |
587 | #define regk_iop_sw_cfg_rw_crc_par_owner_default 0x00000000 | |
588 | #define regk_iop_sw_cfg_rw_dmc_in_owner_default 0x00000000 | |
589 | #define regk_iop_sw_cfg_rw_dmc_out_owner_default 0x00000000 | |
590 | #define regk_iop_sw_cfg_rw_fifo_in_extra_owner_default 0x00000000 | |
591 | #define regk_iop_sw_cfg_rw_fifo_in_owner_default 0x00000000 | |
592 | #define regk_iop_sw_cfg_rw_fifo_out_extra_owner_default 0x00000000 | |
593 | #define regk_iop_sw_cfg_rw_fifo_out_owner_default 0x00000000 | |
594 | #define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000 | |
595 | #define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000 | |
596 | #define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000 | |
597 | #define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000 | |
598 | #define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000 | |
599 | #define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000 | |
600 | #define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000 | |
601 | #define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000 | |
602 | #define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000 | |
603 | #define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000 | |
604 | #define regk_iop_sw_cfg_rw_pdp_cfg_default 0x00000000 | |
605 | #define regk_iop_sw_cfg_rw_pinmapping_default 0x00555555 | |
606 | #define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000 | |
607 | #define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000 | |
608 | #define regk_iop_sw_cfg_rw_scrc_in_owner_default 0x00000000 | |
609 | #define regk_iop_sw_cfg_rw_scrc_out_owner_default 0x00000000 | |
610 | #define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000 | |
611 | #define regk_iop_sw_cfg_rw_spu_cfg_default 0x00000000 | |
612 | #define regk_iop_sw_cfg_rw_spu_owner_default 0x00000000 | |
613 | #define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000 | |
614 | #define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000 | |
615 | #define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000 | |
616 | #define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000 | |
617 | #define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000 | |
618 | #define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000 | |
619 | #define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000 | |
620 | #define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000 | |
621 | #define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000 | |
622 | #define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000 | |
623 | #define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000 | |
624 | #define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000 | |
625 | #define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000 | |
626 | #define regk_iop_sw_cfg_sdp_out 0x00000004 | |
627 | #define regk_iop_sw_cfg_size16 0x00000002 | |
628 | #define regk_iop_sw_cfg_size24 0x00000003 | |
629 | #define regk_iop_sw_cfg_size32 0x00000004 | |
630 | #define regk_iop_sw_cfg_size8 0x00000001 | |
631 | #define regk_iop_sw_cfg_spu 0x00000002 | |
632 | #define regk_iop_sw_cfg_spu_bus_out0_hi 0x00000002 | |
633 | #define regk_iop_sw_cfg_spu_bus_out0_lo 0x00000002 | |
634 | #define regk_iop_sw_cfg_spu_bus_out1_hi 0x00000003 | |
635 | #define regk_iop_sw_cfg_spu_bus_out1_lo 0x00000003 | |
636 | #define regk_iop_sw_cfg_spu_g0 0x00000007 | |
637 | #define regk_iop_sw_cfg_spu_g1 0x00000007 | |
638 | #define regk_iop_sw_cfg_spu_g2 0x00000007 | |
639 | #define regk_iop_sw_cfg_spu_g3 0x00000007 | |
640 | #define regk_iop_sw_cfg_spu_g4 0x00000007 | |
641 | #define regk_iop_sw_cfg_spu_g5 0x00000007 | |
642 | #define regk_iop_sw_cfg_spu_g6 0x00000007 | |
643 | #define regk_iop_sw_cfg_spu_g7 0x00000007 | |
644 | #define regk_iop_sw_cfg_spu_gio0 0x00000000 | |
645 | #define regk_iop_sw_cfg_spu_gio1 0x00000001 | |
646 | #define regk_iop_sw_cfg_spu_gio5 0x00000005 | |
647 | #define regk_iop_sw_cfg_spu_gio6 0x00000006 | |
648 | #define regk_iop_sw_cfg_spu_gio7 0x00000007 | |
649 | #define regk_iop_sw_cfg_spu_gio_out0 0x00000008 | |
650 | #define regk_iop_sw_cfg_spu_gio_out1 0x00000009 | |
651 | #define regk_iop_sw_cfg_spu_gio_out2 0x0000000a | |
652 | #define regk_iop_sw_cfg_spu_gio_out3 0x0000000b | |
653 | #define regk_iop_sw_cfg_spu_gio_out4 0x0000000c | |
654 | #define regk_iop_sw_cfg_spu_gio_out5 0x0000000d | |
655 | #define regk_iop_sw_cfg_spu_gio_out6 0x0000000e | |
656 | #define regk_iop_sw_cfg_spu_gio_out7 0x0000000f | |
657 | #define regk_iop_sw_cfg_spu_gioout0 0x00000000 | |
658 | #define regk_iop_sw_cfg_spu_gioout1 0x00000000 | |
659 | #define regk_iop_sw_cfg_spu_gioout10 0x00000007 | |
660 | #define regk_iop_sw_cfg_spu_gioout11 0x00000007 | |
661 | #define regk_iop_sw_cfg_spu_gioout12 0x00000007 | |
662 | #define regk_iop_sw_cfg_spu_gioout13 0x00000007 | |
663 | #define regk_iop_sw_cfg_spu_gioout14 0x00000007 | |
664 | #define regk_iop_sw_cfg_spu_gioout15 0x00000007 | |
665 | #define regk_iop_sw_cfg_spu_gioout16 0x00000007 | |
666 | #define regk_iop_sw_cfg_spu_gioout17 0x00000007 | |
667 | #define regk_iop_sw_cfg_spu_gioout18 0x00000007 | |
668 | #define regk_iop_sw_cfg_spu_gioout19 0x00000007 | |
669 | #define regk_iop_sw_cfg_spu_gioout2 0x00000001 | |
670 | #define regk_iop_sw_cfg_spu_gioout20 0x00000007 | |
671 | #define regk_iop_sw_cfg_spu_gioout21 0x00000007 | |
672 | #define regk_iop_sw_cfg_spu_gioout22 0x00000007 | |
673 | #define regk_iop_sw_cfg_spu_gioout23 0x00000007 | |
674 | #define regk_iop_sw_cfg_spu_gioout24 0x00000007 | |
675 | #define regk_iop_sw_cfg_spu_gioout25 0x00000007 | |
676 | #define regk_iop_sw_cfg_spu_gioout26 0x00000007 | |
677 | #define regk_iop_sw_cfg_spu_gioout27 0x00000007 | |
678 | #define regk_iop_sw_cfg_spu_gioout28 0x00000007 | |
679 | #define regk_iop_sw_cfg_spu_gioout29 0x00000007 | |
680 | #define regk_iop_sw_cfg_spu_gioout3 0x00000001 | |
681 | #define regk_iop_sw_cfg_spu_gioout30 0x00000007 | |
682 | #define regk_iop_sw_cfg_spu_gioout31 0x00000007 | |
683 | #define regk_iop_sw_cfg_spu_gioout4 0x00000002 | |
684 | #define regk_iop_sw_cfg_spu_gioout5 0x00000002 | |
685 | #define regk_iop_sw_cfg_spu_gioout6 0x00000003 | |
686 | #define regk_iop_sw_cfg_spu_gioout7 0x00000003 | |
687 | #define regk_iop_sw_cfg_spu_gioout8 0x00000007 | |
688 | #define regk_iop_sw_cfg_spu_gioout9 0x00000007 | |
689 | #define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001 | |
690 | #define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002 | |
691 | #define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000003 | |
692 | #define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002 | |
693 | #define regk_iop_sw_cfg_timer_grp0 0x00000000 | |
694 | #define regk_iop_sw_cfg_timer_grp0_rot 0x00000001 | |
695 | #define regk_iop_sw_cfg_timer_grp0_strb0 0x00000005 | |
696 | #define regk_iop_sw_cfg_timer_grp0_strb1 0x00000005 | |
697 | #define regk_iop_sw_cfg_timer_grp0_strb2 0x00000005 | |
698 | #define regk_iop_sw_cfg_timer_grp0_strb3 0x00000005 | |
699 | #define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000002 | |
700 | #define regk_iop_sw_cfg_timer_grp1 0x00000000 | |
701 | #define regk_iop_sw_cfg_timer_grp1_rot 0x00000001 | |
702 | #define regk_iop_sw_cfg_timer_grp1_strb0 0x00000006 | |
703 | #define regk_iop_sw_cfg_timer_grp1_strb1 0x00000006 | |
704 | #define regk_iop_sw_cfg_timer_grp1_strb2 0x00000006 | |
705 | #define regk_iop_sw_cfg_timer_grp1_strb3 0x00000006 | |
706 | #define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000003 | |
707 | #define regk_iop_sw_cfg_trig0_0 0x00000000 | |
708 | #define regk_iop_sw_cfg_trig0_1 0x00000000 | |
709 | #define regk_iop_sw_cfg_trig0_2 0x00000000 | |
710 | #define regk_iop_sw_cfg_trig0_3 0x00000000 | |
711 | #define regk_iop_sw_cfg_trig1_0 0x00000000 | |
712 | #define regk_iop_sw_cfg_trig1_1 0x00000000 | |
713 | #define regk_iop_sw_cfg_trig1_2 0x00000000 | |
714 | #define regk_iop_sw_cfg_trig1_3 0x00000000 | |
715 | #define regk_iop_sw_cfg_trig2_0 0x00000001 | |
716 | #define regk_iop_sw_cfg_trig2_1 0x00000001 | |
717 | #define regk_iop_sw_cfg_trig2_2 0x00000001 | |
718 | #define regk_iop_sw_cfg_trig2_3 0x00000001 | |
719 | #define regk_iop_sw_cfg_trig3_0 0x00000001 | |
720 | #define regk_iop_sw_cfg_trig3_1 0x00000001 | |
721 | #define regk_iop_sw_cfg_trig3_2 0x00000001 | |
722 | #define regk_iop_sw_cfg_trig3_3 0x00000001 | |
723 | #define regk_iop_sw_cfg_trig4_0 0x00000002 | |
724 | #define regk_iop_sw_cfg_trig4_1 0x00000002 | |
725 | #define regk_iop_sw_cfg_trig4_2 0x00000002 | |
726 | #define regk_iop_sw_cfg_trig4_3 0x00000002 | |
727 | #define regk_iop_sw_cfg_trig5_0 0x00000002 | |
728 | #define regk_iop_sw_cfg_trig5_1 0x00000002 | |
729 | #define regk_iop_sw_cfg_trig5_2 0x00000002 | |
730 | #define regk_iop_sw_cfg_trig5_3 0x00000002 | |
731 | #define regk_iop_sw_cfg_trig6_0 0x00000003 | |
732 | #define regk_iop_sw_cfg_trig6_1 0x00000003 | |
733 | #define regk_iop_sw_cfg_trig6_2 0x00000003 | |
734 | #define regk_iop_sw_cfg_trig6_3 0x00000003 | |
735 | #define regk_iop_sw_cfg_trig7_0 0x00000003 | |
736 | #define regk_iop_sw_cfg_trig7_1 0x00000003 | |
737 | #define regk_iop_sw_cfg_trig7_2 0x00000003 | |
738 | #define regk_iop_sw_cfg_trig7_3 0x00000003 | |
739 | #endif /* __iop_sw_cfg_defs_asm_h */ |