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1 | #ifndef __iop_trigger_grp_defs_asm_h |
2 | #define __iop_trigger_grp_defs_asm_h | |
3 | ||
4 | /* | |
5 | * This file is autogenerated from | |
6 | * file: ../../inst/io_proc/rtl/iop_trigger_grp.r | |
7 | * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp | |
8 | * last modfied: Mon Apr 11 16:08:46 2005 | |
9 | * | |
10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_trigger_grp_defs_asm.h ../../inst/io_proc/rtl/iop_trigger_grp.r | |
11 | * id: $Id: iop_trigger_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ | |
12 | * Any changes here will be lost. | |
13 | * | |
14 | * -*- buffer-read-only: t -*- | |
15 | */ | |
16 | ||
17 | #ifndef REG_FIELD | |
18 | #define REG_FIELD( scope, reg, field, value ) \ | |
19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | |
20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | |
21 | #endif | |
22 | ||
23 | #ifndef REG_STATE | |
24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | |
25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | |
26 | #define REG_STATE_X_( k, shift ) (k << shift) | |
27 | #endif | |
28 | ||
29 | #ifndef REG_MASK | |
30 | #define REG_MASK( scope, reg, field ) \ | |
31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | |
32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | |
33 | #endif | |
34 | ||
35 | #ifndef REG_LSB | |
36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | |
37 | #endif | |
38 | ||
39 | #ifndef REG_BIT | |
40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | |
41 | #endif | |
42 | ||
43 | #ifndef REG_ADDR | |
44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | |
45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | |
46 | #endif | |
47 | ||
48 | #ifndef REG_ADDR_VECT | |
49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | |
51 | STRIDE_##scope##_##reg ) | |
52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | |
53 | ((inst) + offs + (index) * stride) | |
54 | #endif | |
55 | ||
56 | #define STRIDE_iop_trigger_grp_rw_cfg 4 | |
57 | /* Register rw_cfg, scope iop_trigger_grp, type rw */ | |
58 | #define reg_iop_trigger_grp_rw_cfg___action___lsb 0 | |
59 | #define reg_iop_trigger_grp_rw_cfg___action___width 2 | |
60 | #define reg_iop_trigger_grp_rw_cfg___once___lsb 2 | |
61 | #define reg_iop_trigger_grp_rw_cfg___once___width 1 | |
62 | #define reg_iop_trigger_grp_rw_cfg___once___bit 2 | |
63 | #define reg_iop_trigger_grp_rw_cfg___trig___lsb 3 | |
64 | #define reg_iop_trigger_grp_rw_cfg___trig___width 3 | |
65 | #define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___lsb 6 | |
66 | #define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___width 1 | |
67 | #define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___bit 6 | |
68 | #define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___lsb 7 | |
69 | #define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___width 1 | |
70 | #define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___bit 7 | |
71 | #define reg_iop_trigger_grp_rw_cfg_offset 0 | |
72 | ||
73 | /* Register rw_cmd, scope iop_trigger_grp, type rw */ | |
74 | #define reg_iop_trigger_grp_rw_cmd___dis___lsb 0 | |
75 | #define reg_iop_trigger_grp_rw_cmd___dis___width 4 | |
76 | #define reg_iop_trigger_grp_rw_cmd___en___lsb 4 | |
77 | #define reg_iop_trigger_grp_rw_cmd___en___width 4 | |
78 | #define reg_iop_trigger_grp_rw_cmd_offset 16 | |
79 | ||
80 | /* Register rw_intr_mask, scope iop_trigger_grp, type rw */ | |
81 | #define reg_iop_trigger_grp_rw_intr_mask___trig0___lsb 0 | |
82 | #define reg_iop_trigger_grp_rw_intr_mask___trig0___width 1 | |
83 | #define reg_iop_trigger_grp_rw_intr_mask___trig0___bit 0 | |
84 | #define reg_iop_trigger_grp_rw_intr_mask___trig1___lsb 1 | |
85 | #define reg_iop_trigger_grp_rw_intr_mask___trig1___width 1 | |
86 | #define reg_iop_trigger_grp_rw_intr_mask___trig1___bit 1 | |
87 | #define reg_iop_trigger_grp_rw_intr_mask___trig2___lsb 2 | |
88 | #define reg_iop_trigger_grp_rw_intr_mask___trig2___width 1 | |
89 | #define reg_iop_trigger_grp_rw_intr_mask___trig2___bit 2 | |
90 | #define reg_iop_trigger_grp_rw_intr_mask___trig3___lsb 3 | |
91 | #define reg_iop_trigger_grp_rw_intr_mask___trig3___width 1 | |
92 | #define reg_iop_trigger_grp_rw_intr_mask___trig3___bit 3 | |
93 | #define reg_iop_trigger_grp_rw_intr_mask_offset 20 | |
94 | ||
95 | /* Register rw_ack_intr, scope iop_trigger_grp, type rw */ | |
96 | #define reg_iop_trigger_grp_rw_ack_intr___trig0___lsb 0 | |
97 | #define reg_iop_trigger_grp_rw_ack_intr___trig0___width 1 | |
98 | #define reg_iop_trigger_grp_rw_ack_intr___trig0___bit 0 | |
99 | #define reg_iop_trigger_grp_rw_ack_intr___trig1___lsb 1 | |
100 | #define reg_iop_trigger_grp_rw_ack_intr___trig1___width 1 | |
101 | #define reg_iop_trigger_grp_rw_ack_intr___trig1___bit 1 | |
102 | #define reg_iop_trigger_grp_rw_ack_intr___trig2___lsb 2 | |
103 | #define reg_iop_trigger_grp_rw_ack_intr___trig2___width 1 | |
104 | #define reg_iop_trigger_grp_rw_ack_intr___trig2___bit 2 | |
105 | #define reg_iop_trigger_grp_rw_ack_intr___trig3___lsb 3 | |
106 | #define reg_iop_trigger_grp_rw_ack_intr___trig3___width 1 | |
107 | #define reg_iop_trigger_grp_rw_ack_intr___trig3___bit 3 | |
108 | #define reg_iop_trigger_grp_rw_ack_intr_offset 24 | |
109 | ||
110 | /* Register r_intr, scope iop_trigger_grp, type r */ | |
111 | #define reg_iop_trigger_grp_r_intr___trig0___lsb 0 | |
112 | #define reg_iop_trigger_grp_r_intr___trig0___width 1 | |
113 | #define reg_iop_trigger_grp_r_intr___trig0___bit 0 | |
114 | #define reg_iop_trigger_grp_r_intr___trig1___lsb 1 | |
115 | #define reg_iop_trigger_grp_r_intr___trig1___width 1 | |
116 | #define reg_iop_trigger_grp_r_intr___trig1___bit 1 | |
117 | #define reg_iop_trigger_grp_r_intr___trig2___lsb 2 | |
118 | #define reg_iop_trigger_grp_r_intr___trig2___width 1 | |
119 | #define reg_iop_trigger_grp_r_intr___trig2___bit 2 | |
120 | #define reg_iop_trigger_grp_r_intr___trig3___lsb 3 | |
121 | #define reg_iop_trigger_grp_r_intr___trig3___width 1 | |
122 | #define reg_iop_trigger_grp_r_intr___trig3___bit 3 | |
123 | #define reg_iop_trigger_grp_r_intr_offset 28 | |
124 | ||
125 | /* Register r_masked_intr, scope iop_trigger_grp, type r */ | |
126 | #define reg_iop_trigger_grp_r_masked_intr___trig0___lsb 0 | |
127 | #define reg_iop_trigger_grp_r_masked_intr___trig0___width 1 | |
128 | #define reg_iop_trigger_grp_r_masked_intr___trig0___bit 0 | |
129 | #define reg_iop_trigger_grp_r_masked_intr___trig1___lsb 1 | |
130 | #define reg_iop_trigger_grp_r_masked_intr___trig1___width 1 | |
131 | #define reg_iop_trigger_grp_r_masked_intr___trig1___bit 1 | |
132 | #define reg_iop_trigger_grp_r_masked_intr___trig2___lsb 2 | |
133 | #define reg_iop_trigger_grp_r_masked_intr___trig2___width 1 | |
134 | #define reg_iop_trigger_grp_r_masked_intr___trig2___bit 2 | |
135 | #define reg_iop_trigger_grp_r_masked_intr___trig3___lsb 3 | |
136 | #define reg_iop_trigger_grp_r_masked_intr___trig3___width 1 | |
137 | #define reg_iop_trigger_grp_r_masked_intr___trig3___bit 3 | |
138 | #define reg_iop_trigger_grp_r_masked_intr_offset 32 | |
139 | ||
140 | ||
141 | /* Constants */ | |
142 | #define regk_iop_trigger_grp_fall 0x00000002 | |
143 | #define regk_iop_trigger_grp_fall_lo 0x00000006 | |
144 | #define regk_iop_trigger_grp_no 0x00000000 | |
145 | #define regk_iop_trigger_grp_off 0x00000000 | |
146 | #define regk_iop_trigger_grp_pulse 0x00000000 | |
147 | #define regk_iop_trigger_grp_rise 0x00000001 | |
148 | #define regk_iop_trigger_grp_rise_fall 0x00000003 | |
149 | #define regk_iop_trigger_grp_rise_fall_hi 0x00000007 | |
150 | #define regk_iop_trigger_grp_rise_fall_lo 0x00000004 | |
151 | #define regk_iop_trigger_grp_rise_hi 0x00000005 | |
152 | #define regk_iop_trigger_grp_rw_cfg_default 0x000000c0 | |
153 | #define regk_iop_trigger_grp_rw_cfg_size 0x00000004 | |
154 | #define regk_iop_trigger_grp_rw_intr_mask_default 0x00000000 | |
155 | #define regk_iop_trigger_grp_toggle 0x00000003 | |
156 | #define regk_iop_trigger_grp_yes 0x00000001 | |
157 | #endif /* __iop_trigger_grp_defs_asm_h */ |