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1 | #ifndef __iop_sw_spu_defs_asm_h |
2 | #define __iop_sw_spu_defs_asm_h | |
3 | ||
4 | /* | |
5 | * This file is autogenerated from | |
6 | * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r | |
7 | * id: <not found> | |
8 | * last modfied: Mon Apr 11 16:10:19 2005 | |
9 | * | |
10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_spu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r | |
11 | * id: $Id: iop_sw_spu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ | |
12 | * Any changes here will be lost. | |
13 | * | |
14 | * -*- buffer-read-only: t -*- | |
15 | */ | |
16 | ||
17 | #ifndef REG_FIELD | |
18 | #define REG_FIELD( scope, reg, field, value ) \ | |
19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | |
20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | |
21 | #endif | |
22 | ||
23 | #ifndef REG_STATE | |
24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | |
25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | |
26 | #define REG_STATE_X_( k, shift ) (k << shift) | |
27 | #endif | |
28 | ||
29 | #ifndef REG_MASK | |
30 | #define REG_MASK( scope, reg, field ) \ | |
31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | |
32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | |
33 | #endif | |
34 | ||
35 | #ifndef REG_LSB | |
36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | |
37 | #endif | |
38 | ||
39 | #ifndef REG_BIT | |
40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | |
41 | #endif | |
42 | ||
43 | #ifndef REG_ADDR | |
44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | |
45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | |
46 | #endif | |
47 | ||
48 | #ifndef REG_ADDR_VECT | |
49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | |
51 | STRIDE_##scope##_##reg ) | |
52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | |
53 | ((inst) + offs + (index) * stride) | |
54 | #endif | |
55 | ||
56 | /* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ | |
57 | #define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0 | |
58 | #define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1 | |
59 | #define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0 | |
60 | #define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1 | |
61 | #define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2 | |
62 | #define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3 | |
63 | #define reg_iop_sw_spu_rw_mc_ctrl___size___width 3 | |
64 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___lsb 6 | |
65 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___width 1 | |
66 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___bit 6 | |
67 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___lsb 7 | |
68 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___width 1 | |
69 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___bit 7 | |
70 | #define reg_iop_sw_spu_rw_mc_ctrl_offset 0 | |
71 | ||
72 | /* Register rw_mc_data, scope iop_sw_spu, type rw */ | |
73 | #define reg_iop_sw_spu_rw_mc_data___val___lsb 0 | |
74 | #define reg_iop_sw_spu_rw_mc_data___val___width 32 | |
75 | #define reg_iop_sw_spu_rw_mc_data_offset 4 | |
76 | ||
77 | /* Register rw_mc_addr, scope iop_sw_spu, type rw */ | |
78 | #define reg_iop_sw_spu_rw_mc_addr_offset 8 | |
79 | ||
80 | /* Register rs_mc_data, scope iop_sw_spu, type rs */ | |
81 | #define reg_iop_sw_spu_rs_mc_data_offset 12 | |
82 | ||
83 | /* Register r_mc_data, scope iop_sw_spu, type r */ | |
84 | #define reg_iop_sw_spu_r_mc_data_offset 16 | |
85 | ||
86 | /* Register r_mc_stat, scope iop_sw_spu, type r */ | |
87 | #define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0 | |
88 | #define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1 | |
89 | #define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0 | |
90 | #define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1 | |
91 | #define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1 | |
92 | #define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1 | |
93 | #define reg_iop_sw_spu_r_mc_stat___busy_spu0___lsb 2 | |
94 | #define reg_iop_sw_spu_r_mc_stat___busy_spu0___width 1 | |
95 | #define reg_iop_sw_spu_r_mc_stat___busy_spu0___bit 2 | |
96 | #define reg_iop_sw_spu_r_mc_stat___busy_spu1___lsb 3 | |
97 | #define reg_iop_sw_spu_r_mc_stat___busy_spu1___width 1 | |
98 | #define reg_iop_sw_spu_r_mc_stat___busy_spu1___bit 3 | |
99 | #define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 4 | |
100 | #define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1 | |
101 | #define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 4 | |
102 | #define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 5 | |
103 | #define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1 | |
104 | #define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 5 | |
105 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___lsb 6 | |
106 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___width 1 | |
107 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___bit 6 | |
108 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___lsb 7 | |
109 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___width 1 | |
110 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___bit 7 | |
111 | #define reg_iop_sw_spu_r_mc_stat_offset 20 | |
112 | ||
113 | /* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */ | |
114 | #define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___lsb 0 | |
115 | #define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___width 8 | |
116 | #define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___lsb 8 | |
117 | #define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___width 8 | |
118 | #define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___lsb 16 | |
119 | #define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___width 8 | |
120 | #define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___lsb 24 | |
121 | #define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___width 8 | |
122 | #define reg_iop_sw_spu_rw_bus0_clr_mask_offset 24 | |
123 | ||
124 | /* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */ | |
125 | #define reg_iop_sw_spu_rw_bus0_set_mask___byte0___lsb 0 | |
126 | #define reg_iop_sw_spu_rw_bus0_set_mask___byte0___width 8 | |
127 | #define reg_iop_sw_spu_rw_bus0_set_mask___byte1___lsb 8 | |
128 | #define reg_iop_sw_spu_rw_bus0_set_mask___byte1___width 8 | |
129 | #define reg_iop_sw_spu_rw_bus0_set_mask___byte2___lsb 16 | |
130 | #define reg_iop_sw_spu_rw_bus0_set_mask___byte2___width 8 | |
131 | #define reg_iop_sw_spu_rw_bus0_set_mask___byte3___lsb 24 | |
132 | #define reg_iop_sw_spu_rw_bus0_set_mask___byte3___width 8 | |
133 | #define reg_iop_sw_spu_rw_bus0_set_mask_offset 28 | |
134 | ||
135 | /* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */ | |
136 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___lsb 0 | |
137 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___width 1 | |
138 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___bit 0 | |
139 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___lsb 1 | |
140 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___width 1 | |
141 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___bit 1 | |
142 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___lsb 2 | |
143 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___width 1 | |
144 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___bit 2 | |
145 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___lsb 3 | |
146 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___width 1 | |
147 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___bit 3 | |
148 | #define reg_iop_sw_spu_rw_bus0_oe_clr_mask_offset 32 | |
149 | ||
150 | /* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */ | |
151 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___lsb 0 | |
152 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___width 1 | |
153 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___bit 0 | |
154 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___lsb 1 | |
155 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___width 1 | |
156 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___bit 1 | |
157 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___lsb 2 | |
158 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___width 1 | |
159 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___bit 2 | |
160 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___lsb 3 | |
161 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___width 1 | |
162 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___bit 3 | |
163 | #define reg_iop_sw_spu_rw_bus0_oe_set_mask_offset 36 | |
164 | ||
165 | /* Register r_bus0_in, scope iop_sw_spu, type r */ | |
166 | #define reg_iop_sw_spu_r_bus0_in_offset 40 | |
167 | ||
168 | /* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */ | |
169 | #define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___lsb 0 | |
170 | #define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___width 8 | |
171 | #define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___lsb 8 | |
172 | #define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___width 8 | |
173 | #define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___lsb 16 | |
174 | #define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___width 8 | |
175 | #define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___lsb 24 | |
176 | #define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___width 8 | |
177 | #define reg_iop_sw_spu_rw_bus1_clr_mask_offset 44 | |
178 | ||
179 | /* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */ | |
180 | #define reg_iop_sw_spu_rw_bus1_set_mask___byte0___lsb 0 | |
181 | #define reg_iop_sw_spu_rw_bus1_set_mask___byte0___width 8 | |
182 | #define reg_iop_sw_spu_rw_bus1_set_mask___byte1___lsb 8 | |
183 | #define reg_iop_sw_spu_rw_bus1_set_mask___byte1___width 8 | |
184 | #define reg_iop_sw_spu_rw_bus1_set_mask___byte2___lsb 16 | |
185 | #define reg_iop_sw_spu_rw_bus1_set_mask___byte2___width 8 | |
186 | #define reg_iop_sw_spu_rw_bus1_set_mask___byte3___lsb 24 | |
187 | #define reg_iop_sw_spu_rw_bus1_set_mask___byte3___width 8 | |
188 | #define reg_iop_sw_spu_rw_bus1_set_mask_offset 48 | |
189 | ||
190 | /* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */ | |
191 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___lsb 0 | |
192 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___width 1 | |
193 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___bit 0 | |
194 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___lsb 1 | |
195 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___width 1 | |
196 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___bit 1 | |
197 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___lsb 2 | |
198 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___width 1 | |
199 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___bit 2 | |
200 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___lsb 3 | |
201 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___width 1 | |
202 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___bit 3 | |
203 | #define reg_iop_sw_spu_rw_bus1_oe_clr_mask_offset 52 | |
204 | ||
205 | /* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */ | |
206 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___lsb 0 | |
207 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___width 1 | |
208 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___bit 0 | |
209 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___lsb 1 | |
210 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___width 1 | |
211 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___bit 1 | |
212 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___lsb 2 | |
213 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___width 1 | |
214 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___bit 2 | |
215 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___lsb 3 | |
216 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___width 1 | |
217 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___bit 3 | |
218 | #define reg_iop_sw_spu_rw_bus1_oe_set_mask_offset 56 | |
219 | ||
220 | /* Register r_bus1_in, scope iop_sw_spu, type r */ | |
221 | #define reg_iop_sw_spu_r_bus1_in_offset 60 | |
222 | ||
223 | /* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ | |
224 | #define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0 | |
225 | #define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32 | |
226 | #define reg_iop_sw_spu_rw_gio_clr_mask_offset 64 | |
227 | ||
228 | /* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ | |
229 | #define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0 | |
230 | #define reg_iop_sw_spu_rw_gio_set_mask___val___width 32 | |
231 | #define reg_iop_sw_spu_rw_gio_set_mask_offset 68 | |
232 | ||
233 | /* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ | |
234 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0 | |
235 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32 | |
236 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 72 | |
237 | ||
238 | /* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ | |
239 | #define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0 | |
240 | #define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32 | |
241 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 76 | |
242 | ||
243 | /* Register r_gio_in, scope iop_sw_spu, type r */ | |
244 | #define reg_iop_sw_spu_r_gio_in_offset 80 | |
245 | ||
246 | /* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */ | |
247 | #define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___lsb 0 | |
248 | #define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___width 8 | |
249 | #define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___lsb 8 | |
250 | #define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___width 8 | |
251 | #define reg_iop_sw_spu_rw_bus0_clr_mask_lo_offset 84 | |
252 | ||
253 | /* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */ | |
254 | #define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___lsb 0 | |
255 | #define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___width 8 | |
256 | #define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___lsb 8 | |
257 | #define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___width 8 | |
258 | #define reg_iop_sw_spu_rw_bus0_clr_mask_hi_offset 88 | |
259 | ||
260 | /* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */ | |
261 | #define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___lsb 0 | |
262 | #define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___width 8 | |
263 | #define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___lsb 8 | |
264 | #define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___width 8 | |
265 | #define reg_iop_sw_spu_rw_bus0_set_mask_lo_offset 92 | |
266 | ||
267 | /* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */ | |
268 | #define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___lsb 0 | |
269 | #define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___width 8 | |
270 | #define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___lsb 8 | |
271 | #define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___width 8 | |
272 | #define reg_iop_sw_spu_rw_bus0_set_mask_hi_offset 96 | |
273 | ||
274 | /* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */ | |
275 | #define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___lsb 0 | |
276 | #define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___width 8 | |
277 | #define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___lsb 8 | |
278 | #define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___width 8 | |
279 | #define reg_iop_sw_spu_rw_bus1_clr_mask_lo_offset 100 | |
280 | ||
281 | /* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */ | |
282 | #define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___lsb 0 | |
283 | #define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___width 8 | |
284 | #define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___lsb 8 | |
285 | #define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___width 8 | |
286 | #define reg_iop_sw_spu_rw_bus1_clr_mask_hi_offset 104 | |
287 | ||
288 | /* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */ | |
289 | #define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___lsb 0 | |
290 | #define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___width 8 | |
291 | #define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___lsb 8 | |
292 | #define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___width 8 | |
293 | #define reg_iop_sw_spu_rw_bus1_set_mask_lo_offset 108 | |
294 | ||
295 | /* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */ | |
296 | #define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___lsb 0 | |
297 | #define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___width 8 | |
298 | #define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___lsb 8 | |
299 | #define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___width 8 | |
300 | #define reg_iop_sw_spu_rw_bus1_set_mask_hi_offset 112 | |
301 | ||
302 | /* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ | |
303 | #define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0 | |
304 | #define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16 | |
305 | #define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 116 | |
306 | ||
307 | /* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ | |
308 | #define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0 | |
309 | #define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16 | |
310 | #define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 120 | |
311 | ||
312 | /* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ | |
313 | #define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0 | |
314 | #define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16 | |
315 | #define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 124 | |
316 | ||
317 | /* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ | |
318 | #define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0 | |
319 | #define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16 | |
320 | #define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 128 | |
321 | ||
322 | /* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ | |
323 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0 | |
324 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16 | |
325 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 132 | |
326 | ||
327 | /* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ | |
328 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0 | |
329 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16 | |
330 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 136 | |
331 | ||
332 | /* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ | |
333 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0 | |
334 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16 | |
335 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 140 | |
336 | ||
337 | /* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ | |
338 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0 | |
339 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16 | |
340 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 144 | |
341 | ||
342 | /* Register rw_cpu_intr, scope iop_sw_spu, type rw */ | |
343 | #define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0 | |
344 | #define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1 | |
345 | #define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0 | |
346 | #define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1 | |
347 | #define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1 | |
348 | #define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1 | |
349 | #define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2 | |
350 | #define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1 | |
351 | #define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2 | |
352 | #define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3 | |
353 | #define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1 | |
354 | #define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3 | |
355 | #define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4 | |
356 | #define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1 | |
357 | #define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4 | |
358 | #define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5 | |
359 | #define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1 | |
360 | #define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5 | |
361 | #define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6 | |
362 | #define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1 | |
363 | #define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6 | |
364 | #define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7 | |
365 | #define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1 | |
366 | #define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7 | |
367 | #define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8 | |
368 | #define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1 | |
369 | #define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8 | |
370 | #define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9 | |
371 | #define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1 | |
372 | #define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9 | |
373 | #define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10 | |
374 | #define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1 | |
375 | #define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10 | |
376 | #define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11 | |
377 | #define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1 | |
378 | #define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11 | |
379 | #define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12 | |
380 | #define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1 | |
381 | #define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12 | |
382 | #define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13 | |
383 | #define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1 | |
384 | #define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13 | |
385 | #define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14 | |
386 | #define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1 | |
387 | #define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14 | |
388 | #define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15 | |
389 | #define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1 | |
390 | #define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15 | |
391 | #define reg_iop_sw_spu_rw_cpu_intr_offset 148 | |
392 | ||
393 | /* Register r_cpu_intr, scope iop_sw_spu, type r */ | |
394 | #define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0 | |
395 | #define reg_iop_sw_spu_r_cpu_intr___intr0___width 1 | |
396 | #define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0 | |
397 | #define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1 | |
398 | #define reg_iop_sw_spu_r_cpu_intr___intr1___width 1 | |
399 | #define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1 | |
400 | #define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2 | |
401 | #define reg_iop_sw_spu_r_cpu_intr___intr2___width 1 | |
402 | #define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2 | |
403 | #define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3 | |
404 | #define reg_iop_sw_spu_r_cpu_intr___intr3___width 1 | |
405 | #define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3 | |
406 | #define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4 | |
407 | #define reg_iop_sw_spu_r_cpu_intr___intr4___width 1 | |
408 | #define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4 | |
409 | #define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5 | |
410 | #define reg_iop_sw_spu_r_cpu_intr___intr5___width 1 | |
411 | #define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5 | |
412 | #define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6 | |
413 | #define reg_iop_sw_spu_r_cpu_intr___intr6___width 1 | |
414 | #define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6 | |
415 | #define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7 | |
416 | #define reg_iop_sw_spu_r_cpu_intr___intr7___width 1 | |
417 | #define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7 | |
418 | #define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8 | |
419 | #define reg_iop_sw_spu_r_cpu_intr___intr8___width 1 | |
420 | #define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8 | |
421 | #define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9 | |
422 | #define reg_iop_sw_spu_r_cpu_intr___intr9___width 1 | |
423 | #define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9 | |
424 | #define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10 | |
425 | #define reg_iop_sw_spu_r_cpu_intr___intr10___width 1 | |
426 | #define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10 | |
427 | #define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11 | |
428 | #define reg_iop_sw_spu_r_cpu_intr___intr11___width 1 | |
429 | #define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11 | |
430 | #define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12 | |
431 | #define reg_iop_sw_spu_r_cpu_intr___intr12___width 1 | |
432 | #define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12 | |
433 | #define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13 | |
434 | #define reg_iop_sw_spu_r_cpu_intr___intr13___width 1 | |
435 | #define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13 | |
436 | #define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14 | |
437 | #define reg_iop_sw_spu_r_cpu_intr___intr14___width 1 | |
438 | #define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14 | |
439 | #define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15 | |
440 | #define reg_iop_sw_spu_r_cpu_intr___intr15___width 1 | |
441 | #define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15 | |
442 | #define reg_iop_sw_spu_r_cpu_intr_offset 152 | |
443 | ||
444 | /* Register r_hw_intr, scope iop_sw_spu, type r */ | |
445 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0 | |
446 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1 | |
447 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0 | |
448 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1 | |
449 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1 | |
450 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1 | |
451 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2 | |
452 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1 | |
453 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2 | |
454 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3 | |
455 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1 | |
456 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3 | |
457 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4 | |
458 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1 | |
459 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4 | |
460 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5 | |
461 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1 | |
462 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5 | |
463 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6 | |
464 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1 | |
465 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6 | |
466 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7 | |
467 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1 | |
468 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7 | |
469 | #define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8 | |
470 | #define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1 | |
471 | #define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8 | |
472 | #define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9 | |
473 | #define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1 | |
474 | #define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9 | |
475 | #define reg_iop_sw_spu_r_hw_intr___timer_grp2___lsb 10 | |
476 | #define reg_iop_sw_spu_r_hw_intr___timer_grp2___width 1 | |
477 | #define reg_iop_sw_spu_r_hw_intr___timer_grp2___bit 10 | |
478 | #define reg_iop_sw_spu_r_hw_intr___timer_grp3___lsb 11 | |
479 | #define reg_iop_sw_spu_r_hw_intr___timer_grp3___width 1 | |
480 | #define reg_iop_sw_spu_r_hw_intr___timer_grp3___bit 11 | |
481 | #define reg_iop_sw_spu_r_hw_intr___fifo_out0___lsb 12 | |
482 | #define reg_iop_sw_spu_r_hw_intr___fifo_out0___width 1 | |
483 | #define reg_iop_sw_spu_r_hw_intr___fifo_out0___bit 12 | |
484 | #define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___lsb 13 | |
485 | #define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___width 1 | |
486 | #define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___bit 13 | |
487 | #define reg_iop_sw_spu_r_hw_intr___fifo_in0___lsb 14 | |
488 | #define reg_iop_sw_spu_r_hw_intr___fifo_in0___width 1 | |
489 | #define reg_iop_sw_spu_r_hw_intr___fifo_in0___bit 14 | |
490 | #define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___lsb 15 | |
491 | #define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___width 1 | |
492 | #define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___bit 15 | |
493 | #define reg_iop_sw_spu_r_hw_intr___fifo_out1___lsb 16 | |
494 | #define reg_iop_sw_spu_r_hw_intr___fifo_out1___width 1 | |
495 | #define reg_iop_sw_spu_r_hw_intr___fifo_out1___bit 16 | |
496 | #define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___lsb 17 | |
497 | #define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___width 1 | |
498 | #define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___bit 17 | |
499 | #define reg_iop_sw_spu_r_hw_intr___fifo_in1___lsb 18 | |
500 | #define reg_iop_sw_spu_r_hw_intr___fifo_in1___width 1 | |
501 | #define reg_iop_sw_spu_r_hw_intr___fifo_in1___bit 18 | |
502 | #define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___lsb 19 | |
503 | #define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___width 1 | |
504 | #define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___bit 19 | |
505 | #define reg_iop_sw_spu_r_hw_intr___dmc_out0___lsb 20 | |
506 | #define reg_iop_sw_spu_r_hw_intr___dmc_out0___width 1 | |
507 | #define reg_iop_sw_spu_r_hw_intr___dmc_out0___bit 20 | |
508 | #define reg_iop_sw_spu_r_hw_intr___dmc_in0___lsb 21 | |
509 | #define reg_iop_sw_spu_r_hw_intr___dmc_in0___width 1 | |
510 | #define reg_iop_sw_spu_r_hw_intr___dmc_in0___bit 21 | |
511 | #define reg_iop_sw_spu_r_hw_intr___dmc_out1___lsb 22 | |
512 | #define reg_iop_sw_spu_r_hw_intr___dmc_out1___width 1 | |
513 | #define reg_iop_sw_spu_r_hw_intr___dmc_out1___bit 22 | |
514 | #define reg_iop_sw_spu_r_hw_intr___dmc_in1___lsb 23 | |
515 | #define reg_iop_sw_spu_r_hw_intr___dmc_in1___width 1 | |
516 | #define reg_iop_sw_spu_r_hw_intr___dmc_in1___bit 23 | |
517 | #define reg_iop_sw_spu_r_hw_intr_offset 156 | |
518 | ||
519 | /* Register rw_mpu_intr, scope iop_sw_spu, type rw */ | |
520 | #define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0 | |
521 | #define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1 | |
522 | #define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0 | |
523 | #define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1 | |
524 | #define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1 | |
525 | #define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1 | |
526 | #define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2 | |
527 | #define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1 | |
528 | #define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2 | |
529 | #define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3 | |
530 | #define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1 | |
531 | #define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3 | |
532 | #define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4 | |
533 | #define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1 | |
534 | #define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4 | |
535 | #define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5 | |
536 | #define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1 | |
537 | #define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5 | |
538 | #define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6 | |
539 | #define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1 | |
540 | #define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6 | |
541 | #define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7 | |
542 | #define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1 | |
543 | #define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7 | |
544 | #define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8 | |
545 | #define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1 | |
546 | #define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8 | |
547 | #define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9 | |
548 | #define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1 | |
549 | #define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9 | |
550 | #define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10 | |
551 | #define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1 | |
552 | #define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10 | |
553 | #define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11 | |
554 | #define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1 | |
555 | #define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11 | |
556 | #define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12 | |
557 | #define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1 | |
558 | #define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12 | |
559 | #define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13 | |
560 | #define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1 | |
561 | #define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13 | |
562 | #define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14 | |
563 | #define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1 | |
564 | #define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14 | |
565 | #define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15 | |
566 | #define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1 | |
567 | #define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15 | |
568 | #define reg_iop_sw_spu_rw_mpu_intr_offset 160 | |
569 | ||
570 | /* Register r_mpu_intr, scope iop_sw_spu, type r */ | |
571 | #define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0 | |
572 | #define reg_iop_sw_spu_r_mpu_intr___intr0___width 1 | |
573 | #define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0 | |
574 | #define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1 | |
575 | #define reg_iop_sw_spu_r_mpu_intr___intr1___width 1 | |
576 | #define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1 | |
577 | #define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2 | |
578 | #define reg_iop_sw_spu_r_mpu_intr___intr2___width 1 | |
579 | #define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2 | |
580 | #define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3 | |
581 | #define reg_iop_sw_spu_r_mpu_intr___intr3___width 1 | |
582 | #define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3 | |
583 | #define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4 | |
584 | #define reg_iop_sw_spu_r_mpu_intr___intr4___width 1 | |
585 | #define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4 | |
586 | #define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5 | |
587 | #define reg_iop_sw_spu_r_mpu_intr___intr5___width 1 | |
588 | #define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5 | |
589 | #define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6 | |
590 | #define reg_iop_sw_spu_r_mpu_intr___intr6___width 1 | |
591 | #define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6 | |
592 | #define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7 | |
593 | #define reg_iop_sw_spu_r_mpu_intr___intr7___width 1 | |
594 | #define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7 | |
595 | #define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8 | |
596 | #define reg_iop_sw_spu_r_mpu_intr___intr8___width 1 | |
597 | #define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8 | |
598 | #define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9 | |
599 | #define reg_iop_sw_spu_r_mpu_intr___intr9___width 1 | |
600 | #define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9 | |
601 | #define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10 | |
602 | #define reg_iop_sw_spu_r_mpu_intr___intr10___width 1 | |
603 | #define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10 | |
604 | #define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11 | |
605 | #define reg_iop_sw_spu_r_mpu_intr___intr11___width 1 | |
606 | #define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11 | |
607 | #define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12 | |
608 | #define reg_iop_sw_spu_r_mpu_intr___intr12___width 1 | |
609 | #define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12 | |
610 | #define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13 | |
611 | #define reg_iop_sw_spu_r_mpu_intr___intr13___width 1 | |
612 | #define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13 | |
613 | #define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14 | |
614 | #define reg_iop_sw_spu_r_mpu_intr___intr14___width 1 | |
615 | #define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14 | |
616 | #define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15 | |
617 | #define reg_iop_sw_spu_r_mpu_intr___intr15___width 1 | |
618 | #define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15 | |
619 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___lsb 16 | |
620 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___width 1 | |
621 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___bit 16 | |
622 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___lsb 17 | |
623 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___width 1 | |
624 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___bit 17 | |
625 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___lsb 18 | |
626 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___width 1 | |
627 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___bit 18 | |
628 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___lsb 19 | |
629 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___width 1 | |
630 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___bit 19 | |
631 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___lsb 20 | |
632 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___width 1 | |
633 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___bit 20 | |
634 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___lsb 21 | |
635 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___width 1 | |
636 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___bit 21 | |
637 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___lsb 22 | |
638 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___width 1 | |
639 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___bit 22 | |
640 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___lsb 23 | |
641 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___width 1 | |
642 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___bit 23 | |
643 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___lsb 24 | |
644 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___width 1 | |
645 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___bit 24 | |
646 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___lsb 25 | |
647 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___width 1 | |
648 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___bit 25 | |
649 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___lsb 26 | |
650 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___width 1 | |
651 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___bit 26 | |
652 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___lsb 27 | |
653 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___width 1 | |
654 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___bit 27 | |
655 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___lsb 28 | |
656 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___width 1 | |
657 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___bit 28 | |
658 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___lsb 29 | |
659 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___width 1 | |
660 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___bit 29 | |
661 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___lsb 30 | |
662 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___width 1 | |
663 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___bit 30 | |
664 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___lsb 31 | |
665 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___width 1 | |
666 | #define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___bit 31 | |
667 | #define reg_iop_sw_spu_r_mpu_intr_offset 164 | |
668 | ||
669 | ||
670 | /* Constants */ | |
671 | #define regk_iop_sw_spu_copy 0x00000000 | |
672 | #define regk_iop_sw_spu_no 0x00000000 | |
673 | #define regk_iop_sw_spu_nop 0x00000000 | |
674 | #define regk_iop_sw_spu_rd 0x00000002 | |
675 | #define regk_iop_sw_spu_reg_copy 0x00000001 | |
676 | #define regk_iop_sw_spu_rw_bus0_clr_mask_default 0x00000000 | |
677 | #define regk_iop_sw_spu_rw_bus0_oe_clr_mask_default 0x00000000 | |
678 | #define regk_iop_sw_spu_rw_bus0_oe_set_mask_default 0x00000000 | |
679 | #define regk_iop_sw_spu_rw_bus0_set_mask_default 0x00000000 | |
680 | #define regk_iop_sw_spu_rw_bus1_clr_mask_default 0x00000000 | |
681 | #define regk_iop_sw_spu_rw_bus1_oe_clr_mask_default 0x00000000 | |
682 | #define regk_iop_sw_spu_rw_bus1_oe_set_mask_default 0x00000000 | |
683 | #define regk_iop_sw_spu_rw_bus1_set_mask_default 0x00000000 | |
684 | #define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000 | |
685 | #define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000 | |
686 | #define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000 | |
687 | #define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000 | |
688 | #define regk_iop_sw_spu_set 0x00000001 | |
689 | #define regk_iop_sw_spu_wr 0x00000003 | |
690 | #define regk_iop_sw_spu_yes 0x00000001 | |
691 | #endif /* __iop_sw_spu_defs_asm_h */ |