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1 | #ifndef __iop_fifo_out_defs_asm_h |
2 | #define __iop_fifo_out_defs_asm_h | |
3 | ||
4 | /* | |
5 | * This file is autogenerated from | |
6 | * file: ../../inst/io_proc/rtl/iop_fifo_out.r | |
7 | * id: <not found> | |
8 | * last modfied: Mon Apr 11 16:10:09 2005 | |
9 | * | |
10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out.r | |
11 | * id: $Id: iop_fifo_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ | |
12 | * Any changes here will be lost. | |
13 | * | |
14 | * -*- buffer-read-only: t -*- | |
15 | */ | |
16 | ||
17 | #ifndef REG_FIELD | |
18 | #define REG_FIELD( scope, reg, field, value ) \ | |
19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | |
20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | |
21 | #endif | |
22 | ||
23 | #ifndef REG_STATE | |
24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | |
25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | |
26 | #define REG_STATE_X_( k, shift ) (k << shift) | |
27 | #endif | |
28 | ||
29 | #ifndef REG_MASK | |
30 | #define REG_MASK( scope, reg, field ) \ | |
31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | |
32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | |
33 | #endif | |
34 | ||
35 | #ifndef REG_LSB | |
36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | |
37 | #endif | |
38 | ||
39 | #ifndef REG_BIT | |
40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | |
41 | #endif | |
42 | ||
43 | #ifndef REG_ADDR | |
44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | |
45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | |
46 | #endif | |
47 | ||
48 | #ifndef REG_ADDR_VECT | |
49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | |
51 | STRIDE_##scope##_##reg ) | |
52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | |
53 | ((inst) + offs + (index) * stride) | |
54 | #endif | |
55 | ||
56 | /* Register rw_cfg, scope iop_fifo_out, type rw */ | |
57 | #define reg_iop_fifo_out_rw_cfg___free_lim___lsb 0 | |
58 | #define reg_iop_fifo_out_rw_cfg___free_lim___width 3 | |
59 | #define reg_iop_fifo_out_rw_cfg___byte_order___lsb 3 | |
60 | #define reg_iop_fifo_out_rw_cfg___byte_order___width 2 | |
61 | #define reg_iop_fifo_out_rw_cfg___trig___lsb 5 | |
62 | #define reg_iop_fifo_out_rw_cfg___trig___width 2 | |
63 | #define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___lsb 7 | |
64 | #define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___width 1 | |
65 | #define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___bit 7 | |
66 | #define reg_iop_fifo_out_rw_cfg___mode___lsb 8 | |
67 | #define reg_iop_fifo_out_rw_cfg___mode___width 2 | |
68 | #define reg_iop_fifo_out_rw_cfg___delay_out_last___lsb 10 | |
69 | #define reg_iop_fifo_out_rw_cfg___delay_out_last___width 1 | |
70 | #define reg_iop_fifo_out_rw_cfg___delay_out_last___bit 10 | |
71 | #define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___lsb 11 | |
72 | #define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___width 1 | |
73 | #define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___bit 11 | |
74 | #define reg_iop_fifo_out_rw_cfg_offset 0 | |
75 | ||
76 | /* Register rw_ctrl, scope iop_fifo_out, type rw */ | |
77 | #define reg_iop_fifo_out_rw_ctrl___dif_in_en___lsb 0 | |
78 | #define reg_iop_fifo_out_rw_ctrl___dif_in_en___width 1 | |
79 | #define reg_iop_fifo_out_rw_ctrl___dif_in_en___bit 0 | |
80 | #define reg_iop_fifo_out_rw_ctrl___dif_out_en___lsb 1 | |
81 | #define reg_iop_fifo_out_rw_ctrl___dif_out_en___width 1 | |
82 | #define reg_iop_fifo_out_rw_ctrl___dif_out_en___bit 1 | |
83 | #define reg_iop_fifo_out_rw_ctrl_offset 4 | |
84 | ||
85 | /* Register r_stat, scope iop_fifo_out, type r */ | |
86 | #define reg_iop_fifo_out_r_stat___avail_bytes___lsb 0 | |
87 | #define reg_iop_fifo_out_r_stat___avail_bytes___width 4 | |
88 | #define reg_iop_fifo_out_r_stat___last___lsb 4 | |
89 | #define reg_iop_fifo_out_r_stat___last___width 8 | |
90 | #define reg_iop_fifo_out_r_stat___dif_in_en___lsb 12 | |
91 | #define reg_iop_fifo_out_r_stat___dif_in_en___width 1 | |
92 | #define reg_iop_fifo_out_r_stat___dif_in_en___bit 12 | |
93 | #define reg_iop_fifo_out_r_stat___dif_out_en___lsb 13 | |
94 | #define reg_iop_fifo_out_r_stat___dif_out_en___width 1 | |
95 | #define reg_iop_fifo_out_r_stat___dif_out_en___bit 13 | |
96 | #define reg_iop_fifo_out_r_stat___zero_data_last___lsb 14 | |
97 | #define reg_iop_fifo_out_r_stat___zero_data_last___width 1 | |
98 | #define reg_iop_fifo_out_r_stat___zero_data_last___bit 14 | |
99 | #define reg_iop_fifo_out_r_stat_offset 8 | |
100 | ||
101 | /* Register rw_wr1byte, scope iop_fifo_out, type rw */ | |
102 | #define reg_iop_fifo_out_rw_wr1byte___data___lsb 0 | |
103 | #define reg_iop_fifo_out_rw_wr1byte___data___width 8 | |
104 | #define reg_iop_fifo_out_rw_wr1byte_offset 12 | |
105 | ||
106 | /* Register rw_wr2byte, scope iop_fifo_out, type rw */ | |
107 | #define reg_iop_fifo_out_rw_wr2byte___data___lsb 0 | |
108 | #define reg_iop_fifo_out_rw_wr2byte___data___width 16 | |
109 | #define reg_iop_fifo_out_rw_wr2byte_offset 16 | |
110 | ||
111 | /* Register rw_wr3byte, scope iop_fifo_out, type rw */ | |
112 | #define reg_iop_fifo_out_rw_wr3byte___data___lsb 0 | |
113 | #define reg_iop_fifo_out_rw_wr3byte___data___width 24 | |
114 | #define reg_iop_fifo_out_rw_wr3byte_offset 20 | |
115 | ||
116 | /* Register rw_wr4byte, scope iop_fifo_out, type rw */ | |
117 | #define reg_iop_fifo_out_rw_wr4byte___data___lsb 0 | |
118 | #define reg_iop_fifo_out_rw_wr4byte___data___width 32 | |
119 | #define reg_iop_fifo_out_rw_wr4byte_offset 24 | |
120 | ||
121 | /* Register rw_wr1byte_last, scope iop_fifo_out, type rw */ | |
122 | #define reg_iop_fifo_out_rw_wr1byte_last___data___lsb 0 | |
123 | #define reg_iop_fifo_out_rw_wr1byte_last___data___width 8 | |
124 | #define reg_iop_fifo_out_rw_wr1byte_last_offset 28 | |
125 | ||
126 | /* Register rw_wr2byte_last, scope iop_fifo_out, type rw */ | |
127 | #define reg_iop_fifo_out_rw_wr2byte_last___data___lsb 0 | |
128 | #define reg_iop_fifo_out_rw_wr2byte_last___data___width 16 | |
129 | #define reg_iop_fifo_out_rw_wr2byte_last_offset 32 | |
130 | ||
131 | /* Register rw_wr3byte_last, scope iop_fifo_out, type rw */ | |
132 | #define reg_iop_fifo_out_rw_wr3byte_last___data___lsb 0 | |
133 | #define reg_iop_fifo_out_rw_wr3byte_last___data___width 24 | |
134 | #define reg_iop_fifo_out_rw_wr3byte_last_offset 36 | |
135 | ||
136 | /* Register rw_wr4byte_last, scope iop_fifo_out, type rw */ | |
137 | #define reg_iop_fifo_out_rw_wr4byte_last___data___lsb 0 | |
138 | #define reg_iop_fifo_out_rw_wr4byte_last___data___width 32 | |
139 | #define reg_iop_fifo_out_rw_wr4byte_last_offset 40 | |
140 | ||
141 | /* Register rw_set_last, scope iop_fifo_out, type rw */ | |
142 | #define reg_iop_fifo_out_rw_set_last_offset 44 | |
143 | ||
144 | /* Register rs_rd_data, scope iop_fifo_out, type rs */ | |
145 | #define reg_iop_fifo_out_rs_rd_data_offset 48 | |
146 | ||
147 | /* Register r_rd_data, scope iop_fifo_out, type r */ | |
148 | #define reg_iop_fifo_out_r_rd_data_offset 52 | |
149 | ||
150 | /* Register rw_strb_dif_out, scope iop_fifo_out, type rw */ | |
151 | #define reg_iop_fifo_out_rw_strb_dif_out_offset 56 | |
152 | ||
153 | /* Register rw_intr_mask, scope iop_fifo_out, type rw */ | |
154 | #define reg_iop_fifo_out_rw_intr_mask___urun___lsb 0 | |
155 | #define reg_iop_fifo_out_rw_intr_mask___urun___width 1 | |
156 | #define reg_iop_fifo_out_rw_intr_mask___urun___bit 0 | |
157 | #define reg_iop_fifo_out_rw_intr_mask___last_data___lsb 1 | |
158 | #define reg_iop_fifo_out_rw_intr_mask___last_data___width 1 | |
159 | #define reg_iop_fifo_out_rw_intr_mask___last_data___bit 1 | |
160 | #define reg_iop_fifo_out_rw_intr_mask___dav___lsb 2 | |
161 | #define reg_iop_fifo_out_rw_intr_mask___dav___width 1 | |
162 | #define reg_iop_fifo_out_rw_intr_mask___dav___bit 2 | |
163 | #define reg_iop_fifo_out_rw_intr_mask___free___lsb 3 | |
164 | #define reg_iop_fifo_out_rw_intr_mask___free___width 1 | |
165 | #define reg_iop_fifo_out_rw_intr_mask___free___bit 3 | |
166 | #define reg_iop_fifo_out_rw_intr_mask___orun___lsb 4 | |
167 | #define reg_iop_fifo_out_rw_intr_mask___orun___width 1 | |
168 | #define reg_iop_fifo_out_rw_intr_mask___orun___bit 4 | |
169 | #define reg_iop_fifo_out_rw_intr_mask_offset 60 | |
170 | ||
171 | /* Register rw_ack_intr, scope iop_fifo_out, type rw */ | |
172 | #define reg_iop_fifo_out_rw_ack_intr___urun___lsb 0 | |
173 | #define reg_iop_fifo_out_rw_ack_intr___urun___width 1 | |
174 | #define reg_iop_fifo_out_rw_ack_intr___urun___bit 0 | |
175 | #define reg_iop_fifo_out_rw_ack_intr___last_data___lsb 1 | |
176 | #define reg_iop_fifo_out_rw_ack_intr___last_data___width 1 | |
177 | #define reg_iop_fifo_out_rw_ack_intr___last_data___bit 1 | |
178 | #define reg_iop_fifo_out_rw_ack_intr___dav___lsb 2 | |
179 | #define reg_iop_fifo_out_rw_ack_intr___dav___width 1 | |
180 | #define reg_iop_fifo_out_rw_ack_intr___dav___bit 2 | |
181 | #define reg_iop_fifo_out_rw_ack_intr___free___lsb 3 | |
182 | #define reg_iop_fifo_out_rw_ack_intr___free___width 1 | |
183 | #define reg_iop_fifo_out_rw_ack_intr___free___bit 3 | |
184 | #define reg_iop_fifo_out_rw_ack_intr___orun___lsb 4 | |
185 | #define reg_iop_fifo_out_rw_ack_intr___orun___width 1 | |
186 | #define reg_iop_fifo_out_rw_ack_intr___orun___bit 4 | |
187 | #define reg_iop_fifo_out_rw_ack_intr_offset 64 | |
188 | ||
189 | /* Register r_intr, scope iop_fifo_out, type r */ | |
190 | #define reg_iop_fifo_out_r_intr___urun___lsb 0 | |
191 | #define reg_iop_fifo_out_r_intr___urun___width 1 | |
192 | #define reg_iop_fifo_out_r_intr___urun___bit 0 | |
193 | #define reg_iop_fifo_out_r_intr___last_data___lsb 1 | |
194 | #define reg_iop_fifo_out_r_intr___last_data___width 1 | |
195 | #define reg_iop_fifo_out_r_intr___last_data___bit 1 | |
196 | #define reg_iop_fifo_out_r_intr___dav___lsb 2 | |
197 | #define reg_iop_fifo_out_r_intr___dav___width 1 | |
198 | #define reg_iop_fifo_out_r_intr___dav___bit 2 | |
199 | #define reg_iop_fifo_out_r_intr___free___lsb 3 | |
200 | #define reg_iop_fifo_out_r_intr___free___width 1 | |
201 | #define reg_iop_fifo_out_r_intr___free___bit 3 | |
202 | #define reg_iop_fifo_out_r_intr___orun___lsb 4 | |
203 | #define reg_iop_fifo_out_r_intr___orun___width 1 | |
204 | #define reg_iop_fifo_out_r_intr___orun___bit 4 | |
205 | #define reg_iop_fifo_out_r_intr_offset 68 | |
206 | ||
207 | /* Register r_masked_intr, scope iop_fifo_out, type r */ | |
208 | #define reg_iop_fifo_out_r_masked_intr___urun___lsb 0 | |
209 | #define reg_iop_fifo_out_r_masked_intr___urun___width 1 | |
210 | #define reg_iop_fifo_out_r_masked_intr___urun___bit 0 | |
211 | #define reg_iop_fifo_out_r_masked_intr___last_data___lsb 1 | |
212 | #define reg_iop_fifo_out_r_masked_intr___last_data___width 1 | |
213 | #define reg_iop_fifo_out_r_masked_intr___last_data___bit 1 | |
214 | #define reg_iop_fifo_out_r_masked_intr___dav___lsb 2 | |
215 | #define reg_iop_fifo_out_r_masked_intr___dav___width 1 | |
216 | #define reg_iop_fifo_out_r_masked_intr___dav___bit 2 | |
217 | #define reg_iop_fifo_out_r_masked_intr___free___lsb 3 | |
218 | #define reg_iop_fifo_out_r_masked_intr___free___width 1 | |
219 | #define reg_iop_fifo_out_r_masked_intr___free___bit 3 | |
220 | #define reg_iop_fifo_out_r_masked_intr___orun___lsb 4 | |
221 | #define reg_iop_fifo_out_r_masked_intr___orun___width 1 | |
222 | #define reg_iop_fifo_out_r_masked_intr___orun___bit 4 | |
223 | #define reg_iop_fifo_out_r_masked_intr_offset 72 | |
224 | ||
225 | ||
226 | /* Constants */ | |
227 | #define regk_iop_fifo_out_hi 0x00000000 | |
228 | #define regk_iop_fifo_out_neg 0x00000002 | |
229 | #define regk_iop_fifo_out_no 0x00000000 | |
230 | #define regk_iop_fifo_out_order16 0x00000001 | |
231 | #define regk_iop_fifo_out_order24 0x00000002 | |
232 | #define regk_iop_fifo_out_order32 0x00000003 | |
233 | #define regk_iop_fifo_out_order8 0x00000000 | |
234 | #define regk_iop_fifo_out_pos 0x00000001 | |
235 | #define regk_iop_fifo_out_pos_neg 0x00000003 | |
236 | #define regk_iop_fifo_out_rw_cfg_default 0x00000024 | |
237 | #define regk_iop_fifo_out_rw_ctrl_default 0x00000000 | |
238 | #define regk_iop_fifo_out_rw_intr_mask_default 0x00000000 | |
239 | #define regk_iop_fifo_out_rw_set_last_default 0x00000000 | |
240 | #define regk_iop_fifo_out_rw_strb_dif_out_default 0x00000000 | |
241 | #define regk_iop_fifo_out_rw_wr1byte_default 0x00000000 | |
242 | #define regk_iop_fifo_out_rw_wr1byte_last_default 0x00000000 | |
243 | #define regk_iop_fifo_out_rw_wr2byte_default 0x00000000 | |
244 | #define regk_iop_fifo_out_rw_wr2byte_last_default 0x00000000 | |
245 | #define regk_iop_fifo_out_rw_wr3byte_default 0x00000000 | |
246 | #define regk_iop_fifo_out_rw_wr3byte_last_default 0x00000000 | |
247 | #define regk_iop_fifo_out_rw_wr4byte_default 0x00000000 | |
248 | #define regk_iop_fifo_out_rw_wr4byte_last_default 0x00000000 | |
249 | #define regk_iop_fifo_out_size16 0x00000002 | |
250 | #define regk_iop_fifo_out_size24 0x00000001 | |
251 | #define regk_iop_fifo_out_size32 0x00000000 | |
252 | #define regk_iop_fifo_out_size8 0x00000003 | |
253 | #define regk_iop_fifo_out_yes 0x00000001 | |
254 | #endif /* __iop_fifo_out_defs_asm_h */ |