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51533b61 MS |
1 | #ifndef __dma_defs_asm_h |
2 | #define __dma_defs_asm_h | |
3 | ||
4 | /* | |
5 | * This file is autogenerated from | |
6 | * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r | |
7 | * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp | |
8 | * last modfied: Mon Apr 11 16:06:51 2005 | |
9 | * | |
10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/dma_defs_asm.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r | |
11 | * id: $Id: dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | |
12 | * Any changes here will be lost. | |
13 | * | |
14 | * -*- buffer-read-only: t -*- | |
15 | */ | |
16 | ||
17 | #ifndef REG_FIELD | |
18 | #define REG_FIELD( scope, reg, field, value ) \ | |
19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | |
20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | |
21 | #endif | |
22 | ||
23 | #ifndef REG_STATE | |
24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | |
25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | |
26 | #define REG_STATE_X_( k, shift ) (k << shift) | |
27 | #endif | |
28 | ||
29 | #ifndef REG_MASK | |
30 | #define REG_MASK( scope, reg, field ) \ | |
31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | |
32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | |
33 | #endif | |
34 | ||
35 | #ifndef REG_LSB | |
36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | |
37 | #endif | |
38 | ||
39 | #ifndef REG_BIT | |
40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | |
41 | #endif | |
42 | ||
43 | #ifndef REG_ADDR | |
44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | |
45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | |
46 | #endif | |
47 | ||
48 | #ifndef REG_ADDR_VECT | |
49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | |
51 | STRIDE_##scope##_##reg ) | |
52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | |
53 | ((inst) + offs + (index) * stride) | |
54 | #endif | |
55 | ||
56 | /* Register rw_data, scope dma, type rw */ | |
57 | #define reg_dma_rw_data_offset 0 | |
58 | ||
59 | /* Register rw_data_next, scope dma, type rw */ | |
60 | #define reg_dma_rw_data_next_offset 4 | |
61 | ||
62 | /* Register rw_data_buf, scope dma, type rw */ | |
63 | #define reg_dma_rw_data_buf_offset 8 | |
64 | ||
65 | /* Register rw_data_ctrl, scope dma, type rw */ | |
66 | #define reg_dma_rw_data_ctrl___eol___lsb 0 | |
67 | #define reg_dma_rw_data_ctrl___eol___width 1 | |
68 | #define reg_dma_rw_data_ctrl___eol___bit 0 | |
69 | #define reg_dma_rw_data_ctrl___out_eop___lsb 3 | |
70 | #define reg_dma_rw_data_ctrl___out_eop___width 1 | |
71 | #define reg_dma_rw_data_ctrl___out_eop___bit 3 | |
72 | #define reg_dma_rw_data_ctrl___intr___lsb 4 | |
73 | #define reg_dma_rw_data_ctrl___intr___width 1 | |
74 | #define reg_dma_rw_data_ctrl___intr___bit 4 | |
75 | #define reg_dma_rw_data_ctrl___wait___lsb 5 | |
76 | #define reg_dma_rw_data_ctrl___wait___width 1 | |
77 | #define reg_dma_rw_data_ctrl___wait___bit 5 | |
78 | #define reg_dma_rw_data_ctrl_offset 12 | |
79 | ||
80 | /* Register rw_data_stat, scope dma, type rw */ | |
81 | #define reg_dma_rw_data_stat___in_eop___lsb 3 | |
82 | #define reg_dma_rw_data_stat___in_eop___width 1 | |
83 | #define reg_dma_rw_data_stat___in_eop___bit 3 | |
84 | #define reg_dma_rw_data_stat_offset 16 | |
85 | ||
86 | /* Register rw_data_md, scope dma, type rw */ | |
87 | #define reg_dma_rw_data_md___md___lsb 0 | |
88 | #define reg_dma_rw_data_md___md___width 16 | |
89 | #define reg_dma_rw_data_md_offset 20 | |
90 | ||
91 | /* Register rw_data_md_s, scope dma, type rw */ | |
92 | #define reg_dma_rw_data_md_s___md_s___lsb 0 | |
93 | #define reg_dma_rw_data_md_s___md_s___width 16 | |
94 | #define reg_dma_rw_data_md_s_offset 24 | |
95 | ||
96 | /* Register rw_data_after, scope dma, type rw */ | |
97 | #define reg_dma_rw_data_after_offset 28 | |
98 | ||
99 | /* Register rw_ctxt, scope dma, type rw */ | |
100 | #define reg_dma_rw_ctxt_offset 32 | |
101 | ||
102 | /* Register rw_ctxt_next, scope dma, type rw */ | |
103 | #define reg_dma_rw_ctxt_next_offset 36 | |
104 | ||
105 | /* Register rw_ctxt_ctrl, scope dma, type rw */ | |
106 | #define reg_dma_rw_ctxt_ctrl___eol___lsb 0 | |
107 | #define reg_dma_rw_ctxt_ctrl___eol___width 1 | |
108 | #define reg_dma_rw_ctxt_ctrl___eol___bit 0 | |
109 | #define reg_dma_rw_ctxt_ctrl___intr___lsb 4 | |
110 | #define reg_dma_rw_ctxt_ctrl___intr___width 1 | |
111 | #define reg_dma_rw_ctxt_ctrl___intr___bit 4 | |
112 | #define reg_dma_rw_ctxt_ctrl___store_mode___lsb 6 | |
113 | #define reg_dma_rw_ctxt_ctrl___store_mode___width 1 | |
114 | #define reg_dma_rw_ctxt_ctrl___store_mode___bit 6 | |
115 | #define reg_dma_rw_ctxt_ctrl___en___lsb 7 | |
116 | #define reg_dma_rw_ctxt_ctrl___en___width 1 | |
117 | #define reg_dma_rw_ctxt_ctrl___en___bit 7 | |
118 | #define reg_dma_rw_ctxt_ctrl_offset 40 | |
119 | ||
120 | /* Register rw_ctxt_stat, scope dma, type rw */ | |
121 | #define reg_dma_rw_ctxt_stat___dis___lsb 7 | |
122 | #define reg_dma_rw_ctxt_stat___dis___width 1 | |
123 | #define reg_dma_rw_ctxt_stat___dis___bit 7 | |
124 | #define reg_dma_rw_ctxt_stat_offset 44 | |
125 | ||
126 | /* Register rw_ctxt_md0, scope dma, type rw */ | |
127 | #define reg_dma_rw_ctxt_md0___md0___lsb 0 | |
128 | #define reg_dma_rw_ctxt_md0___md0___width 16 | |
129 | #define reg_dma_rw_ctxt_md0_offset 48 | |
130 | ||
131 | /* Register rw_ctxt_md0_s, scope dma, type rw */ | |
132 | #define reg_dma_rw_ctxt_md0_s___md0_s___lsb 0 | |
133 | #define reg_dma_rw_ctxt_md0_s___md0_s___width 16 | |
134 | #define reg_dma_rw_ctxt_md0_s_offset 52 | |
135 | ||
136 | /* Register rw_ctxt_md1, scope dma, type rw */ | |
137 | #define reg_dma_rw_ctxt_md1_offset 56 | |
138 | ||
139 | /* Register rw_ctxt_md1_s, scope dma, type rw */ | |
140 | #define reg_dma_rw_ctxt_md1_s_offset 60 | |
141 | ||
142 | /* Register rw_ctxt_md2, scope dma, type rw */ | |
143 | #define reg_dma_rw_ctxt_md2_offset 64 | |
144 | ||
145 | /* Register rw_ctxt_md2_s, scope dma, type rw */ | |
146 | #define reg_dma_rw_ctxt_md2_s_offset 68 | |
147 | ||
148 | /* Register rw_ctxt_md3, scope dma, type rw */ | |
149 | #define reg_dma_rw_ctxt_md3_offset 72 | |
150 | ||
151 | /* Register rw_ctxt_md3_s, scope dma, type rw */ | |
152 | #define reg_dma_rw_ctxt_md3_s_offset 76 | |
153 | ||
154 | /* Register rw_ctxt_md4, scope dma, type rw */ | |
155 | #define reg_dma_rw_ctxt_md4_offset 80 | |
156 | ||
157 | /* Register rw_ctxt_md4_s, scope dma, type rw */ | |
158 | #define reg_dma_rw_ctxt_md4_s_offset 84 | |
159 | ||
160 | /* Register rw_saved_data, scope dma, type rw */ | |
161 | #define reg_dma_rw_saved_data_offset 88 | |
162 | ||
163 | /* Register rw_saved_data_buf, scope dma, type rw */ | |
164 | #define reg_dma_rw_saved_data_buf_offset 92 | |
165 | ||
166 | /* Register rw_group, scope dma, type rw */ | |
167 | #define reg_dma_rw_group_offset 96 | |
168 | ||
169 | /* Register rw_group_next, scope dma, type rw */ | |
170 | #define reg_dma_rw_group_next_offset 100 | |
171 | ||
172 | /* Register rw_group_ctrl, scope dma, type rw */ | |
173 | #define reg_dma_rw_group_ctrl___eol___lsb 0 | |
174 | #define reg_dma_rw_group_ctrl___eol___width 1 | |
175 | #define reg_dma_rw_group_ctrl___eol___bit 0 | |
176 | #define reg_dma_rw_group_ctrl___tol___lsb 1 | |
177 | #define reg_dma_rw_group_ctrl___tol___width 1 | |
178 | #define reg_dma_rw_group_ctrl___tol___bit 1 | |
179 | #define reg_dma_rw_group_ctrl___bol___lsb 2 | |
180 | #define reg_dma_rw_group_ctrl___bol___width 1 | |
181 | #define reg_dma_rw_group_ctrl___bol___bit 2 | |
182 | #define reg_dma_rw_group_ctrl___intr___lsb 4 | |
183 | #define reg_dma_rw_group_ctrl___intr___width 1 | |
184 | #define reg_dma_rw_group_ctrl___intr___bit 4 | |
185 | #define reg_dma_rw_group_ctrl___en___lsb 7 | |
186 | #define reg_dma_rw_group_ctrl___en___width 1 | |
187 | #define reg_dma_rw_group_ctrl___en___bit 7 | |
188 | #define reg_dma_rw_group_ctrl_offset 104 | |
189 | ||
190 | /* Register rw_group_stat, scope dma, type rw */ | |
191 | #define reg_dma_rw_group_stat___dis___lsb 7 | |
192 | #define reg_dma_rw_group_stat___dis___width 1 | |
193 | #define reg_dma_rw_group_stat___dis___bit 7 | |
194 | #define reg_dma_rw_group_stat_offset 108 | |
195 | ||
196 | /* Register rw_group_md, scope dma, type rw */ | |
197 | #define reg_dma_rw_group_md___md___lsb 0 | |
198 | #define reg_dma_rw_group_md___md___width 16 | |
199 | #define reg_dma_rw_group_md_offset 112 | |
200 | ||
201 | /* Register rw_group_md_s, scope dma, type rw */ | |
202 | #define reg_dma_rw_group_md_s___md_s___lsb 0 | |
203 | #define reg_dma_rw_group_md_s___md_s___width 16 | |
204 | #define reg_dma_rw_group_md_s_offset 116 | |
205 | ||
206 | /* Register rw_group_up, scope dma, type rw */ | |
207 | #define reg_dma_rw_group_up_offset 120 | |
208 | ||
209 | /* Register rw_group_down, scope dma, type rw */ | |
210 | #define reg_dma_rw_group_down_offset 124 | |
211 | ||
212 | /* Register rw_cmd, scope dma, type rw */ | |
213 | #define reg_dma_rw_cmd___cont_data___lsb 0 | |
214 | #define reg_dma_rw_cmd___cont_data___width 1 | |
215 | #define reg_dma_rw_cmd___cont_data___bit 0 | |
216 | #define reg_dma_rw_cmd_offset 128 | |
217 | ||
218 | /* Register rw_cfg, scope dma, type rw */ | |
219 | #define reg_dma_rw_cfg___en___lsb 0 | |
220 | #define reg_dma_rw_cfg___en___width 1 | |
221 | #define reg_dma_rw_cfg___en___bit 0 | |
222 | #define reg_dma_rw_cfg___stop___lsb 1 | |
223 | #define reg_dma_rw_cfg___stop___width 1 | |
224 | #define reg_dma_rw_cfg___stop___bit 1 | |
225 | #define reg_dma_rw_cfg_offset 132 | |
226 | ||
227 | /* Register rw_stat, scope dma, type rw */ | |
228 | #define reg_dma_rw_stat___mode___lsb 0 | |
229 | #define reg_dma_rw_stat___mode___width 5 | |
230 | #define reg_dma_rw_stat___list_state___lsb 5 | |
231 | #define reg_dma_rw_stat___list_state___width 3 | |
232 | #define reg_dma_rw_stat___stream_cmd_src___lsb 8 | |
233 | #define reg_dma_rw_stat___stream_cmd_src___width 8 | |
234 | #define reg_dma_rw_stat___buf___lsb 24 | |
235 | #define reg_dma_rw_stat___buf___width 8 | |
236 | #define reg_dma_rw_stat_offset 136 | |
237 | ||
238 | /* Register rw_intr_mask, scope dma, type rw */ | |
239 | #define reg_dma_rw_intr_mask___group___lsb 0 | |
240 | #define reg_dma_rw_intr_mask___group___width 1 | |
241 | #define reg_dma_rw_intr_mask___group___bit 0 | |
242 | #define reg_dma_rw_intr_mask___ctxt___lsb 1 | |
243 | #define reg_dma_rw_intr_mask___ctxt___width 1 | |
244 | #define reg_dma_rw_intr_mask___ctxt___bit 1 | |
245 | #define reg_dma_rw_intr_mask___data___lsb 2 | |
246 | #define reg_dma_rw_intr_mask___data___width 1 | |
247 | #define reg_dma_rw_intr_mask___data___bit 2 | |
248 | #define reg_dma_rw_intr_mask___in_eop___lsb 3 | |
249 | #define reg_dma_rw_intr_mask___in_eop___width 1 | |
250 | #define reg_dma_rw_intr_mask___in_eop___bit 3 | |
251 | #define reg_dma_rw_intr_mask___stream_cmd___lsb 4 | |
252 | #define reg_dma_rw_intr_mask___stream_cmd___width 1 | |
253 | #define reg_dma_rw_intr_mask___stream_cmd___bit 4 | |
254 | #define reg_dma_rw_intr_mask_offset 140 | |
255 | ||
256 | /* Register rw_ack_intr, scope dma, type rw */ | |
257 | #define reg_dma_rw_ack_intr___group___lsb 0 | |
258 | #define reg_dma_rw_ack_intr___group___width 1 | |
259 | #define reg_dma_rw_ack_intr___group___bit 0 | |
260 | #define reg_dma_rw_ack_intr___ctxt___lsb 1 | |
261 | #define reg_dma_rw_ack_intr___ctxt___width 1 | |
262 | #define reg_dma_rw_ack_intr___ctxt___bit 1 | |
263 | #define reg_dma_rw_ack_intr___data___lsb 2 | |
264 | #define reg_dma_rw_ack_intr___data___width 1 | |
265 | #define reg_dma_rw_ack_intr___data___bit 2 | |
266 | #define reg_dma_rw_ack_intr___in_eop___lsb 3 | |
267 | #define reg_dma_rw_ack_intr___in_eop___width 1 | |
268 | #define reg_dma_rw_ack_intr___in_eop___bit 3 | |
269 | #define reg_dma_rw_ack_intr___stream_cmd___lsb 4 | |
270 | #define reg_dma_rw_ack_intr___stream_cmd___width 1 | |
271 | #define reg_dma_rw_ack_intr___stream_cmd___bit 4 | |
272 | #define reg_dma_rw_ack_intr_offset 144 | |
273 | ||
274 | /* Register r_intr, scope dma, type r */ | |
275 | #define reg_dma_r_intr___group___lsb 0 | |
276 | #define reg_dma_r_intr___group___width 1 | |
277 | #define reg_dma_r_intr___group___bit 0 | |
278 | #define reg_dma_r_intr___ctxt___lsb 1 | |
279 | #define reg_dma_r_intr___ctxt___width 1 | |
280 | #define reg_dma_r_intr___ctxt___bit 1 | |
281 | #define reg_dma_r_intr___data___lsb 2 | |
282 | #define reg_dma_r_intr___data___width 1 | |
283 | #define reg_dma_r_intr___data___bit 2 | |
284 | #define reg_dma_r_intr___in_eop___lsb 3 | |
285 | #define reg_dma_r_intr___in_eop___width 1 | |
286 | #define reg_dma_r_intr___in_eop___bit 3 | |
287 | #define reg_dma_r_intr___stream_cmd___lsb 4 | |
288 | #define reg_dma_r_intr___stream_cmd___width 1 | |
289 | #define reg_dma_r_intr___stream_cmd___bit 4 | |
290 | #define reg_dma_r_intr_offset 148 | |
291 | ||
292 | /* Register r_masked_intr, scope dma, type r */ | |
293 | #define reg_dma_r_masked_intr___group___lsb 0 | |
294 | #define reg_dma_r_masked_intr___group___width 1 | |
295 | #define reg_dma_r_masked_intr___group___bit 0 | |
296 | #define reg_dma_r_masked_intr___ctxt___lsb 1 | |
297 | #define reg_dma_r_masked_intr___ctxt___width 1 | |
298 | #define reg_dma_r_masked_intr___ctxt___bit 1 | |
299 | #define reg_dma_r_masked_intr___data___lsb 2 | |
300 | #define reg_dma_r_masked_intr___data___width 1 | |
301 | #define reg_dma_r_masked_intr___data___bit 2 | |
302 | #define reg_dma_r_masked_intr___in_eop___lsb 3 | |
303 | #define reg_dma_r_masked_intr___in_eop___width 1 | |
304 | #define reg_dma_r_masked_intr___in_eop___bit 3 | |
305 | #define reg_dma_r_masked_intr___stream_cmd___lsb 4 | |
306 | #define reg_dma_r_masked_intr___stream_cmd___width 1 | |
307 | #define reg_dma_r_masked_intr___stream_cmd___bit 4 | |
308 | #define reg_dma_r_masked_intr_offset 152 | |
309 | ||
310 | /* Register rw_stream_cmd, scope dma, type rw */ | |
311 | #define reg_dma_rw_stream_cmd___cmd___lsb 0 | |
312 | #define reg_dma_rw_stream_cmd___cmd___width 10 | |
313 | #define reg_dma_rw_stream_cmd___n___lsb 16 | |
314 | #define reg_dma_rw_stream_cmd___n___width 8 | |
315 | #define reg_dma_rw_stream_cmd___busy___lsb 31 | |
316 | #define reg_dma_rw_stream_cmd___busy___width 1 | |
317 | #define reg_dma_rw_stream_cmd___busy___bit 31 | |
318 | #define reg_dma_rw_stream_cmd_offset 156 | |
319 | ||
320 | ||
321 | /* Constants */ | |
322 | #define regk_dma_ack_pkt 0x00000100 | |
323 | #define regk_dma_anytime 0x00000001 | |
324 | #define regk_dma_array 0x00000008 | |
325 | #define regk_dma_burst 0x00000020 | |
326 | #define regk_dma_client 0x00000002 | |
327 | #define regk_dma_copy_next 0x00000010 | |
328 | #define regk_dma_copy_up 0x00000020 | |
329 | #define regk_dma_data_at_eol 0x00000001 | |
330 | #define regk_dma_dis_c 0x00000010 | |
331 | #define regk_dma_dis_g 0x00000020 | |
332 | #define regk_dma_idle 0x00000001 | |
333 | #define regk_dma_intern 0x00000004 | |
334 | #define regk_dma_load_c 0x00000200 | |
335 | #define regk_dma_load_c_n 0x00000280 | |
336 | #define regk_dma_load_c_next 0x00000240 | |
337 | #define regk_dma_load_d 0x00000140 | |
338 | #define regk_dma_load_g 0x00000300 | |
339 | #define regk_dma_load_g_down 0x000003c0 | |
340 | #define regk_dma_load_g_next 0x00000340 | |
341 | #define regk_dma_load_g_up 0x00000380 | |
342 | #define regk_dma_next_en 0x00000010 | |
343 | #define regk_dma_next_pkt 0x00000010 | |
344 | #define regk_dma_no 0x00000000 | |
345 | #define regk_dma_only_at_wait 0x00000000 | |
346 | #define regk_dma_restore 0x00000020 | |
347 | #define regk_dma_rst 0x00000001 | |
348 | #define regk_dma_running 0x00000004 | |
349 | #define regk_dma_rw_cfg_default 0x00000000 | |
350 | #define regk_dma_rw_cmd_default 0x00000000 | |
351 | #define regk_dma_rw_intr_mask_default 0x00000000 | |
352 | #define regk_dma_rw_stat_default 0x00000101 | |
353 | #define regk_dma_rw_stream_cmd_default 0x00000000 | |
354 | #define regk_dma_save_down 0x00000020 | |
355 | #define regk_dma_save_up 0x00000020 | |
356 | #define regk_dma_set_reg 0x00000050 | |
357 | #define regk_dma_set_w_size1 0x00000190 | |
358 | #define regk_dma_set_w_size2 0x000001a0 | |
359 | #define regk_dma_set_w_size4 0x000001c0 | |
360 | #define regk_dma_stopped 0x00000002 | |
361 | #define regk_dma_store_c 0x00000002 | |
362 | #define regk_dma_store_descr 0x00000000 | |
363 | #define regk_dma_store_g 0x00000004 | |
364 | #define regk_dma_store_md 0x00000001 | |
365 | #define regk_dma_sw 0x00000008 | |
366 | #define regk_dma_update_down 0x00000020 | |
367 | #define regk_dma_yes 0x00000001 | |
368 | #endif /* __dma_defs_asm_h */ |