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1 | #ifndef __bif_slave_defs_asm_h |
2 | #define __bif_slave_defs_asm_h | |
3 | ||
4 | /* | |
5 | * This file is autogenerated from | |
6 | * file: ../../inst/bif/rtl/bif_slave_regs.r | |
7 | * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp | |
8 | * last modfied: Mon Apr 11 16:06:34 2005 | |
9 | * | |
10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_slave_defs_asm.h ../../inst/bif/rtl/bif_slave_regs.r | |
11 | * id: $Id: bif_slave_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | |
12 | * Any changes here will be lost. | |
13 | * | |
14 | * -*- buffer-read-only: t -*- | |
15 | */ | |
16 | ||
17 | #ifndef REG_FIELD | |
18 | #define REG_FIELD( scope, reg, field, value ) \ | |
19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | |
20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | |
21 | #endif | |
22 | ||
23 | #ifndef REG_STATE | |
24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | |
25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | |
26 | #define REG_STATE_X_( k, shift ) (k << shift) | |
27 | #endif | |
28 | ||
29 | #ifndef REG_MASK | |
30 | #define REG_MASK( scope, reg, field ) \ | |
31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | |
32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | |
33 | #endif | |
34 | ||
35 | #ifndef REG_LSB | |
36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | |
37 | #endif | |
38 | ||
39 | #ifndef REG_BIT | |
40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | |
41 | #endif | |
42 | ||
43 | #ifndef REG_ADDR | |
44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | |
45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | |
46 | #endif | |
47 | ||
48 | #ifndef REG_ADDR_VECT | |
49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | |
51 | STRIDE_##scope##_##reg ) | |
52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | |
53 | ((inst) + offs + (index) * stride) | |
54 | #endif | |
55 | ||
56 | /* Register rw_slave_cfg, scope bif_slave, type rw */ | |
57 | #define reg_bif_slave_rw_slave_cfg___slave_id___lsb 0 | |
58 | #define reg_bif_slave_rw_slave_cfg___slave_id___width 3 | |
59 | #define reg_bif_slave_rw_slave_cfg___use_slave_id___lsb 3 | |
60 | #define reg_bif_slave_rw_slave_cfg___use_slave_id___width 1 | |
61 | #define reg_bif_slave_rw_slave_cfg___use_slave_id___bit 3 | |
62 | #define reg_bif_slave_rw_slave_cfg___boot_rdy___lsb 4 | |
63 | #define reg_bif_slave_rw_slave_cfg___boot_rdy___width 1 | |
64 | #define reg_bif_slave_rw_slave_cfg___boot_rdy___bit 4 | |
65 | #define reg_bif_slave_rw_slave_cfg___loopback___lsb 5 | |
66 | #define reg_bif_slave_rw_slave_cfg___loopback___width 1 | |
67 | #define reg_bif_slave_rw_slave_cfg___loopback___bit 5 | |
68 | #define reg_bif_slave_rw_slave_cfg___dis___lsb 6 | |
69 | #define reg_bif_slave_rw_slave_cfg___dis___width 1 | |
70 | #define reg_bif_slave_rw_slave_cfg___dis___bit 6 | |
71 | #define reg_bif_slave_rw_slave_cfg_offset 0 | |
72 | ||
73 | /* Register r_slave_mode, scope bif_slave, type r */ | |
74 | #define reg_bif_slave_r_slave_mode___ch0_mode___lsb 0 | |
75 | #define reg_bif_slave_r_slave_mode___ch0_mode___width 1 | |
76 | #define reg_bif_slave_r_slave_mode___ch0_mode___bit 0 | |
77 | #define reg_bif_slave_r_slave_mode___ch1_mode___lsb 1 | |
78 | #define reg_bif_slave_r_slave_mode___ch1_mode___width 1 | |
79 | #define reg_bif_slave_r_slave_mode___ch1_mode___bit 1 | |
80 | #define reg_bif_slave_r_slave_mode___ch2_mode___lsb 2 | |
81 | #define reg_bif_slave_r_slave_mode___ch2_mode___width 1 | |
82 | #define reg_bif_slave_r_slave_mode___ch2_mode___bit 2 | |
83 | #define reg_bif_slave_r_slave_mode___ch3_mode___lsb 3 | |
84 | #define reg_bif_slave_r_slave_mode___ch3_mode___width 1 | |
85 | #define reg_bif_slave_r_slave_mode___ch3_mode___bit 3 | |
86 | #define reg_bif_slave_r_slave_mode_offset 4 | |
87 | ||
88 | /* Register rw_ch0_cfg, scope bif_slave, type rw */ | |
89 | #define reg_bif_slave_rw_ch0_cfg___rd_hold___lsb 0 | |
90 | #define reg_bif_slave_rw_ch0_cfg___rd_hold___width 2 | |
91 | #define reg_bif_slave_rw_ch0_cfg___access_mode___lsb 2 | |
92 | #define reg_bif_slave_rw_ch0_cfg___access_mode___width 1 | |
93 | #define reg_bif_slave_rw_ch0_cfg___access_mode___bit 2 | |
94 | #define reg_bif_slave_rw_ch0_cfg___access_ctrl___lsb 3 | |
95 | #define reg_bif_slave_rw_ch0_cfg___access_ctrl___width 1 | |
96 | #define reg_bif_slave_rw_ch0_cfg___access_ctrl___bit 3 | |
97 | #define reg_bif_slave_rw_ch0_cfg___data_cs___lsb 4 | |
98 | #define reg_bif_slave_rw_ch0_cfg___data_cs___width 2 | |
99 | #define reg_bif_slave_rw_ch0_cfg_offset 16 | |
100 | ||
101 | /* Register rw_ch1_cfg, scope bif_slave, type rw */ | |
102 | #define reg_bif_slave_rw_ch1_cfg___rd_hold___lsb 0 | |
103 | #define reg_bif_slave_rw_ch1_cfg___rd_hold___width 2 | |
104 | #define reg_bif_slave_rw_ch1_cfg___access_mode___lsb 2 | |
105 | #define reg_bif_slave_rw_ch1_cfg___access_mode___width 1 | |
106 | #define reg_bif_slave_rw_ch1_cfg___access_mode___bit 2 | |
107 | #define reg_bif_slave_rw_ch1_cfg___access_ctrl___lsb 3 | |
108 | #define reg_bif_slave_rw_ch1_cfg___access_ctrl___width 1 | |
109 | #define reg_bif_slave_rw_ch1_cfg___access_ctrl___bit 3 | |
110 | #define reg_bif_slave_rw_ch1_cfg___data_cs___lsb 4 | |
111 | #define reg_bif_slave_rw_ch1_cfg___data_cs___width 2 | |
112 | #define reg_bif_slave_rw_ch1_cfg_offset 20 | |
113 | ||
114 | /* Register rw_ch2_cfg, scope bif_slave, type rw */ | |
115 | #define reg_bif_slave_rw_ch2_cfg___rd_hold___lsb 0 | |
116 | #define reg_bif_slave_rw_ch2_cfg___rd_hold___width 2 | |
117 | #define reg_bif_slave_rw_ch2_cfg___access_mode___lsb 2 | |
118 | #define reg_bif_slave_rw_ch2_cfg___access_mode___width 1 | |
119 | #define reg_bif_slave_rw_ch2_cfg___access_mode___bit 2 | |
120 | #define reg_bif_slave_rw_ch2_cfg___access_ctrl___lsb 3 | |
121 | #define reg_bif_slave_rw_ch2_cfg___access_ctrl___width 1 | |
122 | #define reg_bif_slave_rw_ch2_cfg___access_ctrl___bit 3 | |
123 | #define reg_bif_slave_rw_ch2_cfg___data_cs___lsb 4 | |
124 | #define reg_bif_slave_rw_ch2_cfg___data_cs___width 2 | |
125 | #define reg_bif_slave_rw_ch2_cfg_offset 24 | |
126 | ||
127 | /* Register rw_ch3_cfg, scope bif_slave, type rw */ | |
128 | #define reg_bif_slave_rw_ch3_cfg___rd_hold___lsb 0 | |
129 | #define reg_bif_slave_rw_ch3_cfg___rd_hold___width 2 | |
130 | #define reg_bif_slave_rw_ch3_cfg___access_mode___lsb 2 | |
131 | #define reg_bif_slave_rw_ch3_cfg___access_mode___width 1 | |
132 | #define reg_bif_slave_rw_ch3_cfg___access_mode___bit 2 | |
133 | #define reg_bif_slave_rw_ch3_cfg___access_ctrl___lsb 3 | |
134 | #define reg_bif_slave_rw_ch3_cfg___access_ctrl___width 1 | |
135 | #define reg_bif_slave_rw_ch3_cfg___access_ctrl___bit 3 | |
136 | #define reg_bif_slave_rw_ch3_cfg___data_cs___lsb 4 | |
137 | #define reg_bif_slave_rw_ch3_cfg___data_cs___width 2 | |
138 | #define reg_bif_slave_rw_ch3_cfg_offset 28 | |
139 | ||
140 | /* Register rw_arb_cfg, scope bif_slave, type rw */ | |
141 | #define reg_bif_slave_rw_arb_cfg___brin_mode___lsb 0 | |
142 | #define reg_bif_slave_rw_arb_cfg___brin_mode___width 1 | |
143 | #define reg_bif_slave_rw_arb_cfg___brin_mode___bit 0 | |
144 | #define reg_bif_slave_rw_arb_cfg___brout_mode___lsb 1 | |
145 | #define reg_bif_slave_rw_arb_cfg___brout_mode___width 3 | |
146 | #define reg_bif_slave_rw_arb_cfg___bg_mode___lsb 4 | |
147 | #define reg_bif_slave_rw_arb_cfg___bg_mode___width 3 | |
148 | #define reg_bif_slave_rw_arb_cfg___release___lsb 7 | |
149 | #define reg_bif_slave_rw_arb_cfg___release___width 2 | |
150 | #define reg_bif_slave_rw_arb_cfg___acquire___lsb 9 | |
151 | #define reg_bif_slave_rw_arb_cfg___acquire___width 1 | |
152 | #define reg_bif_slave_rw_arb_cfg___acquire___bit 9 | |
153 | #define reg_bif_slave_rw_arb_cfg___settle_time___lsb 10 | |
154 | #define reg_bif_slave_rw_arb_cfg___settle_time___width 2 | |
155 | #define reg_bif_slave_rw_arb_cfg___dram_ctrl___lsb 12 | |
156 | #define reg_bif_slave_rw_arb_cfg___dram_ctrl___width 1 | |
157 | #define reg_bif_slave_rw_arb_cfg___dram_ctrl___bit 12 | |
158 | #define reg_bif_slave_rw_arb_cfg_offset 32 | |
159 | ||
160 | /* Register r_arb_stat, scope bif_slave, type r */ | |
161 | #define reg_bif_slave_r_arb_stat___init_mode___lsb 0 | |
162 | #define reg_bif_slave_r_arb_stat___init_mode___width 1 | |
163 | #define reg_bif_slave_r_arb_stat___init_mode___bit 0 | |
164 | #define reg_bif_slave_r_arb_stat___mode___lsb 1 | |
165 | #define reg_bif_slave_r_arb_stat___mode___width 1 | |
166 | #define reg_bif_slave_r_arb_stat___mode___bit 1 | |
167 | #define reg_bif_slave_r_arb_stat___brin___lsb 2 | |
168 | #define reg_bif_slave_r_arb_stat___brin___width 1 | |
169 | #define reg_bif_slave_r_arb_stat___brin___bit 2 | |
170 | #define reg_bif_slave_r_arb_stat___brout___lsb 3 | |
171 | #define reg_bif_slave_r_arb_stat___brout___width 1 | |
172 | #define reg_bif_slave_r_arb_stat___brout___bit 3 | |
173 | #define reg_bif_slave_r_arb_stat___bg___lsb 4 | |
174 | #define reg_bif_slave_r_arb_stat___bg___width 1 | |
175 | #define reg_bif_slave_r_arb_stat___bg___bit 4 | |
176 | #define reg_bif_slave_r_arb_stat_offset 36 | |
177 | ||
178 | /* Register rw_intr_mask, scope bif_slave, type rw */ | |
179 | #define reg_bif_slave_rw_intr_mask___bus_release___lsb 0 | |
180 | #define reg_bif_slave_rw_intr_mask___bus_release___width 1 | |
181 | #define reg_bif_slave_rw_intr_mask___bus_release___bit 0 | |
182 | #define reg_bif_slave_rw_intr_mask___bus_acquire___lsb 1 | |
183 | #define reg_bif_slave_rw_intr_mask___bus_acquire___width 1 | |
184 | #define reg_bif_slave_rw_intr_mask___bus_acquire___bit 1 | |
185 | #define reg_bif_slave_rw_intr_mask_offset 64 | |
186 | ||
187 | /* Register rw_ack_intr, scope bif_slave, type rw */ | |
188 | #define reg_bif_slave_rw_ack_intr___bus_release___lsb 0 | |
189 | #define reg_bif_slave_rw_ack_intr___bus_release___width 1 | |
190 | #define reg_bif_slave_rw_ack_intr___bus_release___bit 0 | |
191 | #define reg_bif_slave_rw_ack_intr___bus_acquire___lsb 1 | |
192 | #define reg_bif_slave_rw_ack_intr___bus_acquire___width 1 | |
193 | #define reg_bif_slave_rw_ack_intr___bus_acquire___bit 1 | |
194 | #define reg_bif_slave_rw_ack_intr_offset 68 | |
195 | ||
196 | /* Register r_intr, scope bif_slave, type r */ | |
197 | #define reg_bif_slave_r_intr___bus_release___lsb 0 | |
198 | #define reg_bif_slave_r_intr___bus_release___width 1 | |
199 | #define reg_bif_slave_r_intr___bus_release___bit 0 | |
200 | #define reg_bif_slave_r_intr___bus_acquire___lsb 1 | |
201 | #define reg_bif_slave_r_intr___bus_acquire___width 1 | |
202 | #define reg_bif_slave_r_intr___bus_acquire___bit 1 | |
203 | #define reg_bif_slave_r_intr_offset 72 | |
204 | ||
205 | /* Register r_masked_intr, scope bif_slave, type r */ | |
206 | #define reg_bif_slave_r_masked_intr___bus_release___lsb 0 | |
207 | #define reg_bif_slave_r_masked_intr___bus_release___width 1 | |
208 | #define reg_bif_slave_r_masked_intr___bus_release___bit 0 | |
209 | #define reg_bif_slave_r_masked_intr___bus_acquire___lsb 1 | |
210 | #define reg_bif_slave_r_masked_intr___bus_acquire___width 1 | |
211 | #define reg_bif_slave_r_masked_intr___bus_acquire___bit 1 | |
212 | #define reg_bif_slave_r_masked_intr_offset 76 | |
213 | ||
214 | ||
215 | /* Constants */ | |
216 | #define regk_bif_slave_active_hi 0x00000003 | |
217 | #define regk_bif_slave_active_lo 0x00000002 | |
218 | #define regk_bif_slave_addr 0x00000000 | |
219 | #define regk_bif_slave_always 0x00000001 | |
220 | #define regk_bif_slave_at_idle 0x00000002 | |
221 | #define regk_bif_slave_burst_end 0x00000003 | |
222 | #define regk_bif_slave_dma 0x00000001 | |
223 | #define regk_bif_slave_hi 0x00000003 | |
224 | #define regk_bif_slave_inv 0x00000001 | |
225 | #define regk_bif_slave_lo 0x00000002 | |
226 | #define regk_bif_slave_local 0x00000001 | |
227 | #define regk_bif_slave_master 0x00000000 | |
228 | #define regk_bif_slave_mode_reg 0x00000001 | |
229 | #define regk_bif_slave_no 0x00000000 | |
230 | #define regk_bif_slave_norm 0x00000000 | |
231 | #define regk_bif_slave_on_access 0x00000000 | |
232 | #define regk_bif_slave_rw_arb_cfg_default 0x00000000 | |
233 | #define regk_bif_slave_rw_ch0_cfg_default 0x00000000 | |
234 | #define regk_bif_slave_rw_ch1_cfg_default 0x00000000 | |
235 | #define regk_bif_slave_rw_ch2_cfg_default 0x00000000 | |
236 | #define regk_bif_slave_rw_ch3_cfg_default 0x00000000 | |
237 | #define regk_bif_slave_rw_intr_mask_default 0x00000000 | |
238 | #define regk_bif_slave_rw_slave_cfg_default 0x00000000 | |
239 | #define regk_bif_slave_shared 0x00000000 | |
240 | #define regk_bif_slave_slave 0x00000001 | |
241 | #define regk_bif_slave_t0ns 0x00000003 | |
242 | #define regk_bif_slave_t10ns 0x00000002 | |
243 | #define regk_bif_slave_t20ns 0x00000003 | |
244 | #define regk_bif_slave_t30ns 0x00000002 | |
245 | #define regk_bif_slave_t40ns 0x00000001 | |
246 | #define regk_bif_slave_t50ns 0x00000000 | |
247 | #define regk_bif_slave_yes 0x00000001 | |
248 | #define regk_bif_slave_z 0x00000004 | |
249 | #endif /* __bif_slave_defs_asm_h */ |