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[net-next-2.6.git] / arch / cris / arch-v32 / drivers / sync_serial.c
CommitLineData
51533b61 1/*
e908dfc3 2 * Simple synchronous serial port driver for ETRAX FS and Artpec-3.
51533b61
MS		 3 *
4 * Copyright (c) 2005 Axis Communications AB
5 *
6 * Author: Mikael Starvik
7 *
8 */
9
10#include <linux/module.h>
11#include <linux/kernel.h>
51533b61
MS		 12#include <linux/types.h>
13#include <linux/errno.h>
14#include <linux/major.h>
15#include <linux/sched.h>
0c401df3 16#include <linux/smp_lock.h>
51533b61
MS		 17#include <linux/interrupt.h>
18#include <linux/poll.h>
19#include <linux/init.h>
20#include <linux/timer.h>
21#include <linux/spinlock.h>
22
23#include <asm/io.h>
e908dfc3
JN		 24#include <dma.h>
25#include <pinmux.h>
26#include <hwregs/reg_rdwr.h>
27#include <hwregs/sser_defs.h>
28#include <hwregs/dma_defs.h>
29#include <hwregs/dma.h>
30#include <hwregs/intr_vect_defs.h>
31#include <hwregs/intr_vect.h>
32#include <hwregs/reg_map.h>
51533b61
MS		 33#include <asm/sync_serial.h>
34
e908dfc3 35
51533b61
MS		 36/* The receiver is a bit tricky beacuse of the continuous stream of data.*/
37/* */
38/* Three DMA descriptors are linked together. Each DMA descriptor is */
39/* responsible for port->bufchunk of a common buffer. */
40/* */
41/* +---------------------------------------------+ */
42/* | +----------+ +----------+ +----------+ | */
43/* +-> | Descr[0] |-->| Descr[1] |-->| Descr[2] |-+ */
44/* +----------+ +----------+ +----------+ */
45/* | | | */
46/* v v v */
47/* +-------------------------------------+ */
48/* | BUFFER | */
49/* +-------------------------------------+ */
50/* |<- data_avail ->| */
51/* readp writep */
52/* */
53/* If the application keeps up the pace readp will be right after writep.*/
54/* If the application can't keep the pace we have to throw away data. */
55/* The idea is that readp should be ready with the data pointed out by */
56/* Descr[i] when the DMA has filled in Descr[i+1]. */
57/* Otherwise we will discard */
58/* the rest of the data pointed out by Descr1 and set readp to the start */
59/* of Descr2 */
60
61#define SYNC_SERIAL_MAJOR 125
62
63/* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */
64/* words can be handled */
65#define IN_BUFFER_SIZE 12288
66#define IN_DESCR_SIZE 256
e908dfc3
JN		 67#define NBR_IN_DESCR (IN_BUFFER_SIZE/IN_DESCR_SIZE)
68
69#define OUT_BUFFER_SIZE 1024*8
70#define NBR_OUT_DESCR 8
51533b61
MS		 71
72#define DEFAULT_FRAME_RATE 0
73#define DEFAULT_WORD_RATE 7
74
75/* NOTE: Enabling some debug will likely cause overrun or underrun,
76 * especially if manual mode is use.
77 */
78#define DEBUG(x)
79#define DEBUGREAD(x)
80#define DEBUGWRITE(x)
81#define DEBUGPOLL(x)
82#define DEBUGRXINT(x)
83#define DEBUGTXINT(x)
e908dfc3
JN		 84#define DEBUGTRDMA(x)
85#define DEBUGOUTBUF(x)
51533b61
MS		 86
87typedef struct sync_port
88{
89 reg_scope_instances regi_sser;
90 reg_scope_instances regi_dmain;
91 reg_scope_instances regi_dmaout;
92
93 char started; /* 1 if port has been started */
94 char port_nbr; /* Port 0 or 1 */
95 char busy; /* 1 if port is busy */
96
97 char enabled; /* 1 if port is enabled */
98 char use_dma; /* 1 if port uses dma */
99 char tr_running;
100
101 char init_irqs;
102 int output;
103 int input;
104
e908dfc3
JN		 105 /* Next byte to be read by application */
106 volatile unsigned char *volatile readp;
107 /* Next byte to be written by etrax */
108 volatile unsigned char *volatile writep;
109
51533b61
MS		 110 unsigned int in_buffer_size;
111 unsigned int inbufchunk;
112 unsigned char out_buffer[OUT_BUFFER_SIZE] __attribute__ ((aligned(32)));
113 unsigned char in_buffer[IN_BUFFER_SIZE]__attribute__ ((aligned(32)));
114 unsigned char flip[IN_BUFFER_SIZE] __attribute__ ((aligned(32)));
115 struct dma_descr_data* next_rx_desc;
116 struct dma_descr_data* prev_rx_desc;
e908dfc3
JN		 117
118 /* Pointer to the first available descriptor in the ring,
119 * unless active_tr_descr == catch_tr_descr and a dma
120 * transfer is active */
121 struct dma_descr_data *active_tr_descr;
122
123 /* Pointer to the first allocated descriptor in the ring */
124 struct dma_descr_data *catch_tr_descr;
125
126 /* Pointer to the descriptor with the current end-of-list */
127 struct dma_descr_data *prev_tr_descr;
51533b61
MS		 128 int full;
129
e908dfc3
JN		 130 /* Pointer to the first byte being read by DMA
131 * or current position in out_buffer if not using DMA. */
132 unsigned char *out_rd_ptr;
133
134 /* Number of bytes currently locked for being read by DMA */
135 int out_buf_count;
136
137 dma_descr_data in_descr[NBR_IN_DESCR] __attribute__ ((__aligned__(16)));
51533b61 138 dma_descr_context in_context __attribute__ ((__aligned__(32)));
e908dfc3
JN		 139 dma_descr_data out_descr[NBR_OUT_DESCR]
140 __attribute__ ((__aligned__(16)));
51533b61
MS		 141 dma_descr_context out_context __attribute__ ((__aligned__(32)));
142 wait_queue_head_t out_wait_q;
143 wait_queue_head_t in_wait_q;
144
145 spinlock_t lock;
146} sync_port;
147
148static int etrax_sync_serial_init(void);
149static void initialize_port(int portnbr);
150static inline int sync_data_avail(struct sync_port *port);
151
152static int sync_serial_open(struct inode *, struct file*);
153static int sync_serial_release(struct inode*, struct file*);
154static unsigned int sync_serial_poll(struct file *filp, poll_table *wait);
155
90276a1a 156static int sync_serial_ioctl(struct file *,
51533b61
MS		 157 unsigned int cmd, unsigned long arg);
158static ssize_t sync_serial_write(struct file * file, const char * buf,
159 size_t count, loff_t *ppos);
160static ssize_t sync_serial_read(struct file *file, char *buf,
161 size_t count, loff_t *ppos);
162
163#if (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
164 defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
165 (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
166 defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA))
167#define SYNC_SER_DMA
168#endif
169
170static void send_word(sync_port* port);
e908dfc3 171static void start_dma_out(struct sync_port *port, const char *data, int count);
51533b61
MS		 172static void start_dma_in(sync_port* port);
173#ifdef SYNC_SER_DMA
e908dfc3
JN		 174static irqreturn_t tr_interrupt(int irq, void *dev_id);
175static irqreturn_t rx_interrupt(int irq, void *dev_id);
51533b61
MS		 176#endif
177
178#if (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
179 !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
180 (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
181 !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA))
182#define SYNC_SER_MANUAL
183#endif
184#ifdef SYNC_SER_MANUAL
e908dfc3
JN		 185static irqreturn_t manual_interrupt(int irq, void *dev_id);
186#endif
187
188#ifdef CONFIG_ETRAXFS /* ETRAX FS */
189#define OUT_DMA_NBR 4
190#define IN_DMA_NBR 5
191#define PINMUX_SSER pinmux_sser0
192#define SYNCSER_INST regi_sser0
193#define SYNCSER_INTR_VECT SSER0_INTR_VECT
194#define OUT_DMA_INST regi_dma4
195#define IN_DMA_INST regi_dma5
196#define DMA_OUT_INTR_VECT DMA4_INTR_VECT
197#define DMA_IN_INTR_VECT DMA5_INTR_VECT
198#define REQ_DMA_SYNCSER dma_sser0
199#else /* Artpec-3 */
200#define OUT_DMA_NBR 6
201#define IN_DMA_NBR 7
202#define PINMUX_SSER pinmux_sser
203#define SYNCSER_INST regi_sser
204#define SYNCSER_INTR_VECT SSER_INTR_VECT
205#define OUT_DMA_INST regi_dma6
206#define IN_DMA_INST regi_dma7
207#define DMA_OUT_INTR_VECT DMA6_INTR_VECT
208#define DMA_IN_INTR_VECT DMA7_INTR_VECT
209#define REQ_DMA_SYNCSER dma_sser
51533b61
MS		 210#endif
211
212/* The ports */
213static struct sync_port ports[]=
214{
215 {
e908dfc3
JN		 216 .regi_sser = SYNCSER_INST,
217 .regi_dmaout = OUT_DMA_INST,
218 .regi_dmain = IN_DMA_INST,
51533b61
MS		 219#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)
220 .use_dma = 1,
221#else
222 .use_dma = 0,
223#endif
e908dfc3
JN		 224 }
225#ifdef CONFIG_ETRAXFS
226 ,
227
51533b61
MS		 228 {
229 .regi_sser = regi_sser1,
230 .regi_dmaout = regi_dma6,
231 .regi_dmain = regi_dma7,
232#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)
233 .use_dma = 1,
234#else
235 .use_dma = 0,
236#endif
237 }
e908dfc3 238#endif
51533b61
MS		 239};
240
e908dfc3 241#define NBR_PORTS ARRAY_SIZE(ports)
51533b61 242
5dfe4c96 243static const struct file_operations sync_serial_fops = {
90276a1a
JN		 244 .owner = THIS_MODULE,
245 .write = sync_serial_write,
246 .read = sync_serial_read,
247 .poll = sync_serial_poll,
248 .unlocked_ioctl = sync_serial_ioctl,
249 .open = sync_serial_open,
250 .release = sync_serial_release
51533b61
MS		 251};
252
253static int __init etrax_sync_serial_init(void)
254{
255 ports[0].enabled = 0;
e908dfc3 256#ifdef CONFIG_ETRAXFS
51533b61 257 ports[1].enabled = 0;
e908dfc3
JN		 258#endif
259 if (register_chrdev(SYNC_SERIAL_MAJOR, "sync serial",
260 &sync_serial_fops) < 0) {
261 printk(KERN_WARNING
262 "Unable to get major for synchronous serial port\n");
51533b61
MS		 263 return -EBUSY;
264 }
265
266 /* Initialize Ports */
267#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
e908dfc3
JN		 268 if (crisv32_pinmux_alloc_fixed(PINMUX_SSER)) {
269 printk(KERN_WARNING
270 "Unable to alloc pins for synchronous serial port 0\n");
51533b61
MS		 271 return -EIO;
272 }
273 ports[0].enabled = 1;
274 initialize_port(0);
275#endif
276
277#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
e908dfc3
JN		 278 if (crisv32_pinmux_alloc_fixed(pinmux_sser1)) {
279 printk(KERN_WARNING
280 "Unable to alloc pins for synchronous serial port 0\n");
51533b61
MS		 281 return -EIO;
282 }
283 ports[1].enabled = 1;
284 initialize_port(1);
285#endif
286
e908dfc3
JN		 287#ifdef CONFIG_ETRAXFS
288 printk(KERN_INFO "ETRAX FS synchronous serial port driver\n");
289#else
290 printk(KERN_INFO "Artpec-3 synchronous serial port driver\n");
291#endif
51533b61
MS		 292 return 0;
293}
294
295static void __init initialize_port(int portnbr)
296{
e908dfc3
JN		 297 int __attribute__((unused)) i;
298 struct sync_port *port = &ports[portnbr];
51533b61
MS		 299 reg_sser_rw_cfg cfg = {0};
300 reg_sser_rw_frm_cfg frm_cfg = {0};
301 reg_sser_rw_tr_cfg tr_cfg = {0};
302 reg_sser_rw_rec_cfg rec_cfg = {0};
303
e908dfc3 304 DEBUG(printk(KERN_DEBUG "Init sync serial port %d\n", portnbr));
51533b61
MS		 305
306 port->port_nbr = portnbr;
307 port->init_irqs = 1;
308
e908dfc3
JN		 309 port->out_rd_ptr = port->out_buffer;
310 port->out_buf_count = 0;
311
51533b61
MS		 312 port->output = 1;
313 port->input = 0;
314
315 port->readp = port->flip;
316 port->writep = port->flip;
317 port->in_buffer_size = IN_BUFFER_SIZE;
318 port->inbufchunk = IN_DESCR_SIZE;
319 port->next_rx_desc = &port->in_descr[0];
e908dfc3 320 port->prev_rx_desc = &port->in_descr[NBR_IN_DESCR-1];
51533b61
MS		 321 port->prev_rx_desc->eol = 1;
322
323 init_waitqueue_head(&port->out_wait_q);
324 init_waitqueue_head(&port->in_wait_q);
325
326 spin_lock_init(&port->lock);
327
328 cfg.out_clk_src = regk_sser_intern_clk;
329 cfg.out_clk_pol = regk_sser_pos;
330 cfg.clk_od_mode = regk_sser_no;
331 cfg.clk_dir = regk_sser_out;
332 cfg.gate_clk = regk_sser_no;
333 cfg.base_freq = regk_sser_f29_493;
334 cfg.clk_div = 256;
335 REG_WR(sser, port->regi_sser, rw_cfg, cfg);
336
337 frm_cfg.wordrate = DEFAULT_WORD_RATE;
338 frm_cfg.type = regk_sser_edge;
339 frm_cfg.frame_pin_dir = regk_sser_out;
340 frm_cfg.frame_pin_use = regk_sser_frm;
341 frm_cfg.status_pin_dir = regk_sser_in;
342 frm_cfg.status_pin_use = regk_sser_hold;
343 frm_cfg.out_on = regk_sser_tr;
344 frm_cfg.tr_delay = 1;
345 REG_WR(sser, port->regi_sser, rw_frm_cfg, frm_cfg);
346
347 tr_cfg.urun_stop = regk_sser_no;
348 tr_cfg.sample_size = 7;
349 tr_cfg.sh_dir = regk_sser_msbfirst;
350 tr_cfg.use_dma = port->use_dma ? regk_sser_yes : regk_sser_no;
e908dfc3 351#if 0
51533b61
MS		 352 tr_cfg.rate_ctrl = regk_sser_bulk;
353 tr_cfg.data_pin_use = regk_sser_dout;
e908dfc3
JN		 354#else
355 tr_cfg.rate_ctrl = regk_sser_iso;
356 tr_cfg.data_pin_use = regk_sser_dout;
357#endif
51533b61
MS		 358 tr_cfg.bulk_wspace = 1;
359 REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
360
361 rec_cfg.sample_size = 7;
362 rec_cfg.sh_dir = regk_sser_msbfirst;
363 rec_cfg.use_dma = port->use_dma ? regk_sser_yes : regk_sser_no;
364 rec_cfg.fifo_thr = regk_sser_inf;
365 REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
e908dfc3
JN		 366
367#ifdef SYNC_SER_DMA
368 /* Setup the descriptor ring for dma out/transmit. */
369 for (i = 0; i < NBR_OUT_DESCR; i++) {
370 port->out_descr[i].wait = 0;
371 port->out_descr[i].intr = 1;
372 port->out_descr[i].eol = 0;
373 port->out_descr[i].out_eop = 0;
374 port->out_descr[i].next =
375 (dma_descr_data *)virt_to_phys(&port->out_descr[i+1]);
376 }
377
378 /* Create a ring from the list. */
379 port->out_descr[NBR_OUT_DESCR-1].next =
380 (dma_descr_data *)virt_to_phys(&port->out_descr[0]);
381
382 /* Setup context for traversing the ring. */
383 port->active_tr_descr = &port->out_descr[0];
384 port->prev_tr_descr = &port->out_descr[NBR_OUT_DESCR-1];
385 port->catch_tr_descr = &port->out_descr[0];
386#endif
51533b61
MS		 387}
388
389static inline int sync_data_avail(struct sync_port *port)
390{
391 int avail;
392 unsigned char *start;
393 unsigned char *end;
394
395 start = (unsigned char*)port->readp; /* cast away volatile */
396 end = (unsigned char*)port->writep; /* cast away volatile */
397 /* 0123456789 0123456789
398 * ----- - -----
399 * ^rp ^wp ^wp ^rp
400 */
401
e908dfc3 402 if (end >= start)
51533b61
MS		 403 avail = end - start;
404 else
405 avail = port->in_buffer_size - (start - end);
406 return avail;
407}
408
409static inline int sync_data_avail_to_end(struct sync_port *port)
410{
411 int avail;
412 unsigned char *start;
413 unsigned char *end;
414
415 start = (unsigned char*)port->readp; /* cast away volatile */
416 end = (unsigned char*)port->writep; /* cast away volatile */
417 /* 0123456789 0123456789
418 * ----- -----
419 * ^rp ^wp ^wp ^rp
420 */
421
e908dfc3 422 if (end >= start)
51533b61
MS		 423 avail = end - start;
424 else
425 avail = port->flip + port->in_buffer_size - start;
426 return avail;
427}
428
429static int sync_serial_open(struct inode *inode, struct file *file)
430{
32ea086b 431 int dev = iminor(inode);
0c401df3 432 int ret = -EBUSY;
e908dfc3 433 sync_port *port;
51533b61
MS		 434 reg_dma_rw_cfg cfg = {.en = regk_dma_yes};
435 reg_dma_rw_intr_mask intr_mask = {.data = regk_dma_yes};
436
0c401df3 437 lock_kernel();
e908dfc3 438 DEBUG(printk(KERN_DEBUG "Open sync serial port %d\n", dev));
51533b61 439
e908dfc3 440 if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled)
51533b61 441 {
e908dfc3 442 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
0c401df3
JC		 443 ret = -ENODEV;
444 goto out;
51533b61
MS		 445 }
446 port = &ports[dev];
447 /* Allow open this device twice (assuming one reader and one writer) */
448 if (port->busy == 2)
449 {
e908dfc3 450 DEBUG(printk(KERN_DEBUG "Device is busy.. \n"));
0c401df3 451 goto out;
51533b61 452 }
e908dfc3
JN		 453
454
51533b61
MS		 455 if (port->init_irqs) {
456 if (port->use_dma) {
e908dfc3 457 if (port == &ports[0]) {
51533b61 458#ifdef SYNC_SER_DMA
e908dfc3
JN		 459 if (request_irq(DMA_OUT_INTR_VECT,
460 tr_interrupt,
461 0,
462 "synchronous serial 0 dma tr",
463 &ports[0])) {
51533b61 464 printk(KERN_CRIT "Can't allocate sync serial port 0 IRQ");
0c401df3 465 goto out;
e908dfc3
JN		 466 } else if (request_irq(DMA_IN_INTR_VECT,
467 rx_interrupt,
468 0,
469 "synchronous serial 1 dma rx",
470 &ports[0])) {
471 free_irq(DMA_OUT_INTR_VECT, &port[0]);
51533b61 472 printk(KERN_CRIT "Can't allocate sync serial port 0 IRQ");
0c401df3 473 goto out;
e908dfc3
JN		 474 } else if (crisv32_request_dma(OUT_DMA_NBR,
475 "synchronous serial 0 dma tr",
476 DMA_VERBOSE_ON_ERROR,
477 0,
478 REQ_DMA_SYNCSER)) {
479 free_irq(DMA_OUT_INTR_VECT, &port[0]);
480 free_irq(DMA_IN_INTR_VECT, &port[0]);
51533b61 481 printk(KERN_CRIT "Can't allocate sync serial port 0 TX DMA channel");
0c401df3 482 goto out;
e908dfc3
JN		 483 } else if (crisv32_request_dma(IN_DMA_NBR,
484 "synchronous serial 0 dma rec",
485 DMA_VERBOSE_ON_ERROR,
486 0,
487 REQ_DMA_SYNCSER)) {
488 crisv32_free_dma(OUT_DMA_NBR);
489 free_irq(DMA_OUT_INTR_VECT, &port[0]);
490 free_irq(DMA_IN_INTR_VECT, &port[0]);
51533b61 491 printk(KERN_CRIT "Can't allocate sync serial port 1 RX DMA channel");
0c401df3 492 goto out;
51533b61
MS		 493 }
494#endif
495 }
e908dfc3
JN		 496#ifdef CONFIG_ETRAXFS
497 else if (port == &ports[1]) {
51533b61
MS		 498#ifdef SYNC_SER_DMA
499 if (request_irq(DMA6_INTR_VECT,
500 tr_interrupt,
501 0,
502 "synchronous serial 1 dma tr",
503 &ports[1])) {
504 printk(KERN_CRIT "Can't allocate sync serial port 1 IRQ");
0c401df3 505 goto out;
51533b61
MS		 506 } else if (request_irq(DMA7_INTR_VECT,
507 rx_interrupt,
508 0,
509 "synchronous serial 1 dma rx",
510 &ports[1])) {
511 free_irq(DMA6_INTR_VECT, &ports[1]);
512 printk(KERN_CRIT "Can't allocate sync serial port 3 IRQ");
0c401df3 513 goto out;
e908dfc3
JN		 514 } else if (crisv32_request_dma(
515 SYNC_SER1_TX_DMA_NBR,
516 "synchronous serial 1 dma tr",
517 DMA_VERBOSE_ON_ERROR,
518 0,
519 dma_sser1)) {
520 free_irq(DMA6_INTR_VECT, &ports[1]);
521 free_irq(DMA7_INTR_VECT, &ports[1]);
51533b61 522 printk(KERN_CRIT "Can't allocate sync serial port 3 TX DMA channel");
0c401df3 523 goto out;
e908dfc3
JN		 524 } else if (crisv32_request_dma(
525 SYNC_SER1_RX_DMA_NBR,
526 "synchronous serial 3 dma rec",
527 DMA_VERBOSE_ON_ERROR,
528 0,
529 dma_sser1)) {
51533b61
MS		 530 crisv32_free_dma(SYNC_SER1_TX_DMA_NBR);
531 free_irq(DMA6_INTR_VECT, &ports[1]);
532 free_irq(DMA7_INTR_VECT, &ports[1]);
533 printk(KERN_CRIT "Can't allocate sync serial port 3 RX DMA channel");
0c401df3 534 goto out;
51533b61
MS		 535 }
536#endif
537 }
e908dfc3 538#endif
51533b61
MS		 539 /* Enable DMAs */
540 REG_WR(dma, port->regi_dmain, rw_cfg, cfg);
541 REG_WR(dma, port->regi_dmaout, rw_cfg, cfg);
542 /* Enable DMA IRQs */
543 REG_WR(dma, port->regi_dmain, rw_intr_mask, intr_mask);
544 REG_WR(dma, port->regi_dmaout, rw_intr_mask, intr_mask);
e908dfc3 545 /* Set up wordsize = 1 for DMAs. */
51533b61
MS		 546 DMA_WR_CMD (port->regi_dmain, regk_dma_set_w_size1);
547 DMA_WR_CMD (port->regi_dmaout, regk_dma_set_w_size1);
548
549 start_dma_in(port);
550 port->init_irqs = 0;
551 } else { /* !port->use_dma */
552#ifdef SYNC_SER_MANUAL
553 if (port == &ports[0]) {
e908dfc3 554 if (request_irq(SYNCSER_INTR_VECT,
51533b61
MS		 555 manual_interrupt,
556 0,
557 "synchronous serial manual irq",
558 &ports[0])) {
559 printk("Can't allocate sync serial manual irq");
0c401df3 560 goto out;
51533b61 561 }
e908dfc3
JN		 562 }
563#ifdef CONFIG_ETRAXFS
564 else if (port == &ports[1]) {
51533b61
MS		 565 if (request_irq(SSER1_INTR_VECT,
566 manual_interrupt,
567 0,
568 "synchronous serial manual irq",
569 &ports[1])) {
570 printk(KERN_CRIT "Can't allocate sync serial manual irq");
0c401df3 571 goto out;
51533b61
MS		 572 }
573 }
e908dfc3 574#endif
51533b61
MS		 575 port->init_irqs = 0;
576#else
577 panic("sync_serial: Manual mode not supported.\n");
578#endif /* SYNC_SER_MANUAL */
579 }
e908dfc3 580
51533b61
MS		 581 } /* port->init_irqs */
582
583 port->busy++;
0c401df3
JC		 584 ret = 0;
585out:
586 unlock_kernel();
587 return ret;
51533b61
MS		 588}
589
590static int sync_serial_release(struct inode *inode, struct file *file)
591{
32ea086b 592 int dev = iminor(inode);
e908dfc3 593 sync_port *port;
51533b61 594
e908dfc3 595 if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled)
51533b61
MS		 596 {
597 DEBUG(printk("Invalid minor %d\n", dev));
598 return -ENODEV;
599 }
600 port = &ports[dev];
601 if (port->busy)
602 port->busy--;
603 if (!port->busy)
604 /* XXX */ ;
605 return 0;
606}
607
608static unsigned int sync_serial_poll(struct file *file, poll_table *wait)
609{
d817be9c 610 int dev = iminor(file->f_path.dentry->d_inode);
51533b61 611 unsigned int mask = 0;
e908dfc3 612 sync_port *port;
51533b61
MS		 613 DEBUGPOLL( static unsigned int prev_mask = 0; );
614
615 port = &ports[dev];
e908dfc3
JN		 616
617 if (!port->started) {
618 reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg);
619 reg_sser_rw_rec_cfg rec_cfg =
620 REG_RD(sser, port->regi_sser, rw_rec_cfg);
621 cfg.en = regk_sser_yes;
622 rec_cfg.rec_en = port->input;
623 REG_WR(sser, port->regi_sser, rw_cfg, cfg);
624 REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
625 port->started = 1;
626 }
627
51533b61
MS		 628 poll_wait(file, &port->out_wait_q, wait);
629 poll_wait(file, &port->in_wait_q, wait);
e908dfc3
JN		 630
631 /* No active transfer, descriptors are available */
632 if (port->output && !port->tr_running)
633 mask |= POLLOUT | POLLWRNORM;
634
635 /* Descriptor and buffer space available. */
636 if (port->output &&
637 port->active_tr_descr != port->catch_tr_descr &&
638 port->out_buf_count < OUT_BUFFER_SIZE)
51533b61 639 mask |= POLLOUT | POLLWRNORM;
e908dfc3 640
51533b61 641 /* At least an inbufchunk of data */
e908dfc3 642 if (port->input && sync_data_avail(port) >= port->inbufchunk)
51533b61
MS		 643 mask |= POLLIN | POLLRDNORM;
644
645 DEBUGPOLL(if (mask != prev_mask)
646 printk("sync_serial_poll: mask 0x%08X %s %s\n", mask,
647 mask&POLLOUT?"POLLOUT":"", mask&POLLIN?"POLLIN":"");
648 prev_mask = mask;
649 );
650 return mask;
651}
652
90276a1a 653static int sync_serial_ioctl(struct file *file,
51533b61
MS		 654 unsigned int cmd, unsigned long arg)
655{
656 int return_val = 0;
e908dfc3 657 int dma_w_size = regk_dma_set_w_size1;
d817be9c 658 int dev = iminor(file->f_path.dentry->d_inode);
e908dfc3 659 sync_port *port;
51533b61
MS		 660 reg_sser_rw_tr_cfg tr_cfg;
661 reg_sser_rw_rec_cfg rec_cfg;
662 reg_sser_rw_frm_cfg frm_cfg;
663 reg_sser_rw_cfg gen_cfg;
664 reg_sser_rw_intr_mask intr_mask;
665
e908dfc3 666 if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled)
51533b61
MS		 667 {
668 DEBUG(printk("Invalid minor %d\n", dev));
669 return -1;
670 }
671 port = &ports[dev];
672 spin_lock_irq(&port->lock);
673
674 tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg);
675 rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg);
676 frm_cfg = REG_RD(sser, port->regi_sser, rw_frm_cfg);
677 gen_cfg = REG_RD(sser, port->regi_sser, rw_cfg);
678 intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask);
679
680 switch(cmd)
681 {
682 case SSP_SPEED:
683 if (GET_SPEED(arg) == CODEC)
684 {
e908dfc3
JN		 685 unsigned int freq;
686
51533b61 687 gen_cfg.base_freq = regk_sser_f32;
e908dfc3
JN		 688
689 /* Clock divider will internally be
690 * gen_cfg.clk_div + 1.
691 */
692
693 freq = GET_FREQ(arg);
694 switch (freq) {
695 case FREQ_32kHz:
696 case FREQ_64kHz:
697 case FREQ_128kHz:
698 case FREQ_256kHz:
699 gen_cfg.clk_div = 125 *
700 (1 << (freq - FREQ_256kHz)) - 1;
701 break;
702 case FREQ_512kHz:
703 gen_cfg.clk_div = 62;
704 break;
705 case FREQ_1MHz:
706 case FREQ_2MHz:
707 case FREQ_4MHz:
708 gen_cfg.clk_div = 8 * (1 << freq) - 1;
709 break;
710 }
711 } else {
51533b61 712 gen_cfg.base_freq = regk_sser_f29_493;
e908dfc3
JN		 713 switch (GET_SPEED(arg)) {
714 case SSP150:
715 gen_cfg.clk_div = 29493000 / (150 * 8) - 1;
716 break;
717 case SSP300:
718 gen_cfg.clk_div = 29493000 / (300 * 8) - 1;
719 break;
720 case SSP600:
721 gen_cfg.clk_div = 29493000 / (600 * 8) - 1;
722 break;
723 case SSP1200:
724 gen_cfg.clk_div = 29493000 / (1200 * 8) - 1;
725 break;
726 case SSP2400:
727 gen_cfg.clk_div = 29493000 / (2400 * 8) - 1;
728 break;
729 case SSP4800:
730 gen_cfg.clk_div = 29493000 / (4800 * 8) - 1;
731 break;
732 case SSP9600:
733 gen_cfg.clk_div = 29493000 / (9600 * 8) - 1;
734 break;
735 case SSP19200:
736 gen_cfg.clk_div = 29493000 / (19200 * 8) - 1;
737 break;
738 case SSP28800:
739 gen_cfg.clk_div = 29493000 / (28800 * 8) - 1;
740 break;
741 case SSP57600:
742 gen_cfg.clk_div = 29493000 / (57600 * 8) - 1;
743 break;
744 case SSP115200:
745 gen_cfg.clk_div = 29493000 / (115200 * 8) - 1;
746 break;
747 case SSP230400:
748 gen_cfg.clk_div = 29493000 / (230400 * 8) - 1;
749 break;
750 case SSP460800:
751 gen_cfg.clk_div = 29493000 / (460800 * 8) - 1;
752 break;
753 case SSP921600:
754 gen_cfg.clk_div = 29493000 / (921600 * 8) - 1;
755 break;
756 case SSP3125000:
757 gen_cfg.base_freq = regk_sser_f100;
758 gen_cfg.clk_div = 100000000 / (3125000 * 8) - 1;
759 break;
51533b61
MS		 760
761 }
762 }
763 frm_cfg.wordrate = GET_WORD_RATE(arg);
764
765 break;
766 case SSP_MODE:
767 switch(arg)
768 {
769 case MASTER_OUTPUT:
770 port->output = 1;
771 port->input = 0;
e908dfc3
JN		 772 frm_cfg.out_on = regk_sser_tr;
773 frm_cfg.frame_pin_dir = regk_sser_out;
51533b61
MS		 774 gen_cfg.clk_dir = regk_sser_out;
775 break;
776 case SLAVE_OUTPUT:
777 port->output = 1;
778 port->input = 0;
e908dfc3 779 frm_cfg.frame_pin_dir = regk_sser_in;
51533b61
MS		 780 gen_cfg.clk_dir = regk_sser_in;
781 break;
782 case MASTER_INPUT:
783 port->output = 0;
784 port->input = 1;
e908dfc3
JN		 785 frm_cfg.frame_pin_dir = regk_sser_out;
786 frm_cfg.out_on = regk_sser_intern_tb;
51533b61
MS		 787 gen_cfg.clk_dir = regk_sser_out;
788 break;
789 case SLAVE_INPUT:
790 port->output = 0;
791 port->input = 1;
e908dfc3 792 frm_cfg.frame_pin_dir = regk_sser_in;
51533b61
MS		 793 gen_cfg.clk_dir = regk_sser_in;
794 break;
795 case MASTER_BIDIR:
796 port->output = 1;
797 port->input = 1;
e908dfc3
JN		 798 frm_cfg.frame_pin_dir = regk_sser_out;
799 frm_cfg.out_on = regk_sser_intern_tb;
51533b61
MS		 800 gen_cfg.clk_dir = regk_sser_out;
801 break;
802 case SLAVE_BIDIR:
803 port->output = 1;
804 port->input = 1;
e908dfc3 805 frm_cfg.frame_pin_dir = regk_sser_in;
51533b61
MS		 806 gen_cfg.clk_dir = regk_sser_in;
807 break;
808 default:
809 spin_unlock_irq(&port->lock);
810 return -EINVAL;
51533b61
MS		 811 }
812 if (!port->use_dma || (arg == MASTER_OUTPUT || arg == SLAVE_OUTPUT))
813 intr_mask.rdav = regk_sser_yes;
814 break;
815 case SSP_FRAME_SYNC:
e908dfc3
JN		 816 if (arg & NORMAL_SYNC) {
817 frm_cfg.rec_delay = 1;
51533b61 818 frm_cfg.tr_delay = 1;
e908dfc3 819 }
51533b61 820 else if (arg & EARLY_SYNC)
e908dfc3
JN		 821 frm_cfg.rec_delay = frm_cfg.tr_delay = 0;
822 else if (arg & SECOND_WORD_SYNC) {
823 frm_cfg.rec_delay = 7;
824 frm_cfg.tr_delay = 1;
825 }
51533b61
MS		 826
827 tr_cfg.bulk_wspace = frm_cfg.tr_delay;
828 frm_cfg.early_wend = regk_sser_yes;
829 if (arg & BIT_SYNC)
830 frm_cfg.type = regk_sser_edge;
831 else if (arg & WORD_SYNC)
832 frm_cfg.type = regk_sser_level;
833 else if (arg & EXTENDED_SYNC)
834 frm_cfg.early_wend = regk_sser_no;
835
836 if (arg & SYNC_ON)
837 frm_cfg.frame_pin_use = regk_sser_frm;
838 else if (arg & SYNC_OFF)
839 frm_cfg.frame_pin_use = regk_sser_gio0;
840
e908dfc3
JN		 841 dma_w_size = regk_dma_set_w_size2;
842 if (arg & WORD_SIZE_8) {
51533b61 843 rec_cfg.sample_size = tr_cfg.sample_size = 7;
e908dfc3
JN		 844 dma_w_size = regk_dma_set_w_size1;
845 } else if (arg & WORD_SIZE_12)
51533b61
MS		 846 rec_cfg.sample_size = tr_cfg.sample_size = 11;
847 else if (arg & WORD_SIZE_16)
848 rec_cfg.sample_size = tr_cfg.sample_size = 15;
849 else if (arg & WORD_SIZE_24)
850 rec_cfg.sample_size = tr_cfg.sample_size = 23;
851 else if (arg & WORD_SIZE_32)
852 rec_cfg.sample_size = tr_cfg.sample_size = 31;
853
854 if (arg & BIT_ORDER_MSB)
855 rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_msbfirst;
856 else if (arg & BIT_ORDER_LSB)
857 rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_lsbfirst;
858
e908dfc3
JN		 859 if (arg & FLOW_CONTROL_ENABLE) {
860 frm_cfg.status_pin_use = regk_sser_frm;
51533b61 861 rec_cfg.fifo_thr = regk_sser_thr16;
e908dfc3
JN		 862 } else if (arg & FLOW_CONTROL_DISABLE) {
863 frm_cfg.status_pin_use = regk_sser_gio0;
51533b61 864 rec_cfg.fifo_thr = regk_sser_inf;
e908dfc3 865 }
51533b61
MS		 866
867 if (arg & CLOCK_NOT_GATED)
868 gen_cfg.gate_clk = regk_sser_no;
869 else if (arg & CLOCK_GATED)
870 gen_cfg.gate_clk = regk_sser_yes;
871
872 break;
873 case SSP_IPOLARITY:
874 /* NOTE!! negedge is considered NORMAL */
875 if (arg & CLOCK_NORMAL)
876 rec_cfg.clk_pol = regk_sser_neg;
877 else if (arg & CLOCK_INVERT)
878 rec_cfg.clk_pol = regk_sser_pos;
879
880 if (arg & FRAME_NORMAL)
881 frm_cfg.level = regk_sser_pos_hi;
882 else if (arg & FRAME_INVERT)
883 frm_cfg.level = regk_sser_neg_lo;
884
885 if (arg & STATUS_NORMAL)
886 gen_cfg.hold_pol = regk_sser_pos;
887 else if (arg & STATUS_INVERT)
888 gen_cfg.hold_pol = regk_sser_neg;
889 break;
890 case SSP_OPOLARITY:
891 if (arg & CLOCK_NORMAL)
51533b61 892 gen_cfg.out_clk_pol = regk_sser_pos;
e908dfc3
JN		 893 else if (arg & CLOCK_INVERT)
894 gen_cfg.out_clk_pol = regk_sser_neg;
51533b61
MS		 895
896 if (arg & FRAME_NORMAL)
897 frm_cfg.level = regk_sser_pos_hi;
898 else if (arg & FRAME_INVERT)
899 frm_cfg.level = regk_sser_neg_lo;
900
901 if (arg & STATUS_NORMAL)
902 gen_cfg.hold_pol = regk_sser_pos;
903 else if (arg & STATUS_INVERT)
904 gen_cfg.hold_pol = regk_sser_neg;
905 break;
906 case SSP_SPI:
907 rec_cfg.fifo_thr = regk_sser_inf;
908 rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_msbfirst;
909 rec_cfg.sample_size = tr_cfg.sample_size = 7;
910 frm_cfg.frame_pin_use = regk_sser_frm;
911 frm_cfg.type = regk_sser_level;
912 frm_cfg.tr_delay = 1;
913 frm_cfg.level = regk_sser_neg_lo;
914 if (arg & SPI_SLAVE)
915 {
916 rec_cfg.clk_pol = regk_sser_neg;
917 gen_cfg.clk_dir = regk_sser_in;
918 port->input = 1;
919 port->output = 0;
920 }
921 else
922 {
923 gen_cfg.out_clk_pol = regk_sser_pos;
924 port->input = 0;
925 port->output = 1;
926 gen_cfg.clk_dir = regk_sser_out;
927 }
928 break;
929 case SSP_INBUFCHUNK:
930 break;
931 default:
932 return_val = -1;
933 }
934
935
e908dfc3 936 if (port->started) {
51533b61 937 rec_cfg.rec_en = port->input;
e908dfc3 938 gen_cfg.en = (port->output | port->input);
51533b61
MS		 939 }
940
941 REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
942 REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
943 REG_WR(sser, port->regi_sser, rw_frm_cfg, frm_cfg);
944 REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask);
945 REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg);
946
e908dfc3
JN		 947
948 if (cmd == SSP_FRAME_SYNC && (arg & (WORD_SIZE_8 | WORD_SIZE_12 |
949 WORD_SIZE_16 | WORD_SIZE_24 | WORD_SIZE_32))) {
950 int en = gen_cfg.en;
951 gen_cfg.en = 0;
952 REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg);
953 /* ##### Should DMA be stoped before we change dma size? */
954 DMA_WR_CMD(port->regi_dmain, dma_w_size);
955 DMA_WR_CMD(port->regi_dmaout, dma_w_size);
956 gen_cfg.en = en;
957 REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg);
958 }
959
51533b61
MS		 960 spin_unlock_irq(&port->lock);
961 return return_val;
962}
963
90276a1a
JN		 964static long sync_serial_ioctl(struct file *file,
965 unsigned int cmd, unsigned long arg)
966{
967 long ret;
968
969 lock_kernel();
970 ret = sync_serial_ioctl_unlocked(file, cmd, arg);
971 unlock_kernel();
972
973 return ret;
974}
975
e908dfc3
JN		 976/* NOTE: sync_serial_write does not support concurrency */
977static ssize_t sync_serial_write(struct file *file, const char *buf,
978 size_t count, loff_t *ppos)
51533b61 979{
d817be9c 980 int dev = iminor(file->f_path.dentry->d_inode);
51533b61 981 DECLARE_WAITQUEUE(wait, current);
e908dfc3
JN		 982 struct sync_port *port;
983 int trunc_count;
51533b61 984 unsigned long flags;
e908dfc3
JN		 985 int bytes_free;
986 int out_buf_count;
51533b61 987
e908dfc3
JN		 988 unsigned char *rd_ptr; /* First allocated byte in the buffer */
989 unsigned char *wr_ptr; /* First free byte in the buffer */
990 unsigned char *buf_stop_ptr; /* Last byte + 1 */
991
992 if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) {
51533b61
MS		 993 DEBUG(printk("Invalid minor %d\n", dev));
994 return -ENODEV;
995 }
996 port = &ports[dev];
997
e908dfc3
JN		 998 /* |<- OUT_BUFFER_SIZE ->|
999 * |<- out_buf_count ->|
1000 * |<- trunc_count ->| ...->|
1001 * ______________________________________________________
1002 * | free | data | free |
1003 * |_________|___________________|________________________|
1004 * ^ rd_ptr ^ wr_ptr
51533b61 1005 */
e908dfc3
JN		 1006 DEBUGWRITE(printk(KERN_DEBUG "W d%d c %lu a: %p c: %p\n",
1007 port->port_nbr, count, port->active_tr_descr,
1008 port->catch_tr_descr));
51533b61
MS		 1009
1010 /* Read variables that may be updated by interrupts */
1011 spin_lock_irqsave(&port->lock, flags);
e908dfc3
JN		 1012 rd_ptr = port->out_rd_ptr;
1013 out_buf_count = port->out_buf_count;
51533b61 1014 spin_unlock_irqrestore(&port->lock, flags);
51533b61 1015
e908dfc3
JN		 1016 /* Check if resources are available */
1017 if (port->tr_running &&
1018 ((port->use_dma && port->active_tr_descr == port->catch_tr_descr) ||
1019 out_buf_count >= OUT_BUFFER_SIZE)) {
1020 DEBUGWRITE(printk(KERN_DEBUG "sser%d full\n", dev));
1021 return -EAGAIN;
1022 }
1023
1024 buf_stop_ptr = port->out_buffer + OUT_BUFFER_SIZE;
1025
1026 /* Determine pointer to the first free byte, before copying. */
1027 wr_ptr = rd_ptr + out_buf_count;
1028 if (wr_ptr >= buf_stop_ptr)
1029 wr_ptr -= OUT_BUFFER_SIZE;
1030
1031 /* If we wrap the ring buffer, let the user space program handle it by
1032 * truncating the data. This could be more elegant, small buffer
1033 * fragments may occur.
1034 */
1035 bytes_free = OUT_BUFFER_SIZE - out_buf_count;
1036 if (wr_ptr + bytes_free > buf_stop_ptr)
1037 bytes_free = buf_stop_ptr - wr_ptr;
1038 trunc_count = (count < bytes_free) ? count : bytes_free;
51533b61 1039
e908dfc3 1040 if (copy_from_user(wr_ptr, buf, trunc_count))
51533b61
MS		 1041 return -EFAULT;
1042
e908dfc3
JN		 1043 DEBUGOUTBUF(printk(KERN_DEBUG "%-4d + %-4d = %-4d %p %p %p\n",
1044 out_buf_count, trunc_count,
1045 port->out_buf_count, port->out_buffer,
1046 wr_ptr, buf_stop_ptr));
51533b61
MS		 1047
1048 /* Make sure transmitter/receiver is running */
e908dfc3 1049 if (!port->started) {
51533b61 1050 reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg);
51533b61
MS		 1051 reg_sser_rw_rec_cfg rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg);
1052 cfg.en = regk_sser_yes;
51533b61
MS		 1053 rec_cfg.rec_en = port->input;
1054 REG_WR(sser, port->regi_sser, rw_cfg, cfg);
51533b61
MS		 1055 REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
1056 port->started = 1;
1057 }
1058
e908dfc3
JN		 1059 /* Setup wait if blocking */
1060 if (!(file->f_flags & O_NONBLOCK)) {
1061 add_wait_queue(&port->out_wait_q, &wait);
1062 set_current_state(TASK_INTERRUPTIBLE);
51533b61
MS		 1063 }
1064
51533b61 1065 spin_lock_irqsave(&port->lock, flags);
e908dfc3
JN		 1066 port->out_buf_count += trunc_count;
1067 if (port->use_dma) {
1068 start_dma_out(port, wr_ptr, trunc_count);
1069 } else if (!port->tr_running) {
1070 reg_sser_rw_intr_mask intr_mask;
1071 intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask);
1072 /* Start sender by writing data */
1073 send_word(port);
1074 /* and enable transmitter ready IRQ */
1075 intr_mask.trdy = 1;
1076 REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask);
51533b61
MS		 1077 }
1078 spin_unlock_irqrestore(&port->lock, flags);
e908dfc3
JN		 1079
1080 /* Exit if non blocking */
1081 if (file->f_flags & O_NONBLOCK) {
1082 DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu %08x\n",
1083 port->port_nbr, trunc_count,
1084 REG_RD_INT(dma, port->regi_dmaout, r_intr)));
1085 return trunc_count;
1086 }
1087
51533b61
MS		 1088 schedule();
1089 set_current_state(TASK_RUNNING);
1090 remove_wait_queue(&port->out_wait_q, &wait);
e908dfc3 1091
51533b61 1092 if (signal_pending(current))
51533b61 1093 return -EINTR;
cbca6634 1094
e908dfc3
JN		 1095 DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu\n",
1096 port->port_nbr, trunc_count));
1097 return trunc_count;
51533b61
MS		 1098}
1099
1100static ssize_t sync_serial_read(struct file * file, char * buf,
1101 size_t count, loff_t *ppos)
1102{
d817be9c 1103 int dev = iminor(file->f_path.dentry->d_inode);
51533b61
MS		 1104 int avail;
1105 sync_port *port;
1106 unsigned char* start;
1107 unsigned char* end;
1108 unsigned long flags;
1109
e908dfc3 1110 if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled)
51533b61
MS		 1111 {
1112 DEBUG(printk("Invalid minor %d\n", dev));
1113 return -ENODEV;
1114 }
1115 port = &ports[dev];
1116
1117 DEBUGREAD(printk("R%d c %d ri %lu wi %lu /%lu\n", dev, count, port->readp - port->flip, port->writep - port->flip, port->in_buffer_size));
1118
1119 if (!port->started)
1120 {
1121 reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg);
1122 reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg);
1123 reg_sser_rw_rec_cfg rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg);
1124 cfg.en = regk_sser_yes;
1125 tr_cfg.tr_en = regk_sser_yes;
1126 rec_cfg.rec_en = regk_sser_yes;
1127 REG_WR(sser, port->regi_sser, rw_cfg, cfg);
1128 REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
1129 REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
1130 port->started = 1;
1131 }
1132
51533b61
MS		 1133 /* Calculate number of available bytes */
1134 /* Save pointers to avoid that they are modified by interrupt */
1135 spin_lock_irqsave(&port->lock, flags);
1136 start = (unsigned char*)port->readp; /* cast away volatile */
1137 end = (unsigned char*)port->writep; /* cast away volatile */
1138 spin_unlock_irqrestore(&port->lock, flags);
1139 while ((start == end) && !port->full) /* No data */
1140 {
e908dfc3 1141 DEBUGREAD(printk(KERN_DEBUG "&"));
51533b61 1142 if (file->f_flags & O_NONBLOCK)
51533b61 1143 return -EAGAIN;
51533b61
MS		 1144
1145 interruptible_sleep_on(&port->in_wait_q);
1146 if (signal_pending(current))
51533b61 1147 return -EINTR;
e908dfc3 1148
51533b61
MS		 1149 spin_lock_irqsave(&port->lock, flags);
1150 start = (unsigned char*)port->readp; /* cast away volatile */
1151 end = (unsigned char*)port->writep; /* cast away volatile */
1152 spin_unlock_irqrestore(&port->lock, flags);
1153 }
1154
1155 /* Lazy read, never return wrapped data. */
1156 if (port->full)
1157 avail = port->in_buffer_size;
1158 else if (end > start)
1159 avail = end - start;
1160 else
1161 avail = port->flip + port->in_buffer_size - start;
1162
1163 count = count > avail ? avail : count;
1164 if (copy_to_user(buf, start, count))
1165 return -EFAULT;
1166 /* Disable interrupts while updating readp */
1167 spin_lock_irqsave(&port->lock, flags);
1168 port->readp += count;
1169 if (port->readp >= port->flip + port->in_buffer_size) /* Wrap? */
1170 port->readp = port->flip;
1171 port->full = 0;
1172 spin_unlock_irqrestore(&port->lock, flags);
1173 DEBUGREAD(printk("r %d\n", count));
1174 return count;
1175}
1176
1177static void send_word(sync_port* port)
1178{
1179 reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg);
1180 reg_sser_rw_tr_data tr_data = {0};
1181
1182 switch(tr_cfg.sample_size)
1183 {
1184 case 8:
e908dfc3
JN		 1185 port->out_buf_count--;
1186 tr_data.data = *port->out_rd_ptr++;
51533b61 1187 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
e908dfc3
JN		 1188 if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
1189 port->out_rd_ptr = port->out_buffer;
51533b61
MS		 1190 break;
1191 case 12:
1192 {
e908dfc3
JN		 1193 int data = (*port->out_rd_ptr++) << 8;
1194 data |= *port->out_rd_ptr++;
1195 port->out_buf_count -= 2;
51533b61
MS		 1196 tr_data.data = data;
1197 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
e908dfc3
JN		 1198 if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
1199 port->out_rd_ptr = port->out_buffer;
51533b61
MS		 1200 }
1201 break;
1202 case 16:
e908dfc3
JN		 1203 port->out_buf_count -= 2;
1204 tr_data.data = *(unsigned short *)port->out_rd_ptr;
51533b61 1205 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
e908dfc3
JN		 1206 port->out_rd_ptr += 2;
1207 if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
1208 port->out_rd_ptr = port->out_buffer;
51533b61
MS		 1209 break;
1210 case 24:
e908dfc3
JN		 1211 port->out_buf_count -= 3;
1212 tr_data.data = *(unsigned short *)port->out_rd_ptr;
51533b61 1213 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
e908dfc3
JN		 1214 port->out_rd_ptr += 2;
1215 tr_data.data = *port->out_rd_ptr++;
51533b61 1216 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
e908dfc3
JN		 1217 if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
1218 port->out_rd_ptr = port->out_buffer;
51533b61
MS		 1219 break;
1220 case 32:
e908dfc3
JN		 1221 port->out_buf_count -= 4;
1222 tr_data.data = *(unsigned short *)port->out_rd_ptr;
51533b61 1223 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
e908dfc3
JN		 1224 port->out_rd_ptr += 2;
1225 tr_data.data = *(unsigned short *)port->out_rd_ptr;
51533b61 1226 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
e908dfc3
JN		 1227 port->out_rd_ptr += 2;
1228 if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
1229 port->out_rd_ptr = port->out_buffer;
51533b61
MS		 1230 break;
1231 }
1232}
1233
e908dfc3
JN		 1234static void start_dma_out(struct sync_port *port,
1235 const char *data, int count)
51533b61 1236{
e908dfc3
JN		 1237 port->active_tr_descr->buf = (char *) virt_to_phys((char *) data);
1238 port->active_tr_descr->after = port->active_tr_descr->buf + count;
1239 port->active_tr_descr->intr = 1;
1240
1241 port->active_tr_descr->eol = 1;
1242 port->prev_tr_descr->eol = 0;
1243
1244 DEBUGTRDMA(printk(KERN_DEBUG "Inserting eolr:%p eol@:%p\n",
1245 port->prev_tr_descr, port->active_tr_descr));
1246 port->prev_tr_descr = port->active_tr_descr;
1247 port->active_tr_descr = phys_to_virt((int) port->active_tr_descr->next);
1248
1249 if (!port->tr_running) {
1250 reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser,
1251 rw_tr_cfg);
51533b61 1252
e908dfc3
JN		 1253 port->out_context.next = 0;
1254 port->out_context.saved_data =
1255 (dma_descr_data *)virt_to_phys(port->prev_tr_descr);
1256 port->out_context.saved_data_buf = port->prev_tr_descr->buf;
1257
1258 DMA_START_CONTEXT(port->regi_dmaout,
1259 virt_to_phys((char *)&port->out_context));
1260
1261 tr_cfg.tr_en = regk_sser_yes;
1262 REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
1263 DEBUGTRDMA(printk(KERN_DEBUG "dma s\n"););
1264 } else {
1265 DMA_CONTINUE_DATA(port->regi_dmaout);
1266 DEBUGTRDMA(printk(KERN_DEBUG "dma c\n"););
1267 }
51533b61 1268
e908dfc3 1269 port->tr_running = 1;
51533b61
MS		 1270}
1271
e908dfc3 1272static void start_dma_in(sync_port *port)
51533b61
MS		 1273{
1274 int i;
e908dfc3 1275 char *buf;
51533b61
MS		 1276 port->writep = port->flip;
1277
e908dfc3 1278 if (port->writep > port->flip + port->in_buffer_size) {
51533b61
MS		 1279 panic("Offset too large in sync serial driver\n");
1280 return;
1281 }
1282 buf = (char*)virt_to_phys(port->in_buffer);
e908dfc3 1283 for (i = 0; i < NBR_IN_DESCR; i++) {
51533b61
MS		 1284 port->in_descr[i].buf = buf;
1285 port->in_descr[i].after = buf + port->inbufchunk;
1286 port->in_descr[i].intr = 1;
1287 port->in_descr[i].next = (dma_descr_data*)virt_to_phys(&port->in_descr[i+1]);
1288 port->in_descr[i].buf = buf;
1289 buf += port->inbufchunk;
1290 }
1291 /* Link the last descriptor to the first */
1292 port->in_descr[i-1].next = (dma_descr_data*)virt_to_phys(&port->in_descr[0]);
1293 port->in_descr[i-1].eol = regk_sser_yes;
1294 port->next_rx_desc = &port->in_descr[0];
e908dfc3 1295 port->prev_rx_desc = &port->in_descr[NBR_IN_DESCR - 1];
51533b61
MS		 1296 port->in_context.saved_data = (dma_descr_data*)virt_to_phys(&port->in_descr[0]);
1297 port->in_context.saved_data_buf = port->in_descr[0].buf;
1298 DMA_START_CONTEXT(port->regi_dmain, virt_to_phys(&port->in_context));
1299}
1300
1301#ifdef SYNC_SER_DMA
e908dfc3 1302static irqreturn_t tr_interrupt(int irq, void *dev_id)
51533b61
MS		 1303{
1304 reg_dma_r_masked_intr masked;
1305 reg_dma_rw_ack_intr ack_intr = {.data = regk_dma_yes};
e908dfc3 1306 reg_dma_rw_stat stat;
51533b61 1307 int i;
51533b61 1308 int found = 0;
e908dfc3 1309 int stop_sser = 0;
51533b61 1310
e908dfc3 1311 for (i = 0; i < NBR_PORTS; i++) {
51533b61 1312 sync_port *port = &ports[i];
e908dfc3 1313 if (!port->enabled || !port->use_dma)
51533b61
MS		 1314 continue;
1315
e908dfc3 1316 /* IRQ active for the port? */
51533b61 1317 masked = REG_RD(dma, port->regi_dmaout, r_masked_intr);
e908dfc3
JN		 1318 if (!masked.data)
1319 continue;
51533b61 1320
e908dfc3
JN		 1321 found = 1;
1322
1323 /* Check if we should stop the DMA transfer */
1324 stat = REG_RD(dma, port->regi_dmaout, rw_stat);
1325 if (stat.list_state == regk_dma_data_at_eol)
1326 stop_sser = 1;
1327
1328 /* Clear IRQ */
1329 REG_WR(dma, port->regi_dmaout, rw_ack_intr, ack_intr);
1330
1331 if (!stop_sser) {
1332 /* The DMA has completed a descriptor, EOL was not
1333 * encountered, so step relevant descriptor and
1334 * datapointers forward. */
1335 int sent;
1336 sent = port->catch_tr_descr->after -
1337 port->catch_tr_descr->buf;
1338 DEBUGTXINT(printk(KERN_DEBUG "%-4d - %-4d = %-4d\t"
1339 "in descr %p (ac: %p)\n",
1340 port->out_buf_count, sent,
1341 port->out_buf_count - sent,
1342 port->catch_tr_descr,
1343 port->active_tr_descr););
1344 port->out_buf_count -= sent;
1345 port->catch_tr_descr =
1346 phys_to_virt((int) port->catch_tr_descr->next);
1347 port->out_rd_ptr =
1348 phys_to_virt((int) port->catch_tr_descr->buf);
1349 } else {
1350 int i, sent;
1351 /* EOL handler.
1352 * Note that if an EOL was encountered during the irq
1353 * locked section of sync_ser_write the DMA will be
1354 * restarted and the eol flag will be cleared.
1355 * The remaining descriptors will be traversed by
1356 * the descriptor interrupts as usual.
1357 */
1358 i = 0;
1359 while (!port->catch_tr_descr->eol) {
1360 sent = port->catch_tr_descr->after -
1361 port->catch_tr_descr->buf;
1362 DEBUGOUTBUF(printk(KERN_DEBUG
1363 "traversing descr %p -%d (%d)\n",
1364 port->catch_tr_descr,
1365 sent,
1366 port->out_buf_count));
1367 port->out_buf_count -= sent;
1368 port->catch_tr_descr = phys_to_virt(
1369 (int)port->catch_tr_descr->next);
1370 i++;
1371 if (i >= NBR_OUT_DESCR) {
1372 /* TODO: Reset and recover */
1373 panic("sync_serial: missing eol");
1374 }
51533b61 1375 }
e908dfc3
JN		 1376 sent = port->catch_tr_descr->after -
1377 port->catch_tr_descr->buf;
1378 DEBUGOUTBUF(printk(KERN_DEBUG
1379 "eol at descr %p -%d (%d)\n",
1380 port->catch_tr_descr,
1381 sent,
1382 port->out_buf_count));
1383
1384 port->out_buf_count -= sent;
1385
1386 /* Update read pointer to first free byte, we
1387 * may already be writing data there. */
1388 port->out_rd_ptr =
1389 phys_to_virt((int) port->catch_tr_descr->after);
1390 if (port->out_rd_ptr > port->out_buffer +
1391 OUT_BUFFER_SIZE)
1392 port->out_rd_ptr = port->out_buffer;
1393
1394 reg_sser_rw_tr_cfg tr_cfg =
1395 REG_RD(sser, port->regi_sser, rw_tr_cfg);
1396 DEBUGTXINT(printk(KERN_DEBUG
1397 "tr_int DMA stop %d, set catch @ %p\n",
1398 port->out_buf_count,
1399 port->active_tr_descr));
1400 if (port->out_buf_count != 0)
1401 printk(KERN_CRIT "sync_ser: buffer not "
1402 "empty after eol.\n");
1403 port->catch_tr_descr = port->active_tr_descr;
1404 port->tr_running = 0;
1405 tr_cfg.tr_en = regk_sser_no;
1406 REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
51533b61 1407 }
e908dfc3
JN		 1408 /* wake up the waiting process */
1409 wake_up_interruptible(&port->out_wait_q);
51533b61
MS		 1410 }
1411 return IRQ_RETVAL(found);
1412} /* tr_interrupt */
1413
e908dfc3 1414static irqreturn_t rx_interrupt(int irq, void *dev_id)
51533b61
MS		 1415{
1416 reg_dma_r_masked_intr masked;
1417 reg_dma_rw_ack_intr ack_intr = {.data = regk_dma_yes};
1418
1419 int i;
1420 int found = 0;
1421
e908dfc3 1422 for (i = 0; i < NBR_PORTS; i++)
51533b61
MS		 1423 {
1424 sync_port *port = &ports[i];
1425
1426 if (!port->enabled || !port->use_dma )
1427 continue;
1428
1429 masked = REG_RD(dma, port->regi_dmain, r_masked_intr);
1430
1431 if (masked.data) /* Descriptor interrupt */
1432 {
1433 found = 1;
1434 while (REG_RD(dma, port->regi_dmain, rw_data) !=
1435 virt_to_phys(port->next_rx_desc)) {
e908dfc3 1436 DEBUGRXINT(printk(KERN_DEBUG "!"));
51533b61
MS		 1437 if (port->writep + port->inbufchunk > port->flip + port->in_buffer_size) {
1438 int first_size = port->flip + port->in_buffer_size - port->writep;
1439 memcpy((char*)port->writep, phys_to_virt((unsigned)port->next_rx_desc->buf), first_size);
1440 memcpy(port->flip, phys_to_virt((unsigned)port->next_rx_desc->buf+first_size), port->inbufchunk - first_size);
1441 port->writep = port->flip + port->inbufchunk - first_size;
1442 } else {
1443 memcpy((char*)port->writep,
1444 phys_to_virt((unsigned)port->next_rx_desc->buf),
1445 port->inbufchunk);
1446 port->writep += port->inbufchunk;
1447 if (port->writep >= port->flip + port->in_buffer_size)
1448 port->writep = port->flip;
1449 }
1450 if (port->writep == port->readp)
1451 {
1452 port->full = 1;
1453 }
1454
e908dfc3
JN		 1455 port->next_rx_desc->eol = 1;
1456 port->prev_rx_desc->eol = 0;
1457 /* Cache bug workaround */
1458 flush_dma_descr(port->prev_rx_desc, 0);
1459 port->prev_rx_desc = port->next_rx_desc;
51533b61 1460 port->next_rx_desc = phys_to_virt((unsigned)port->next_rx_desc->next);
e908dfc3
JN		 1461 /* Cache bug workaround */
1462 flush_dma_descr(port->prev_rx_desc, 1);
1463 /* wake up the waiting process */
1464 wake_up_interruptible(&port->in_wait_q);
51533b61
MS		 1465 DMA_CONTINUE(port->regi_dmain);
1466 REG_WR(dma, port->regi_dmain, rw_ack_intr, ack_intr);
1467
1468 }
1469 }
1470 }
1471 return IRQ_RETVAL(found);
1472} /* rx_interrupt */
1473#endif /* SYNC_SER_DMA */
1474
1475#ifdef SYNC_SER_MANUAL
e908dfc3 1476static irqreturn_t manual_interrupt(int irq, void *dev_id)
51533b61
MS		 1477{
1478 int i;
1479 int found = 0;
1480 reg_sser_r_masked_intr masked;
1481
e908dfc3 1482 for (i = 0; i < NBR_PORTS; i++)
51533b61 1483 {
e908dfc3 1484 sync_port *port = &ports[i];
51533b61
MS		 1485
1486 if (!port->enabled || port->use_dma)
1487 {
1488 continue;
1489 }
1490
1491 masked = REG_RD(sser, port->regi_sser, r_masked_intr);
1492 if (masked.rdav) /* Data received? */
1493 {
1494 reg_sser_rw_rec_cfg rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg);
1495 reg_sser_r_rec_data data = REG_RD(sser, port->regi_sser, r_rec_data);
1496 found = 1;
1497 /* Read data */
1498 switch(rec_cfg.sample_size)
1499 {
1500 case 8:
1501 *port->writep++ = data.data & 0xff;
1502 break;
1503 case 12:
1504 *port->writep = (data.data & 0x0ff0) >> 4;
1505 *(port->writep + 1) = data.data & 0x0f;
1506 port->writep+=2;
1507 break;
1508 case 16:
1509 *(unsigned short*)port->writep = data.data;
1510 port->writep+=2;
1511 break;
1512 case 24:
1513 *(unsigned int*)port->writep = data.data;
1514 port->writep+=3;
1515 break;
1516 case 32:
1517 *(unsigned int*)port->writep = data.data;
1518 port->writep+=4;
1519 break;
1520 }
1521
1522 if (port->writep >= port->flip + port->in_buffer_size) /* Wrap? */
1523 port->writep = port->flip;
1524 if (port->writep == port->readp) {
1525 /* receive buffer overrun, discard oldest data
1526 */
1527 port->readp++;
1528 if (port->readp >= port->flip + port->in_buffer_size) /* Wrap? */
1529 port->readp = port->flip;
1530 }
1531 if (sync_data_avail(port) >= port->inbufchunk)
1532 wake_up_interruptible(&port->in_wait_q); /* Wake up application */
1533 }
1534
1535 if (masked.trdy) /* Transmitter ready? */
1536 {
1537 found = 1;
e908dfc3 1538 if (port->out_buf_count > 0) /* More data to send */
51533b61
MS		 1539 send_word(port);
1540 else /* transmission finished */
1541 {
1542 reg_sser_rw_intr_mask intr_mask;
1543 intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask);
1544 intr_mask.trdy = 0;
1545 REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask);
1546 wake_up_interruptible(&port->out_wait_q); /* Wake up application */
1547 }
1548 }
1549 }
1550 return IRQ_RETVAL(found);
1551}
1552#endif
1553
1554module_init(etrax_sync_serial_init);
Clone of davem's net-next-2.6 tree