[net-next-2.6.git] / arch / cris / arch-v10 / mm / fault.c

/*
 *  linux/arch/cris/mm/fault.c
 *
 *  Low level bus fault handler
 *
 *
 *  Copyright (C) 2000-2007  Axis Communications AB
 *
 *  Authors:  Bjorn Wesen
 *
 */

#include <linux/mm.h>
#include <asm/uaccess.h>
#include <asm/pgtable.h>
#include <arch/svinto.h>
#include <asm/mmu_context.h>

/* debug of low-level TLB reload */
#undef DEBUG

#ifdef DEBUG
#define D(x) x
#else
#define D(x)
#endif

extern const struct exception_table_entry
	*search_exception_tables(unsigned long addr);

asmlinkage void do_page_fault(unsigned long address, struct pt_regs *regs,
                              int protection, int writeaccess);

/* fast TLB-fill fault handler
 * this is called from entry.S with interrupts disabled
 */

void
handle_mmu_bus_fault(struct pt_regs *regs)
{
	int cause;
	int select;
#ifdef DEBUG
	int index;
	int page_id;
	int acc, inv;
#endif
	pgd_t* pgd = (pgd_t*)per_cpu(current_pgd, smp_processor_id());
	pmd_t *pmd;
	pte_t pte;
	int miss, we, writeac;
	unsigned long address;
	unsigned long flags;

	cause = *R_MMU_CAUSE;

	address = cause & PAGE_MASK; /* get faulting address */
	select = *R_TLB_SELECT;

#ifdef DEBUG
	page_id = IO_EXTRACT(R_MMU_CAUSE,  page_id,   cause);
	acc     = IO_EXTRACT(R_MMU_CAUSE,  acc_excp,  cause);
	inv     = IO_EXTRACT(R_MMU_CAUSE,  inv_excp,  cause);
	index   = IO_EXTRACT(R_TLB_SELECT, index,     select);
#endif
	miss    = IO_EXTRACT(R_MMU_CAUSE,  miss_excp, cause);
	we      = IO_EXTRACT(R_MMU_CAUSE,  we_excp,   cause);
	writeac = IO_EXTRACT(R_MMU_CAUSE,  wr_rd,     cause);

	D(printk("bus_fault from IRP 0x%lx: addr 0x%lx, miss %d, inv %d, we %d, acc %d, dx %d pid %d\n",
		 regs->irp, address, miss, inv, we, acc, index, page_id));

	/* leave it to the MM system fault handler */
	if (miss)
		do_page_fault(address, regs, 0, writeac);
        else
		do_page_fault(address, regs, 1, we);

        /* Reload TLB with new entry to avoid an extra miss exception.
	 * do_page_fault may have flushed the TLB so we have to restore
	 * the MMU registers.
	 */
	local_save_flags(flags);
	local_irq_disable();
	pmd = (pmd_t *)(pgd + pgd_index(address));
	if (pmd_none(*pmd))
		goto exit;
	pte = *pte_offset_kernel(pmd, address);
	if (!pte_present(pte))
		goto exit;
	*R_TLB_SELECT = select;
	*R_TLB_HI = cause;
	*R_TLB_LO = pte_val(pte);
exit:
	local_irq_restore(flags);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/cris/mm/fault.c
	3	*
	4	* Low level bus fault handler
	5	*
	6	*
40316c1f JN	7	* Copyright (C) 2000-2007 Axis Communications AB
	8	*
	9	* Authors: Bjorn Wesen
1da177e4	10	*
1da177e4 LT	11	*/
	12
	13	#include <linux/mm.h>
	14	#include <asm/uaccess.h>
	15	#include <asm/pgtable.h>
556dcee7	16	#include <arch/svinto.h>
8d20a541	17	#include <asm/mmu_context.h>
1da177e4 LT	18
	19	/* debug of low-level TLB reload */
	20	#undef DEBUG
	21
	22	#ifdef DEBUG
	23	#define D(x) x
	24	#else
	25	#define D(x)
	26	#endif
	27
1da177e4 LT	28	extern const struct exception_table_entry
	29	*search_exception_tables(unsigned long addr);
	30
	31	asmlinkage void do_page_fault(unsigned long address, struct pt_regs *regs,
	32	int protection, int writeaccess);
	33
	34	/* fast TLB-fill fault handler
	35	* this is called from entry.S with interrupts disabled
	36	*/
	37
	38	void
	39	handle_mmu_bus_fault(struct pt_regs *regs)
	40	{
	41	int cause;
	42	int select;
	43	#ifdef DEBUG
	44	int index;
	45	int page_id;
	46	int acc, inv;
	47	#endif
8d20a541	48	pgd_t* pgd = (pgd_t*)per_cpu(current_pgd, smp_processor_id());
1da177e4 LT	49	pmd_t *pmd;
	50	pte_t pte;
	51	int miss, we, writeac;
	52	unsigned long address;
	53	unsigned long flags;
	54
	55	cause = *R_MMU_CAUSE;
	56
	57	address = cause & PAGE_MASK; /* get faulting address */
	58	select = *R_TLB_SELECT;
	59
	60	#ifdef DEBUG
	61	page_id = IO_EXTRACT(R_MMU_CAUSE, page_id, cause);
	62	acc = IO_EXTRACT(R_MMU_CAUSE, acc_excp, cause);
40316c1f	63	inv = IO_EXTRACT(R_MMU_CAUSE, inv_excp, cause);
1da177e4 LT	64	index = IO_EXTRACT(R_TLB_SELECT, index, select);
	65	#endif
	66	miss = IO_EXTRACT(R_MMU_CAUSE, miss_excp, cause);
	67	we = IO_EXTRACT(R_MMU_CAUSE, we_excp, cause);
	68	writeac = IO_EXTRACT(R_MMU_CAUSE, wr_rd, cause);
	69
	70	D(printk("bus_fault from IRP 0x%lx: addr 0x%lx, miss %d, inv %d, we %d, acc %d, dx %d pid %d\n",
	71	regs->irp, address, miss, inv, we, acc, index, page_id));
	72
	73	/* leave it to the MM system fault handler */
	74	if (miss)
	75	do_page_fault(address, regs, 0, writeac);
	76	else
	77	do_page_fault(address, regs, 1, we);
	78
	79	/* Reload TLB with new entry to avoid an extra miss exception.
	80	* do_page_fault may have flushed the TLB so we have to restore
	81	* the MMU registers.
	82	*/
	83	local_save_flags(flags);
	84	local_irq_disable();
	85	pmd = (pmd_t *)(pgd + pgd_index(address));
	86	if (pmd_none(*pmd))
40316c1f	87	goto exit;
1da177e4 LT	88	pte = *pte_offset_kernel(pmd, address);
1da177e4 LT	89	if (!pte_present(pte))
40316c1f	90	goto exit;
1da177e4 LT	91	*R_TLB_SELECT = select;
	92	*R_TLB_HI = cause;
	93	*R_TLB_LO = pte_val(pte);
40316c1f	94	exit:
1da177e4 LT	95	local_irq_restore(flags);
1da177e4 LT	96	}