[net-next-2.6.git] / arch / cris / arch-v10 / kernel / time.c

/*
 *  linux/arch/cris/arch-v10/kernel/time.c
 *
 *  Copyright (C) 1991, 1992, 1995  Linus Torvalds
 *  Copyright (C) 1999-2002 Axis Communications AB
 *
 */

#include <linux/timex.h>
#include <linux/time.h>
#include <linux/jiffies.h>
#include <linux/interrupt.h>
#include <linux/swap.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <asm/arch/svinto.h>
#include <asm/types.h>
#include <asm/signal.h>
#include <asm/io.h>
#include <asm/delay.h>
#include <asm/rtc.h>
#include <asm/irq_regs.h>

/* define this if you need to use print_timestamp */
/* it will make jiffies at 96 hz instead of 100 hz though */
#undef USE_CASCADE_TIMERS

extern void update_xtime_from_cmos(void);
extern int set_rtc_mmss(unsigned long nowtime);
extern int setup_irq(int, struct irqaction *);
extern int have_rtc;

unsigned long get_ns_in_jiffie(void)
{
	unsigned char timer_count, t1;
	unsigned short presc_count;
	unsigned long ns;
	unsigned long flags;

	local_irq_save(flags);
	timer_count = *R_TIMER0_DATA;
	presc_count = *R_TIM_PRESC_STATUS;  
	/* presc_count might be wrapped */
	t1 = *R_TIMER0_DATA;

	if (timer_count != t1){
		/* it wrapped, read prescaler again...  */
		presc_count = *R_TIM_PRESC_STATUS;
		timer_count = t1;
	}
	local_irq_restore(flags);
	if (presc_count >= PRESCALE_VALUE/2 ){
		presc_count =  PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
	} else {
		presc_count =  PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
	}

	ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) + 
	     ( (presc_count) * (1000000000/PRESCALE_FREQ));
	return ns;
}

unsigned long do_slow_gettimeoffset(void)
{
	unsigned long count, t1;
	unsigned long usec_count = 0;
	unsigned short presc_count;

	static unsigned long count_p = TIMER0_DIV;/* for the first call after boot */
	static unsigned long jiffies_p = 0;

	/*
	 * cache volatile jiffies temporarily; we have IRQs turned off. 
	 */
	unsigned long jiffies_t;

	/* The timer interrupt comes from Etrax timer 0. In order to get
	 * better precision, we check the current value. It might have
	 * underflowed already though.
	 */

#ifndef CONFIG_SVINTO_SIM
	/* Not available in the xsim simulator. */
	count = *R_TIMER0_DATA;
	presc_count = *R_TIM_PRESC_STATUS;  
	/* presc_count might be wrapped */
	t1 = *R_TIMER0_DATA;
	if (count != t1){
		/* it wrapped, read prescaler again...  */
		presc_count = *R_TIM_PRESC_STATUS;
		count = t1;
	}
#else
	count = 0;
	presc_count = 0;
#endif

 	jiffies_t = jiffies;

	/*
	 * avoiding timer inconsistencies (they are rare, but they happen)...
	 * there are one problem that must be avoided here:
	 *  1. the timer counter underflows
	 */
	if( jiffies_t == jiffies_p ) {
		if( count > count_p ) {
			/* Timer wrapped, use new count and prescale 
			 * increase the time corresponding to one jiffie
			 */
			usec_count = 1000000/HZ;
		}
	} else
		jiffies_p = jiffies_t;
        count_p = count;
	if (presc_count >= PRESCALE_VALUE/2 ){
		presc_count =  PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
	} else {
		presc_count =  PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
	}
	/* Convert timer value to usec */
	usec_count += ( (TIMER0_DIV - count) * (1000000/HZ)/TIMER0_DIV ) +
	              (( (presc_count) * (1000000000/PRESCALE_FREQ))/1000);

	return usec_count;
}

/* Excerpt from the Etrax100 HSDD about the built-in watchdog:
 *
 * 3.10.4 Watchdog timer

 * When the watchdog timer is started, it generates an NMI if the watchdog
 * isn't restarted or stopped within 0.1 s. If it still isn't restarted or
 * stopped after an additional 3.3 ms, the watchdog resets the chip.
 * The watchdog timer is stopped after reset. The watchdog timer is controlled
 * by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit
 * and a 3-bit key value. The effect of writing to the R_WATCHDOG register is
 * described in the table below:
 * 
 *   Watchdog    Value written:
 *   state:      To enable:  To key:      Operation:
 *   --------    ----------  -------      ----------
 *   stopped         0         X          No effect.
 *   stopped         1       key_val      Start watchdog with key = key_val.
 *   started         0       ~key         Stop watchdog
 *   started         1       ~key         Restart watchdog with key = ~key.
 *   started         X       new_key_val  Change key to new_key_val.
 * 
 * Note: '~' is the bitwise NOT operator.
 * 
 */

/* right now, starting the watchdog is the same as resetting it */
#define start_watchdog reset_watchdog

#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
static int watchdog_key = 0;  /* arbitrary number */
#endif

/* number of pages to consider "out of memory". it is normal that the memory
 * is used though, so put this really low.
 */

#define WATCHDOG_MIN_FREE_PAGES 8

void
reset_watchdog(void)
{
#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
	/* only keep watchdog happy as long as we have memory left! */
	if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
		/* reset the watchdog with the inverse of the old key */
		watchdog_key ^= 0x7; /* invert key, which is 3 bits */
		*R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
			IO_STATE(R_WATCHDOG, enable, start);
	}
#endif
}

/* stop the watchdog - we still need the correct key */

void 
stop_watchdog(void)
{
#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
	watchdog_key ^= 0x7; /* invert key, which is 3 bits */
	*R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
		IO_STATE(R_WATCHDOG, enable, stop);
#endif	
}

/* last time the cmos clock got updated */
static long last_rtc_update = 0;

/*
 * timer_interrupt() needs to keep up the real-time clock,
 * as well as call the "do_timer()" routine every clocktick
 */

//static unsigned short myjiff; /* used by our debug routine print_timestamp */

extern void cris_do_profile(struct pt_regs *regs);

static inline irqreturn_t
timer_interrupt(int irq, void *dev_id)
{
	struct pt_regs *regs = get_irq_regs();
	/* acknowledge the timer irq */

#ifdef USE_CASCADE_TIMERS
	*R_TIMER_CTRL =
		IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
		IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
		IO_STATE( R_TIMER_CTRL, i1, clr) |
		IO_STATE( R_TIMER_CTRL, tm1, run) |
		IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
		IO_STATE( R_TIMER_CTRL, i0, clr) |
		IO_STATE( R_TIMER_CTRL, tm0, run) |
		IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
#else
	*R_TIMER_CTRL = r_timer_ctrl_shadow | 
		IO_STATE(R_TIMER_CTRL, i0, clr);
#endif

	/* reset watchdog otherwise it resets us! */
	reset_watchdog();
	
	/* Update statistics. */
	update_process_times(user_mode(regs));

	/* call the real timer interrupt handler */

	do_timer(1);
	
        cris_do_profile(regs); /* Save profiling information */

	/*
	 * If we have an externally synchronized Linux clock, then update
	 * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
	 * called as close as possible to 500 ms before the new second starts.
	 *
	 * The division here is not time critical since it will run once in 
	 * 11 minutes
	 */
	if (ntp_synced() &&
	    xtime.tv_sec > last_rtc_update + 660 &&
	    (xtime.tv_nsec / 1000) >= 500000 - (tick_nsec / 1000) / 2 &&
	    (xtime.tv_nsec / 1000) <= 500000 + (tick_nsec / 1000) / 2) {
		if (set_rtc_mmss(xtime.tv_sec) == 0)
			last_rtc_update = xtime.tv_sec;
		else
			last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
	}
        return IRQ_HANDLED;
}

/* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain
 * it needs to be IRQF_DISABLED to make the jiffies update work properly
 */

static struct irqaction irq2  = {
	.handler = timer_interrupt,
	.flags = IRQF_SHARED | IRQF_DISABLED,
	.mask = CPU_MASK_NONE,
	.name = "timer",
};

void __init
time_init(void)
{	
	/* probe for the RTC and read it if it exists 
	 * Before the RTC can be probed the loops_per_usec variable needs 
	 * to be initialized to make usleep work. A better value for 
	 * loops_per_usec is calculated by the kernel later once the 
	 * clock has started.  
	 */
	loops_per_usec = 50;

	if(RTC_INIT() < 0) {
		/* no RTC, start at 1980 */
		xtime.tv_sec = 0;
		xtime.tv_nsec = 0;
		have_rtc = 0;
	} else {		
		/* get the current time */
		have_rtc = 1;
		update_xtime_from_cmos();
	}

	/*
	 * Initialize wall_to_monotonic such that adding it to xtime will yield zero, the
	 * tv_nsec field must be normalized (i.e., 0 <= nsec < NSEC_PER_SEC).
	 */
	set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);

	/* Setup the etrax timers
	 * Base frequency is 25000 hz, divider 250 -> 100 HZ
	 * In normal mode, we use timer0, so timer1 is free. In cascade
	 * mode (which we sometimes use for debugging) both timers are used.
	 * Remember that linux/timex.h contains #defines that rely on the
	 * timer settings below (hz and divide factor) !!!
	 */
	
#ifdef USE_CASCADE_TIMERS
	*R_TIMER_CTRL =
		IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
		IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
		IO_STATE( R_TIMER_CTRL, i1, nop) |
		IO_STATE( R_TIMER_CTRL, tm1, stop_ld) |
		IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
		IO_STATE( R_TIMER_CTRL, i0, nop) |
		IO_STATE( R_TIMER_CTRL, tm0, stop_ld) |
		IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
	
	*R_TIMER_CTRL = r_timer_ctrl_shadow = 
		IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
		IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
		IO_STATE( R_TIMER_CTRL, i1, nop) |
		IO_STATE( R_TIMER_CTRL, tm1, run) |
		IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
		IO_STATE( R_TIMER_CTRL, i0, nop) |
		IO_STATE( R_TIMER_CTRL, tm0, run) |
		IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
#else
	*R_TIMER_CTRL = 
		IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      | 
		IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
		IO_STATE(R_TIMER_CTRL, i1,        nop)      | 
		IO_STATE(R_TIMER_CTRL, tm1,       stop_ld)  |
		IO_STATE(R_TIMER_CTRL, clksel1,   c19k2Hz)  |
		IO_STATE(R_TIMER_CTRL, i0,        nop)      |
		IO_STATE(R_TIMER_CTRL, tm0,       stop_ld)  |
		IO_STATE(R_TIMER_CTRL, clksel0,   flexible);
	
	*R_TIMER_CTRL = r_timer_ctrl_shadow =
		IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      | 
		IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
		IO_STATE(R_TIMER_CTRL, i1,        nop)      |
		IO_STATE(R_TIMER_CTRL, tm1,       run)      |
		IO_STATE(R_TIMER_CTRL, clksel1,   c19k2Hz)  |
		IO_STATE(R_TIMER_CTRL, i0,        nop)      |
		IO_STATE(R_TIMER_CTRL, tm0,       run)      |
		IO_STATE(R_TIMER_CTRL, clksel0,   flexible);

	*R_TIMER_PRESCALE = PRESCALE_VALUE;
#endif

	*R_IRQ_MASK0_SET =
		IO_STATE(R_IRQ_MASK0_SET, timer0, set); /* unmask the timer irq */
	
	/* now actually register the timer irq handler that calls timer_interrupt() */
	
	setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */

	/* enable watchdog if we should use one */

#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
	printk("Enabling watchdog...\n");
	start_watchdog();

	/* If we use the hardware watchdog, we want to trap it as an NMI
	   and dump registers before it resets us.  For this to happen, we
	   must set the "m" NMI enable flag (which once set, is unset only
	   when an NMI is taken).

	   The same goes for the external NMI, but that doesn't have any
	   driver or infrastructure support yet.  */
	asm ("setf m");

	*R_IRQ_MASK0_SET =
		IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
	*R_VECT_MASK_SET =
		IO_STATE(R_VECT_MASK_SET, nmi, set);
#endif
}
Commit	Line	Data
3244c77b	1	/*
1da177e4 LT	2	* linux/arch/cris/arch-v10/kernel/time.c
	3	*
	4	* Copyright (C) 1991, 1992, 1995 Linus Torvalds
	5	* Copyright (C) 1999-2002 Axis Communications AB
	6	*
	7	*/
	8
1da177e4 LT	9	#include <linux/timex.h>
	10	#include <linux/time.h>
	11	#include <linux/jiffies.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/swap.h>
	14	#include <linux/sched.h>
	15	#include <linux/init.h>
a1056873	16	#include <linux/mm.h>
1da177e4 LT	17	#include <asm/arch/svinto.h>
	18	#include <asm/types.h>
	19	#include <asm/signal.h>
	20	#include <asm/io.h>
	21	#include <asm/delay.h>
	22	#include <asm/rtc.h>
3244c77b	23	#include <asm/irq_regs.h>
1da177e4 LT	24
	25	/* define this if you need to use print_timestamp */
	26	/* it will make jiffies at 96 hz instead of 100 hz though */
	27	#undef USE_CASCADE_TIMERS
	28
	29	extern void update_xtime_from_cmos(void);
	30	extern int set_rtc_mmss(unsigned long nowtime);
	31	extern int setup_irq(int, struct irqaction *);
	32	extern int have_rtc;
	33
	34	unsigned long get_ns_in_jiffie(void)
	35	{
	36	unsigned char timer_count, t1;
	37	unsigned short presc_count;
	38	unsigned long ns;
	39	unsigned long flags;
	40
	41	local_irq_save(flags);
1da177e4 LT	42	timer_count = *R_TIMER0_DATA;
	43	presc_count = *R_TIM_PRESC_STATUS;
	44	/* presc_count might be wrapped */
	45	t1 = *R_TIMER0_DATA;
	46
	47	if (timer_count != t1){
	48	/* it wrapped, read prescaler again... */
	49	presc_count = *R_TIM_PRESC_STATUS;
	50	timer_count = t1;
	51	}
	52	local_irq_restore(flags);
	53	if (presc_count >= PRESCALE_VALUE/2 ){
	54	presc_count = PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
	55	} else {
	56	presc_count = PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
	57	}
	58
	59	ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) +
	60	( (presc_count) * (1000000000/PRESCALE_FREQ));
	61	return ns;
	62	}
	63
	64	unsigned long do_slow_gettimeoffset(void)
	65	{
	66	unsigned long count, t1;
	67	unsigned long usec_count = 0;
	68	unsigned short presc_count;
	69
	70	static unsigned long count_p = TIMER0_DIV;/* for the first call after boot */
	71	static unsigned long jiffies_p = 0;
	72
	73	/*
	74	* cache volatile jiffies temporarily; we have IRQs turned off.
	75	*/
	76	unsigned long jiffies_t;
	77
	78	/* The timer interrupt comes from Etrax timer 0. In order to get
	79	* better precision, we check the current value. It might have
	80	* underflowed already though.
	81	*/
	82
	83	#ifndef CONFIG_SVINTO_SIM
	84	/* Not available in the xsim simulator. */
	85	count = *R_TIMER0_DATA;
	86	presc_count = *R_TIM_PRESC_STATUS;
	87	/* presc_count might be wrapped */
	88	t1 = *R_TIMER0_DATA;
	89	if (count != t1){
	90	/* it wrapped, read prescaler again... */
	91	presc_count = *R_TIM_PRESC_STATUS;
	92	count = t1;
	93	}
	94	#else
	95	count = 0;
	96	presc_count = 0;
	97	#endif
	98
	99	jiffies_t = jiffies;
	100
	101	/*
	102	* avoiding timer inconsistencies (they are rare, but they happen)...
	103	* there are one problem that must be avoided here:
	104	* 1. the timer counter underflows
	105	*/
106	if( jiffies_t == jiffies_p ) {
107	if( count > count_p ) {
108	/* Timer wrapped, use new count and prescale
109	* increase the time corresponding to one jiffie
110	*/
111	usec_count = 1000000/HZ;
112	}
113	} else
114	jiffies_p = jiffies_t;
115	count_p = count;
116	if (presc_count >= PRESCALE_VALUE/2 ){
117	presc_count = PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
118	} else {
119	presc_count = PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
120	}
121	/* Convert timer value to usec */
122	usec_count += ( (TIMER0_DIV - count) * (1000000/HZ)/TIMER0_DIV ) +
123	(( (presc_count) * (1000000000/PRESCALE_FREQ))/1000);
124
125	return usec_count;
126	}
127
128	/* Excerpt from the Etrax100 HSDD about the built-in watchdog:
129	*
130	* 3.10.4 Watchdog timer
131
132	* When the watchdog timer is started, it generates an NMI if the watchdog
133	* isn't restarted or stopped within 0.1 s. If it still isn't restarted or
134	* stopped after an additional 3.3 ms, the watchdog resets the chip.
135	* The watchdog timer is stopped after reset. The watchdog timer is controlled
136	* by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit
137	* and a 3-bit key value. The effect of writing to the R_WATCHDOG register is
138	* described in the table below:
139	*
140	* Watchdog Value written:
141	* state: To enable: To key: Operation:
142	* -------- ---------- ------- ----------
143	* stopped 0 X No effect.
144	* stopped 1 key_val Start watchdog with key = key_val.
145	* started 0 ~key Stop watchdog
146	* started 1 ~key Restart watchdog with key = ~key.
147	* started X new_key_val Change key to new_key_val.
148	*
149	* Note: '~' is the bitwise NOT operator.
150	*
151	*/
152
153	/* right now, starting the watchdog is the same as resetting it */
154	#define start_watchdog reset_watchdog
155
156	#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
157	static int watchdog_key = 0; /* arbitrary number */
158	#endif
159
160	/* number of pages to consider "out of memory". it is normal that the memory
161	* is used though, so put this really low.
162	*/
163
164	#define WATCHDOG_MIN_FREE_PAGES 8
165
166	void
167	reset_watchdog(void)
168	{
169	#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
170	/* only keep watchdog happy as long as we have memory left! */
171	if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
172	/* reset the watchdog with the inverse of the old key */
173	watchdog_key ^= 0x7; /* invert key, which is 3 bits */
174	*R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) \|
175	IO_STATE(R_WATCHDOG, enable, start);
176	}
177	#endif
178	}
179
180	/* stop the watchdog - we still need the correct key */
181
182	void
183	stop_watchdog(void)
184	{
185	#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
186	watchdog_key ^= 0x7; /* invert key, which is 3 bits */
187	*R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) \|
188	IO_STATE(R_WATCHDOG, enable, stop);
189	#endif
190	}
191
192	/* last time the cmos clock got updated */
193	static long last_rtc_update = 0;
194
195	/*
196	* timer_interrupt() needs to keep up the real-time clock,
197	* as well as call the "do_timer()" routine every clocktick
198	*/
199
200	//static unsigned short myjiff; /* used by our debug routine print_timestamp */
201
202	extern void cris_do_profile(struct pt_regs *regs);
203
204	static inline irqreturn_t
3244c77b	205	timer_interrupt(int irq, void *dev_id)
1da177e4	206	{
3244c77b	207	struct pt_regs *regs = get_irq_regs();
1da177e4 LT	208	/* acknowledge the timer irq */
	209
	210	#ifdef USE_CASCADE_TIMERS
	211	*R_TIMER_CTRL =
	212	IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) \|
	213	IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) \|
	214	IO_STATE( R_TIMER_CTRL, i1, clr) \|
	215	IO_STATE( R_TIMER_CTRL, tm1, run) \|
	216	IO_STATE( R_TIMER_CTRL, clksel1, cascade0) \|
	217	IO_STATE( R_TIMER_CTRL, i0, clr) \|
	218	IO_STATE( R_TIMER_CTRL, tm0, run) \|
	219	IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
	220	#else
	221	*R_TIMER_CTRL = r_timer_ctrl_shadow \|
	222	IO_STATE(R_TIMER_CTRL, i0, clr);
	223	#endif
	224
	225	/* reset watchdog otherwise it resets us! */
1da177e4 LT	226	reset_watchdog();
1da177e4 LT	227
3244c77b JN	228	/* Update statistics. */
	229	update_process_times(user_mode(regs));
	230
1da177e4 LT	231	/* call the real timer interrupt handler */
1da177e4 LT	232
3171a030	233	do_timer(1);
1da177e4 LT	234
	235	cris_do_profile(regs); /* Save profiling information */
	236
	237	/*
	238	* If we have an externally synchronized Linux clock, then update
	239	* CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
	240	* called as close as possible to 500 ms before the new second starts.
	241	*
	242	* The division here is not time critical since it will run once in
	243	* 11 minutes
	244	*/
b149ee22	245	if (ntp_synced() &&
1da177e4 LT	246	xtime.tv_sec > last_rtc_update + 660 &&
	247	(xtime.tv_nsec / 1000) >= 500000 - (tick_nsec / 1000) / 2 &&
	248	(xtime.tv_nsec / 1000) <= 500000 + (tick_nsec / 1000) / 2) {
	249	if (set_rtc_mmss(xtime.tv_sec) == 0)
	250	last_rtc_update = xtime.tv_sec;
	251	else
	252	last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
	253	}
	254	return IRQ_HANDLED;
	255	}
	256
aa7135ff TG	257	/* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain
aa7135ff TG	258	* it needs to be IRQF_DISABLED to make the jiffies update work properly
1da177e4 LT	259	*/
1da177e4 LT	260
e5f71781 TG	261	static struct irqaction irq2 = {
	262	.handler = timer_interrupt,
	263	.flags = IRQF_SHARED \| IRQF_DISABLED,
	264	.mask = CPU_MASK_NONE,
	265	.name = "timer",
	266	};
1da177e4 LT	267
	268	void __init
	269	time_init(void)
	270	{
	271	/* probe for the RTC and read it if it exists
	272	* Before the RTC can be probed the loops_per_usec variable needs
	273	* to be initialized to make usleep work. A better value for
	274	* loops_per_usec is calculated by the kernel later once the
	275	* clock has started.
	276	*/
	277	loops_per_usec = 50;
	278
	279	if(RTC_INIT() < 0) {
	280	/* no RTC, start at 1980 */
	281	xtime.tv_sec = 0;
	282	xtime.tv_nsec = 0;
	283	have_rtc = 0;
	284	} else {
	285	/* get the current time */
	286	have_rtc = 1;
	287	update_xtime_from_cmos();
	288	}
	289
	290	/*
	291	* Initialize wall_to_monotonic such that adding it to xtime will yield zero, the
	292	* tv_nsec field must be normalized (i.e., 0 <= nsec < NSEC_PER_SEC).
	293	*/
	294	set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
	295
	296	/* Setup the etrax timers
	297	* Base frequency is 25000 hz, divider 250 -> 100 HZ
	298	* In normal mode, we use timer0, so timer1 is free. In cascade
	299	* mode (which we sometimes use for debugging) both timers are used.
	300	* Remember that linux/timex.h contains #defines that rely on the
	301	* timer settings below (hz and divide factor) !!!
	302	*/
	303
	304	#ifdef USE_CASCADE_TIMERS
	305	*R_TIMER_CTRL =
	306	IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) \|
	307	IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) \|
	308	IO_STATE( R_TIMER_CTRL, i1, nop) \|
	309	IO_STATE( R_TIMER_CTRL, tm1, stop_ld) \|
	310	IO_STATE( R_TIMER_CTRL, clksel1, cascade0) \|
	311	IO_STATE( R_TIMER_CTRL, i0, nop) \|
	312	IO_STATE( R_TIMER_CTRL, tm0, stop_ld) \|
	313	IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
	314
	315	*R_TIMER_CTRL = r_timer_ctrl_shadow =
	316	IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) \|
	317	IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) \|
	318	IO_STATE( R_TIMER_CTRL, i1, nop) \|
	319	IO_STATE( R_TIMER_CTRL, tm1, run) \|
	320	IO_STATE( R_TIMER_CTRL, clksel1, cascade0) \|
	321	IO_STATE( R_TIMER_CTRL, i0, nop) \|
	322	IO_STATE( R_TIMER_CTRL, tm0, run) \|
	323	IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
	324	#else
	325	*R_TIMER_CTRL =
	326	IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) \|
	327	IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) \|
	328	IO_STATE(R_TIMER_CTRL, i1, nop) \|
	329	IO_STATE(R_TIMER_CTRL, tm1, stop_ld) \|
	330	IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) \|
331	IO_STATE(R_TIMER_CTRL, i0, nop) \|
332	IO_STATE(R_TIMER_CTRL, tm0, stop_ld) \|
333	IO_STATE(R_TIMER_CTRL, clksel0, flexible);
334
335	*R_TIMER_CTRL = r_timer_ctrl_shadow =
336	IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) \|
337	IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) \|
338	IO_STATE(R_TIMER_CTRL, i1, nop) \|
339	IO_STATE(R_TIMER_CTRL, tm1, run) \|
340	IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) \|
341	IO_STATE(R_TIMER_CTRL, i0, nop) \|
342	IO_STATE(R_TIMER_CTRL, tm0, run) \|
343	IO_STATE(R_TIMER_CTRL, clksel0, flexible);
344
345	*R_TIMER_PRESCALE = PRESCALE_VALUE;
346	#endif
347
348	*R_IRQ_MASK0_SET =
349	IO_STATE(R_IRQ_MASK0_SET, timer0, set); /* unmask the timer irq */
350
351	/* now actually register the timer irq handler that calls timer_interrupt() */
352
353	setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */
354
355	/* enable watchdog if we should use one */
356
357	#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
358	printk("Enabling watchdog...\n");
359	start_watchdog();
360
361	/* If we use the hardware watchdog, we want to trap it as an NMI
362	and dump registers before it resets us. For this to happen, we
363	must set the "m" NMI enable flag (which once set, is unset only
364	when an NMI is taken).
365
366	The same goes for the external NMI, but that doesn't have any
367	driver or infrastructure support yet. */
368	asm ("setf m");
369
370	*R_IRQ_MASK0_SET =
371	IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
372	*R_VECT_MASK_SET =
373	IO_STATE(R_VECT_MASK_SET, nmi, set);
374	#endif
375	}